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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <vscale x 2 x i1> @isnan_nxv2f16(<vscale x 2 x half> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: isnan_nxv2f16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma11; CHECK-NEXT: vfclass.v v8, v8, v0.t12; CHECK-NEXT: li a0, 76813; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma14; CHECK-NEXT: vand.vx v8, v8, a015; CHECK-NEXT: vmsne.vi v0, v8, 016; CHECK-NEXT: ret17 %1 = call <vscale x 2 x i1> @llvm.vp.is.fpclass.nxv2f16(<vscale x 2 x half> %x, i32 3, <vscale x 2 x i1> %m, i32 %evl) ; nan18 ret <vscale x 2 x i1> %119}20 21define <vscale x 2 x i1> @isnan_nxv2f16_unmasked(<vscale x 2 x half> %x, i32 zeroext %evl) {22; CHECK-LABEL: isnan_nxv2f16_unmasked:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma25; CHECK-NEXT: vfclass.v v8, v826; CHECK-NEXT: li a0, 76827; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma28; CHECK-NEXT: vand.vx v8, v8, a029; CHECK-NEXT: vmsne.vi v0, v8, 030; CHECK-NEXT: ret31 %1 = call <vscale x 2 x i1> @llvm.vp.is.fpclass.nxv2f16(<vscale x 2 x half> %x, i32 3, <vscale x 2 x i1> splat (i1 true), i32 %evl) ; nan32 ret <vscale x 2 x i1> %133}34 35define <vscale x 2 x i1> @isnan_nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {36; CHECK-LABEL: isnan_nxv2f32:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma39; CHECK-NEXT: vfclass.v v8, v8, v0.t40; CHECK-NEXT: li a0, 92741; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma42; CHECK-NEXT: vand.vx v8, v8, a043; CHECK-NEXT: vmsne.vi v0, v8, 044; CHECK-NEXT: ret45 %1 = call <vscale x 2 x i1> @llvm.vp.is.fpclass.nxv2f32(<vscale x 2 x float> %x, i32 639, <vscale x 2 x i1> %m, i32 %evl)46 ret <vscale x 2 x i1> %147}48 49define <vscale x 2 x i1> @isnan_nxv2f32_unmasked(<vscale x 2 x float> %x, i32 zeroext %evl) {50; CHECK-LABEL: isnan_nxv2f32_unmasked:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma53; CHECK-NEXT: vfclass.v v8, v854; CHECK-NEXT: li a0, 92755; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma56; CHECK-NEXT: vand.vx v8, v8, a057; CHECK-NEXT: vmsne.vi v0, v8, 058; CHECK-NEXT: ret59 %1 = call <vscale x 2 x i1> @llvm.vp.is.fpclass.nxv2f32(<vscale x 2 x float> %x, i32 639, <vscale x 2 x i1> splat (i1 true), i32 %evl)60 ret <vscale x 2 x i1> %161}62 63define <vscale x 4 x i1> @isnan_nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {64; CHECK-LABEL: isnan_nxv4f32:65; CHECK: # %bb.0:66; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma67; CHECK-NEXT: vfclass.v v8, v8, v0.t68; CHECK-NEXT: li a0, 76869; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma70; CHECK-NEXT: vand.vx v8, v8, a071; CHECK-NEXT: vmsne.vi v0, v8, 072; CHECK-NEXT: ret73 %1 = call <vscale x 4 x i1> @llvm.vp.is.fpclass.nxv4f32(<vscale x 4 x float> %x, i32 3, <vscale x 4 x i1> %m, i32 %evl) ; nan74 ret <vscale x 4 x i1> %175}76 77define <vscale x 4 x i1> @isnan_nxv4f32_unmasked(<vscale x 4 x float> %x, i32 zeroext %evl) {78; CHECK-LABEL: isnan_nxv4f32_unmasked:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma81; CHECK-NEXT: vfclass.v v8, v882; CHECK-NEXT: li a0, 76883; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma84; CHECK-NEXT: vand.vx v8, v8, a085; CHECK-NEXT: vmsne.vi v0, v8, 086; CHECK-NEXT: ret87 %1 = call <vscale x 4 x i1> @llvm.vp.is.fpclass.nxv4f32(<vscale x 4 x float> %x, i32 3, <vscale x 4 x i1> splat (i1 true), i32 %evl) ; nan88 ret <vscale x 4 x i1> %189}90 91define <vscale x 8 x i1> @isnan_nxv8f32(<vscale x 8 x float> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {92; CHECK-LABEL: isnan_nxv8f32:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma95; CHECK-NEXT: vfclass.v v8, v8, v0.t96; CHECK-NEXT: li a0, 51297; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma98; CHECK-NEXT: vmseq.vx v0, v8, a099; CHECK-NEXT: ret100 %1 = call <vscale x 8 x i1> @llvm.vp.is.fpclass.nxv8f32(<vscale x 8 x float> %x, i32 2, <vscale x 8 x i1> %m, i32 %evl)101 ret <vscale x 8 x i1> %1102}103 104define <vscale x 8 x i1> @isnan_nxv8f32_unmasked(<vscale x 8 x float> %x, i32 zeroext %evl) {105; CHECK-LABEL: isnan_nxv8f32_unmasked:106; CHECK: # %bb.0:107; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma108; CHECK-NEXT: vfclass.v v8, v8109; CHECK-NEXT: li a0, 512110; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma111; CHECK-NEXT: vmseq.vx v0, v8, a0112; CHECK-NEXT: ret113 %1 = call <vscale x 8 x i1> @llvm.vp.is.fpclass.nxv8f32(<vscale x 8 x float> %x, i32 2, <vscale x 8 x i1> splat (i1 true), i32 %evl)114 ret <vscale x 8 x i1> %1115}116 117define <vscale x 16 x i1> @isnan_nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 zeroext %evl) {118; CHECK-LABEL: isnan_nxv16f32:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma121; CHECK-NEXT: vfclass.v v8, v8, v0.t122; CHECK-NEXT: li a0, 256123; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma124; CHECK-NEXT: vmseq.vx v0, v8, a0125; CHECK-NEXT: ret126 %1 = call <vscale x 16 x i1> @llvm.vp.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 1, <vscale x 16 x i1> %m, i32 %evl)127 ret <vscale x 16 x i1> %1128}129 130define <vscale x 16 x i1> @isnan_nxv16f32_unmasked(<vscale x 16 x float> %x, i32 zeroext %evl) {131; CHECK-LABEL: isnan_nxv16f32_unmasked:132; CHECK: # %bb.0:133; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma134; CHECK-NEXT: vfclass.v v8, v8135; CHECK-NEXT: li a0, 256136; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma137; CHECK-NEXT: vmseq.vx v0, v8, a0138; CHECK-NEXT: ret139 %1 = call <vscale x 16 x i1> @llvm.vp.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 1, <vscale x 16 x i1> splat (i1 true), i32 %evl)140 ret <vscale x 16 x i1> %1141}142 143define <vscale x 2 x i1> @isnormal_nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {144; CHECK-LABEL: isnormal_nxv2f64:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma147; CHECK-NEXT: vfclass.v v8, v8, v0.t148; CHECK-NEXT: li a0, 129149; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma150; CHECK-NEXT: vand.vx v8, v8, a0151; CHECK-NEXT: vmsne.vi v0, v8, 0152; CHECK-NEXT: ret153 %1 = call <vscale x 2 x i1> @llvm.vp.is.fpclass.nxv2f64(<vscale x 2 x double> %x, i32 516, <vscale x 2 x i1> %m, i32 %evl) ; 0x204 = "inf"154 ret <vscale x 2 x i1> %1155}156 157define <vscale x 2 x i1> @isnormal_nxv2f64_unmasked(<vscale x 2 x double> %x, i32 zeroext %evl) {158; CHECK-LABEL: isnormal_nxv2f64_unmasked:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma161; CHECK-NEXT: vfclass.v v8, v8162; CHECK-NEXT: li a0, 129163; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma164; CHECK-NEXT: vand.vx v8, v8, a0165; CHECK-NEXT: vmsne.vi v0, v8, 0166; CHECK-NEXT: ret167 %1 = call <vscale x 2 x i1> @llvm.vp.is.fpclass.nxv2f64(<vscale x 2 x double> %x, i32 516, <vscale x 2 x i1> splat (i1 true), i32 %evl) ; 0x204 = "inf"168 ret <vscale x 2 x i1> %1169}170 171define <vscale x 4 x i1> @isposinf_nxv4f64(<vscale x 4 x double> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {172; CHECK-LABEL: isposinf_nxv4f64:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma175; CHECK-NEXT: vfclass.v v8, v8, v0.t176; CHECK-NEXT: li a0, 128177; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma178; CHECK-NEXT: vmseq.vx v0, v8, a0179; CHECK-NEXT: ret180 %1 = call <vscale x 4 x i1> @llvm.vp.is.fpclass.nxv4f64(<vscale x 4 x double> %x, i32 512, <vscale x 4 x i1> %m, i32 %evl) ; 0x200 = "+inf"181 ret <vscale x 4 x i1> %1182}183 184define <vscale x 4 x i1> @isposinf_nxv4f64_unmasked(<vscale x 4 x double> %x, i32 zeroext %evl) {185; CHECK-LABEL: isposinf_nxv4f64_unmasked:186; CHECK: # %bb.0:187; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma188; CHECK-NEXT: vfclass.v v8, v8189; CHECK-NEXT: li a0, 128190; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma191; CHECK-NEXT: vmseq.vx v0, v8, a0192; CHECK-NEXT: ret193 %1 = call <vscale x 4 x i1> @llvm.vp.is.fpclass.nxv4f64(<vscale x 4 x double> %x, i32 512, <vscale x 4 x i1> splat (i1 true), i32 %evl) ; 0x200 = "+inf"194 ret <vscale x 4 x i1> %1195}196 197define <vscale x 8 x i1> @isneginf_nxv8f64(<vscale x 8 x double> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {198; CHECK-LABEL: isneginf_nxv8f64:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma201; CHECK-NEXT: vfclass.v v8, v8, v0.t202; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma203; CHECK-NEXT: vmseq.vi v0, v8, 1204; CHECK-NEXT: ret205 %1 = call <vscale x 8 x i1> @llvm.vp.is.fpclass.nxv8f64(<vscale x 8 x double> %x, i32 4, <vscale x 8 x i1> %m, i32 %evl) ; "-inf"206 ret <vscale x 8 x i1> %1207}208 209define <vscale x 8 x i1> @isneginf_nxv8f64_unmasked(<vscale x 8 x double> %x, i32 zeroext %evl) {210; CHECK-LABEL: isneginf_nxv8f64_unmasked:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma213; CHECK-NEXT: vfclass.v v8, v8214; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma215; CHECK-NEXT: vmseq.vi v0, v8, 1216; CHECK-NEXT: ret217 %1 = call <vscale x 8 x i1> @llvm.vp.is.fpclass.nxv8f64(<vscale x 8 x double> %x, i32 4, <vscale x 8 x i1> splat (i1 true), i32 %evl) ; "-inf"218 ret <vscale x 8 x i1> %1219}220 221