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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i16> @intrinsic_vfclass_v_nxv1i16_nxv1f16(8; CHECK-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vfclass.v v8, v812; CHECK-NEXT: ret13 <vscale x 1 x half> %0,14 iXLen %1) nounwind {15entry:16 %a = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16(17 <vscale x 1 x i16> poison,18 <vscale x 1 x half> %0,19 iXLen %1)20 21 ret <vscale x 1 x i16> %a22}23 24define <vscale x 1 x i16> @intrinsic_vfclass_mask_v_nxv1i16_nxv1f16(25; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i16_nxv1f16:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu28; CHECK-NEXT: vfclass.v v8, v9, v0.t29; CHECK-NEXT: ret30 <vscale x 1 x i16> %0,31 <vscale x 1 x half> %1,32 <vscale x 1 x i1> %2,33 iXLen %3) nounwind {34entry:35 %a = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16(36 <vscale x 1 x i16> %0,37 <vscale x 1 x half> %1,38 <vscale x 1 x i1> %2,39 iXLen %3, iXLen 0)40 41 ret <vscale x 1 x i16> %a42}43 44define <vscale x 2 x i16> @intrinsic_vfclass_v_nxv2i16_nxv2f16(45; CHECK-LABEL: intrinsic_vfclass_v_nxv2i16_nxv2f16:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma48; CHECK-NEXT: vfclass.v v8, v849; CHECK-NEXT: ret50 <vscale x 2 x half> %0,51 iXLen %1) nounwind {52entry:53 %a = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2i16(54 <vscale x 2 x i16> poison,55 <vscale x 2 x half> %0,56 iXLen %1)57 58 ret <vscale x 2 x i16> %a59}60 61define <vscale x 2 x i16> @intrinsic_vfclass_mask_v_nxv2i16_nxv2f16(62; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i16_nxv2f16:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu65; CHECK-NEXT: vfclass.v v8, v9, v0.t66; CHECK-NEXT: ret67 <vscale x 2 x i16> %0,68 <vscale x 2 x half> %1,69 <vscale x 2 x i1> %2,70 iXLen %3) nounwind {71entry:72 %a = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2i16(73 <vscale x 2 x i16> %0,74 <vscale x 2 x half> %1,75 <vscale x 2 x i1> %2,76 iXLen %3, iXLen 0)77 78 ret <vscale x 2 x i16> %a79}80 81define <vscale x 4 x i16> @intrinsic_vfclass_v_nxv4i16_nxv4f16(82; CHECK-LABEL: intrinsic_vfclass_v_nxv4i16_nxv4f16:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma85; CHECK-NEXT: vfclass.v v8, v886; CHECK-NEXT: ret87 <vscale x 4 x half> %0,88 iXLen %1) nounwind {89entry:90 %a = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4i16(91 <vscale x 4 x i16> poison,92 <vscale x 4 x half> %0,93 iXLen %1)94 95 ret <vscale x 4 x i16> %a96}97 98define <vscale x 4 x i16> @intrinsic_vfclass_mask_v_nxv4i16_nxv4f16(99; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i16_nxv4f16:100; CHECK: # %bb.0: # %entry101; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu102; CHECK-NEXT: vfclass.v v8, v9, v0.t103; CHECK-NEXT: ret104 <vscale x 4 x i16> %0,105 <vscale x 4 x half> %1,106 <vscale x 4 x i1> %2,107 iXLen %3) nounwind {108entry:109 %a = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4i16(110 <vscale x 4 x i16> %0,111 <vscale x 4 x half> %1,112 <vscale x 4 x i1> %2,113 iXLen %3, iXLen 0)114 115 ret <vscale x 4 x i16> %a116}117 118define <vscale x 8 x i16> @intrinsic_vfclass_v_nxv8i16_nxv8f16(119; CHECK-LABEL: intrinsic_vfclass_v_nxv8i16_nxv8f16:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma122; CHECK-NEXT: vfclass.v v8, v8123; CHECK-NEXT: ret124 <vscale x 8 x half> %0,125 iXLen %1) nounwind {126entry:127 %a = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8i16(128 <vscale x 8 x i16> poison,129 <vscale x 8 x half> %0,130 iXLen %1)131 132 ret <vscale x 8 x i16> %a133}134 135define <vscale x 8 x i16> @intrinsic_vfclass_mask_v_nxv8i16_nxv8f16(136; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i16_nxv8f16:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu139; CHECK-NEXT: vfclass.v v8, v10, v0.t140; CHECK-NEXT: ret141 <vscale x 8 x i16> %0,142 <vscale x 8 x half> %1,143 <vscale x 8 x i1> %2,144 iXLen %3) nounwind {145entry:146 %a = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8i16(147 <vscale x 8 x i16> %0,148 <vscale x 8 x half> %1,149 <vscale x 8 x i1> %2,150 iXLen %3, iXLen 0)151 152 ret <vscale x 8 x i16> %a153}154 155define <vscale x 16 x i16> @intrinsic_vfclass_v_nxv16i16_nxv16f16(156; CHECK-LABEL: intrinsic_vfclass_v_nxv16i16_nxv16f16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma159; CHECK-NEXT: vfclass.v v8, v8160; CHECK-NEXT: ret161 <vscale x 16 x half> %0,162 iXLen %1) nounwind {163entry:164 %a = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16i16(165 <vscale x 16 x i16> poison,166 <vscale x 16 x half> %0,167 iXLen %1)168 169 ret <vscale x 16 x i16> %a170}171 172define <vscale x 16 x i16> @intrinsic_vfclass_mask_v_nxv16i16_nxv16f16(173; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i16_nxv16f16:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu176; CHECK-NEXT: vfclass.v v8, v12, v0.t177; CHECK-NEXT: ret178 <vscale x 16 x i16> %0,179 <vscale x 16 x half> %1,180 <vscale x 16 x i1> %2,181 iXLen %3) nounwind {182entry:183 %a = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16i16(184 <vscale x 16 x i16> %0,185 <vscale x 16 x half> %1,186 <vscale x 16 x i1> %2,187 iXLen %3, iXLen 0)188 189 ret <vscale x 16 x i16> %a190}191 192define <vscale x 32 x i16> @intrinsic_vfclass_v_nxv32i16_nxv32f16(193; CHECK-LABEL: intrinsic_vfclass_v_nxv32i16_nxv32f16:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma196; CHECK-NEXT: vfclass.v v8, v8197; CHECK-NEXT: ret198 <vscale x 32 x half> %0,199 iXLen %1) nounwind {200entry:201 %a = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32i16(202 <vscale x 32 x i16> poison,203 <vscale x 32 x half> %0,204 iXLen %1)205 206 ret <vscale x 32 x i16> %a207}208 209define <vscale x 32 x i16> @intrinsic_vfclass_mask_v_nxv32i16_nxv32f16(210; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv32i16_nxv32f16:211; CHECK: # %bb.0: # %entry212; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu213; CHECK-NEXT: vfclass.v v8, v16, v0.t214; CHECK-NEXT: ret215 <vscale x 32 x i16> %0,216 <vscale x 32 x half> %1,217 <vscale x 32 x i1> %2,218 iXLen %3) nounwind {219entry:220 %a = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32i16(221 <vscale x 32 x i16> %0,222 <vscale x 32 x half> %1,223 <vscale x 32 x i1> %2,224 iXLen %3, iXLen 0)225 226 ret <vscale x 32 x i16> %a227}228 229define <vscale x 1 x i32> @intrinsic_vfclass_v_nxv1i32_nxv1f32(230; CHECK-LABEL: intrinsic_vfclass_v_nxv1i32_nxv1f32:231; CHECK: # %bb.0: # %entry232; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma233; CHECK-NEXT: vfclass.v v8, v8234; CHECK-NEXT: ret235 <vscale x 1 x float> %0,236 iXLen %1) nounwind {237entry:238 %a = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1i32(239 <vscale x 1 x i32> poison,240 <vscale x 1 x float> %0,241 iXLen %1)242 243 ret <vscale x 1 x i32> %a244}245 246define <vscale x 1 x i32> @intrinsic_vfclass_mask_v_nxv1i32_nxv1f32(247; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i32_nxv1f32:248; CHECK: # %bb.0: # %entry249; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu250; CHECK-NEXT: vfclass.v v8, v9, v0.t251; CHECK-NEXT: ret252 <vscale x 1 x i32> %0,253 <vscale x 1 x float> %1,254 <vscale x 1 x i1> %2,255 iXLen %3) nounwind {256entry:257 %a = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1i32(258 <vscale x 1 x i32> %0,259 <vscale x 1 x float> %1,260 <vscale x 1 x i1> %2,261 iXLen %3, iXLen 0)262 263 ret <vscale x 1 x i32> %a264}265 266define <vscale x 2 x i32> @intrinsic_vfclass_v_nxv2i32_nxv2f32(267; CHECK-LABEL: intrinsic_vfclass_v_nxv2i32_nxv2f32:268; CHECK: # %bb.0: # %entry269; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma270; CHECK-NEXT: vfclass.v v8, v8271; CHECK-NEXT: ret272 <vscale x 2 x float> %0,273 iXLen %1) nounwind {274entry:275 %a = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2i32(276 <vscale x 2 x i32> poison,277 <vscale x 2 x float> %0,278 iXLen %1)279 280 ret <vscale x 2 x i32> %a281}282 283define <vscale x 2 x i32> @intrinsic_vfclass_mask_v_nxv2i32_nxv2f32(284; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i32_nxv2f32:285; CHECK: # %bb.0: # %entry286; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu287; CHECK-NEXT: vfclass.v v8, v9, v0.t288; CHECK-NEXT: ret289 <vscale x 2 x i32> %0,290 <vscale x 2 x float> %1,291 <vscale x 2 x i1> %2,292 iXLen %3) nounwind {293entry:294 %a = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2i32(295 <vscale x 2 x i32> %0,296 <vscale x 2 x float> %1,297 <vscale x 2 x i1> %2,298 iXLen %3, iXLen 0)299 300 ret <vscale x 2 x i32> %a301}302 303define <vscale x 4 x i32> @intrinsic_vfclass_v_nxv4i32_nxv4f32(304; CHECK-LABEL: intrinsic_vfclass_v_nxv4i32_nxv4f32:305; CHECK: # %bb.0: # %entry306; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma307; CHECK-NEXT: vfclass.v v8, v8308; CHECK-NEXT: ret309 <vscale x 4 x float> %0,310 iXLen %1) nounwind {311entry:312 %a = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4i32(313 <vscale x 4 x i32> poison,314 <vscale x 4 x float> %0,315 iXLen %1)316 317 ret <vscale x 4 x i32> %a318}319 320define <vscale x 4 x i32> @intrinsic_vfclass_mask_v_nxv4i32_nxv4f32(321; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i32_nxv4f32:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu324; CHECK-NEXT: vfclass.v v8, v10, v0.t325; CHECK-NEXT: ret326 <vscale x 4 x i32> %0,327 <vscale x 4 x float> %1,328 <vscale x 4 x i1> %2,329 iXLen %3) nounwind {330entry:331 %a = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4i32(332 <vscale x 4 x i32> %0,333 <vscale x 4 x float> %1,334 <vscale x 4 x i1> %2,335 iXLen %3, iXLen 0)336 337 ret <vscale x 4 x i32> %a338}339 340define <vscale x 8 x i32> @intrinsic_vfclass_v_nxv8i32_nxv8f32(341; CHECK-LABEL: intrinsic_vfclass_v_nxv8i32_nxv8f32:342; CHECK: # %bb.0: # %entry343; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma344; CHECK-NEXT: vfclass.v v8, v8345; CHECK-NEXT: ret346 <vscale x 8 x float> %0,347 iXLen %1) nounwind {348entry:349 %a = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8i32(350 <vscale x 8 x i32> poison,351 <vscale x 8 x float> %0,352 iXLen %1)353 354 ret <vscale x 8 x i32> %a355}356 357define <vscale x 8 x i32> @intrinsic_vfclass_mask_v_nxv8i32_nxv8f32(358; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i32_nxv8f32:359; CHECK: # %bb.0: # %entry360; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu361; CHECK-NEXT: vfclass.v v8, v12, v0.t362; CHECK-NEXT: ret363 <vscale x 8 x i32> %0,364 <vscale x 8 x float> %1,365 <vscale x 8 x i1> %2,366 iXLen %3) nounwind {367entry:368 %a = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8i32(369 <vscale x 8 x i32> %0,370 <vscale x 8 x float> %1,371 <vscale x 8 x i1> %2,372 iXLen %3, iXLen 0)373 374 ret <vscale x 8 x i32> %a375}376 377define <vscale x 16 x i32> @intrinsic_vfclass_v_nxv16i32_nxv16f32(378; CHECK-LABEL: intrinsic_vfclass_v_nxv16i32_nxv16f32:379; CHECK: # %bb.0: # %entry380; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma381; CHECK-NEXT: vfclass.v v8, v8382; CHECK-NEXT: ret383 <vscale x 16 x float> %0,384 iXLen %1) nounwind {385entry:386 %a = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16i32(387 <vscale x 16 x i32> poison,388 <vscale x 16 x float> %0,389 iXLen %1)390 391 ret <vscale x 16 x i32> %a392}393 394define <vscale x 16 x i32> @intrinsic_vfclass_mask_v_nxv16i32_nxv16f32(395; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i32_nxv16f32:396; CHECK: # %bb.0: # %entry397; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu398; CHECK-NEXT: vfclass.v v8, v16, v0.t399; CHECK-NEXT: ret400 <vscale x 16 x i32> %0,401 <vscale x 16 x float> %1,402 <vscale x 16 x i1> %2,403 iXLen %3) nounwind {404entry:405 %a = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16i32(406 <vscale x 16 x i32> %0,407 <vscale x 16 x float> %1,408 <vscale x 16 x i1> %2,409 iXLen %3, iXLen 0)410 411 ret <vscale x 16 x i32> %a412}413 414define <vscale x 1 x i64> @intrinsic_vfclass_v_nxv1i64_nxv1f64(415; CHECK-LABEL: intrinsic_vfclass_v_nxv1i64_nxv1f64:416; CHECK: # %bb.0: # %entry417; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma418; CHECK-NEXT: vfclass.v v8, v8419; CHECK-NEXT: ret420 <vscale x 1 x double> %0,421 iXLen %1) nounwind {422entry:423 %a = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1i64(424 <vscale x 1 x i64> poison,425 <vscale x 1 x double> %0,426 iXLen %1)427 428 ret <vscale x 1 x i64> %a429}430 431define <vscale x 1 x i64> @intrinsic_vfclass_mask_v_nxv1i64_nxv1f64(432; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i64_nxv1f64:433; CHECK: # %bb.0: # %entry434; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu435; CHECK-NEXT: vfclass.v v8, v9, v0.t436; CHECK-NEXT: ret437 <vscale x 1 x i64> %0,438 <vscale x 1 x double> %1,439 <vscale x 1 x i1> %2,440 iXLen %3) nounwind {441entry:442 %a = call <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1i64(443 <vscale x 1 x i64> %0,444 <vscale x 1 x double> %1,445 <vscale x 1 x i1> %2,446 iXLen %3, iXLen 0)447 448 ret <vscale x 1 x i64> %a449}450 451define <vscale x 2 x i64> @intrinsic_vfclass_v_nxv2i64_nxv2f64(452; CHECK-LABEL: intrinsic_vfclass_v_nxv2i64_nxv2f64:453; CHECK: # %bb.0: # %entry454; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma455; CHECK-NEXT: vfclass.v v8, v8456; CHECK-NEXT: ret457 <vscale x 2 x double> %0,458 iXLen %1) nounwind {459entry:460 %a = call <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2i64(461 <vscale x 2 x i64> poison,462 <vscale x 2 x double> %0,463 iXLen %1)464 465 ret <vscale x 2 x i64> %a466}467 468define <vscale x 2 x i64> @intrinsic_vfclass_mask_v_nxv2i64_nxv2f64(469; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i64_nxv2f64:470; CHECK: # %bb.0: # %entry471; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu472; CHECK-NEXT: vfclass.v v8, v10, v0.t473; CHECK-NEXT: ret474 <vscale x 2 x i64> %0,475 <vscale x 2 x double> %1,476 <vscale x 2 x i1> %2,477 iXLen %3) nounwind {478entry:479 %a = call <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2i64(480 <vscale x 2 x i64> %0,481 <vscale x 2 x double> %1,482 <vscale x 2 x i1> %2,483 iXLen %3, iXLen 0)484 485 ret <vscale x 2 x i64> %a486}487 488define <vscale x 4 x i64> @intrinsic_vfclass_v_nxv4i64_nxv4f64(489; CHECK-LABEL: intrinsic_vfclass_v_nxv4i64_nxv4f64:490; CHECK: # %bb.0: # %entry491; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma492; CHECK-NEXT: vfclass.v v8, v8493; CHECK-NEXT: ret494 <vscale x 4 x double> %0,495 iXLen %1) nounwind {496entry:497 %a = call <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4i64(498 <vscale x 4 x i64> poison,499 <vscale x 4 x double> %0,500 iXLen %1)501 502 ret <vscale x 4 x i64> %a503}504 505define <vscale x 4 x i64> @intrinsic_vfclass_mask_v_nxv4i64_nxv4f64(506; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i64_nxv4f64:507; CHECK: # %bb.0: # %entry508; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu509; CHECK-NEXT: vfclass.v v8, v12, v0.t510; CHECK-NEXT: ret511 <vscale x 4 x i64> %0,512 <vscale x 4 x double> %1,513 <vscale x 4 x i1> %2,514 iXLen %3) nounwind {515entry:516 %a = call <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4i64(517 <vscale x 4 x i64> %0,518 <vscale x 4 x double> %1,519 <vscale x 4 x i1> %2,520 iXLen %3, iXLen 0)521 522 ret <vscale x 4 x i64> %a523}524 525define <vscale x 8 x i64> @intrinsic_vfclass_v_nxv8i64_nxv8f64(526; CHECK-LABEL: intrinsic_vfclass_v_nxv8i64_nxv8f64:527; CHECK: # %bb.0: # %entry528; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma529; CHECK-NEXT: vfclass.v v8, v8530; CHECK-NEXT: ret531 <vscale x 8 x double> %0,532 iXLen %1) nounwind {533entry:534 %a = call <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8i64(535 <vscale x 8 x i64> poison,536 <vscale x 8 x double> %0,537 iXLen %1)538 539 ret <vscale x 8 x i64> %a540}541 542define <vscale x 8 x i64> @intrinsic_vfclass_mask_v_nxv8i64_nxv8f64(543; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i64_nxv8f64:544; CHECK: # %bb.0: # %entry545; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu546; CHECK-NEXT: vfclass.v v8, v16, v0.t547; CHECK-NEXT: ret548 <vscale x 8 x i64> %0,549 <vscale x 8 x double> %1,550 <vscale x 8 x i1> %2,551 iXLen %3) nounwind {552entry:553 %a = call <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8i64(554 <vscale x 8 x i64> %0,555 <vscale x 8 x double> %1,556 <vscale x 8 x i1> %2,557 iXLen %3, iXLen 0)558 559 ret <vscale x 8 x i64> %a560}561