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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define iXLen @intrinsic_vfirst_m_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfirst_m_nxv1i1:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vfirst.m a0, v012; CHECK-NEXT: ret13entry:14 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(15 <vscale x 1 x i1> %0,16 iXLen %1)17 18 ret iXLen %a19}20 21define iXLen @intrinsic_vfirst_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {22; CHECK-LABEL: intrinsic_vfirst_m_nxv1i1_zero:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: li a0, -125; CHECK-NEXT: ret26entry:27 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(28 <vscale x 1 x i1> %0,29 iXLen 0)30 31 ret iXLen %a32}33 34define iXLen @intrinsic_vfirst_mask_m_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {35; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1:36; CHECK: # %bb.0: # %entry37; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma38; CHECK-NEXT: vmv1r.v v9, v039; CHECK-NEXT: vmv1r.v v0, v840; CHECK-NEXT: vfirst.m a0, v9, v0.t41; CHECK-NEXT: ret42entry:43 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(44 <vscale x 1 x i1> %0,45 <vscale x 1 x i1> %1,46 iXLen %2)47 48 ret iXLen %a49}50 51define iXLen @intrinsic_vfirst_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {52; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1_zero:53; CHECK: # %bb.0: # %entry54; CHECK-NEXT: li a0, -155; CHECK-NEXT: ret56entry:57 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(58 <vscale x 1 x i1> %0,59 <vscale x 1 x i1> %1,60 iXLen 0)61 62 ret iXLen %a63}64 65define iXLen @intrinsic_vfirst_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {66; CHECK-LABEL: intrinsic_vfirst_m_nxv2i1:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma69; CHECK-NEXT: vfirst.m a0, v070; CHECK-NEXT: ret71entry:72 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv2i1(73 <vscale x 2 x i1> %0,74 iXLen %1)75 76 ret iXLen %a77}78 79define iXLen @intrinsic_vfirst_mask_m_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {80; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv2i1:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma83; CHECK-NEXT: vmv1r.v v9, v084; CHECK-NEXT: vmv1r.v v0, v885; CHECK-NEXT: vfirst.m a0, v9, v0.t86; CHECK-NEXT: ret87entry:88 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv2i1(89 <vscale x 2 x i1> %0,90 <vscale x 2 x i1> %1,91 iXLen %2)92 93 ret iXLen %a94}95 96define iXLen @intrinsic_vfirst_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {97; CHECK-LABEL: intrinsic_vfirst_m_nxv4i1:98; CHECK: # %bb.0: # %entry99; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma100; CHECK-NEXT: vfirst.m a0, v0101; CHECK-NEXT: ret102entry:103 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv4i1(104 <vscale x 4 x i1> %0,105 iXLen %1)106 107 ret iXLen %a108}109 110define iXLen @intrinsic_vfirst_mask_m_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {111; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv4i1:112; CHECK: # %bb.0: # %entry113; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma114; CHECK-NEXT: vmv1r.v v9, v0115; CHECK-NEXT: vmv1r.v v0, v8116; CHECK-NEXT: vfirst.m a0, v9, v0.t117; CHECK-NEXT: ret118entry:119 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv4i1(120 <vscale x 4 x i1> %0,121 <vscale x 4 x i1> %1,122 iXLen %2)123 124 ret iXLen %a125}126 127define iXLen @intrinsic_vfirst_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {128; CHECK-LABEL: intrinsic_vfirst_m_nxv8i1:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma131; CHECK-NEXT: vfirst.m a0, v0132; CHECK-NEXT: ret133entry:134 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv8i1(135 <vscale x 8 x i1> %0,136 iXLen %1)137 138 ret iXLen %a139}140 141define iXLen @intrinsic_vfirst_mask_m_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {142; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv8i1:143; CHECK: # %bb.0: # %entry144; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma145; CHECK-NEXT: vmv1r.v v9, v0146; CHECK-NEXT: vmv1r.v v0, v8147; CHECK-NEXT: vfirst.m a0, v9, v0.t148; CHECK-NEXT: ret149entry:150 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv8i1(151 <vscale x 8 x i1> %0,152 <vscale x 8 x i1> %1,153 iXLen %2)154 155 ret iXLen %a156}157 158define iXLen @intrinsic_vfirst_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {159; CHECK-LABEL: intrinsic_vfirst_m_nxv16i1:160; CHECK: # %bb.0: # %entry161; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma162; CHECK-NEXT: vfirst.m a0, v0163; CHECK-NEXT: ret164entry:165 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv16i1(166 <vscale x 16 x i1> %0,167 iXLen %1)168 169 ret iXLen %a170}171 172define iXLen @intrinsic_vfirst_mask_m_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv16i1:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma176; CHECK-NEXT: vmv1r.v v9, v0177; CHECK-NEXT: vmv1r.v v0, v8178; CHECK-NEXT: vfirst.m a0, v9, v0.t179; CHECK-NEXT: ret180entry:181 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv16i1(182 <vscale x 16 x i1> %0,183 <vscale x 16 x i1> %1,184 iXLen %2)185 186 ret iXLen %a187}188 189define iXLen @intrinsic_vfirst_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {190; CHECK-LABEL: intrinsic_vfirst_m_nxv32i1:191; CHECK: # %bb.0: # %entry192; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma193; CHECK-NEXT: vfirst.m a0, v0194; CHECK-NEXT: ret195entry:196 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv32i1(197 <vscale x 32 x i1> %0,198 iXLen %1)199 200 ret iXLen %a201}202 203define iXLen @intrinsic_vfirst_mask_m_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {204; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv32i1:205; CHECK: # %bb.0: # %entry206; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma207; CHECK-NEXT: vmv1r.v v9, v0208; CHECK-NEXT: vmv1r.v v0, v8209; CHECK-NEXT: vfirst.m a0, v9, v0.t210; CHECK-NEXT: ret211entry:212 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv32i1(213 <vscale x 32 x i1> %0,214 <vscale x 32 x i1> %1,215 iXLen %2)216 217 ret iXLen %a218}219 220define iXLen @intrinsic_vfirst_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {221; CHECK-LABEL: intrinsic_vfirst_m_nxv64i1:222; CHECK: # %bb.0: # %entry223; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma224; CHECK-NEXT: vfirst.m a0, v0225; CHECK-NEXT: ret226entry:227 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv64i1(228 <vscale x 64 x i1> %0,229 iXLen %1)230 231 ret iXLen %a232}233 234define iXLen @intrinsic_vfirst_mask_m_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {235; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv64i1:236; CHECK: # %bb.0: # %entry237; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma238; CHECK-NEXT: vmv1r.v v9, v0239; CHECK-NEXT: vmv1r.v v0, v8240; CHECK-NEXT: vfirst.m a0, v9, v0.t241; CHECK-NEXT: ret242entry:243 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv64i1(244 <vscale x 64 x i1> %0,245 <vscale x 64 x i1> %1,246 iXLen %2)247 248 ret iXLen %a249}250