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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32 %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64 %s6 7; (-N0 * -N1) + N2 --> (N0 * N1) + N28define <vscale x 1 x double> @test1(<vscale x 1 x double> %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {9; CHECK-LABEL: test1:10; CHECK: # %bb.0:11; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma12; CHECK-NEXT: vfmadd.vv v9, v8, v10, v0.t13; CHECK-NEXT: vmv.v.v v8, v914; CHECK-NEXT: ret15 %nega = call <vscale x 1 x double> @llvm.vp.fneg.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x i1> %m, i32 %evl)16 %negb = call <vscale x 1 x double> @llvm.vp.fneg.nxv1f64(<vscale x 1 x double> %b, <vscale x 1 x i1> %m, i32 %evl)17 %v = call <vscale x 1 x double> @llvm.vp.fma.nxv1f64(<vscale x 1 x double> %nega, <vscale x 1 x double> %negb, <vscale x 1 x double> %c, <vscale x 1 x i1> %m, i32 %evl)18 ret <vscale x 1 x double> %v19}20 21; (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)22define <vscale x 1 x double> @test2(<vscale x 1 x double> %a, <vscale x 1 x i1> %m, i32 zeroext %evl) {23; RV32-LABEL: test2:24; RV32: # %bb.0:25; RV32-NEXT: lui a1, %hi(.LCPI1_0)26; RV32-NEXT: fld fa5, %lo(.LCPI1_0)(a1)27; RV32-NEXT: lui a1, %hi(.LCPI1_1)28; RV32-NEXT: fld fa4, %lo(.LCPI1_1)(a1)29; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma30; RV32-NEXT: vfmv.v.f v9, fa531; RV32-NEXT: vfadd.vf v9, v9, fa4, v0.t32; RV32-NEXT: vfmul.vv v8, v8, v9, v0.t33; RV32-NEXT: ret34;35; RV64-LABEL: test2:36; RV64: # %bb.0:37; RV64-NEXT: li a1, 102538; RV64-NEXT: slli a1, a1, 5239; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma40; RV64-NEXT: vmv.v.x v9, a141; RV64-NEXT: li a0, 142; RV64-NEXT: slli a0, a0, 6243; RV64-NEXT: fmv.d.x fa5, a044; RV64-NEXT: vfadd.vf v9, v9, fa5, v0.t45; RV64-NEXT: vfmul.vv v8, v8, v9, v0.t46; RV64-NEXT: ret47 %t = call <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> splat (double 2.0), <vscale x 1 x i1> %m, i32 %evl)48 %v = call fast <vscale x 1 x double> @llvm.vp.fma.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> splat (double 4.0), <vscale x 1 x double> %t, <vscale x 1 x i1> %m, i32 %evl)49 ret <vscale x 1 x double> %v50}51 52; (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)53define <vscale x 1 x double> @test3(<vscale x 1 x double> %a, <vscale x 1 x double> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {54; RV32-LABEL: test3:55; RV32: # %bb.0:56; RV32-NEXT: lui a1, %hi(.LCPI2_0)57; RV32-NEXT: fld fa5, %lo(.LCPI2_0)(a1)58; RV32-NEXT: lui a1, %hi(.LCPI2_1)59; RV32-NEXT: fld fa4, %lo(.LCPI2_1)(a1)60; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma61; RV32-NEXT: vfmv.v.f v10, fa562; RV32-NEXT: vfmul.vf v10, v10, fa4, v0.t63; RV32-NEXT: vfmadd.vv v10, v8, v9, v0.t64; RV32-NEXT: vmv.v.v v8, v1065; RV32-NEXT: ret66;67; RV64-LABEL: test3:68; RV64: # %bb.0:69; RV64-NEXT: li a1, 102570; RV64-NEXT: slli a1, a1, 5271; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma72; RV64-NEXT: vmv.v.x v10, a173; RV64-NEXT: li a0, 174; RV64-NEXT: slli a0, a0, 6275; RV64-NEXT: fmv.d.x fa5, a076; RV64-NEXT: vfmul.vf v10, v10, fa5, v0.t77; RV64-NEXT: vfmadd.vv v10, v8, v9, v0.t78; RV64-NEXT: vmv.v.v v8, v1079; RV64-NEXT: ret80 %t = call <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> splat (double 2.0), <vscale x 1 x i1> %m, i32 %evl)81 %v = call fast <vscale x 1 x double> @llvm.vp.fma.nxv1f64(<vscale x 1 x double> %t, <vscale x 1 x double> splat (double 4.0), <vscale x 1 x double> %b, <vscale x 1 x i1> %m, i32 %evl)82 ret <vscale x 1 x double> %v83}84