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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN10 11; This tests a mix of vfmacc and vfmadd by using different operand orders to12; trigger commuting in TwoAddressInstructionPass.13 14define <vscale x 1 x bfloat> @vfmadd_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x bfloat> %vc) {15; CHECK-LABEL: vfmadd_vv_nxv1bf16:16; CHECK: # %bb.0:17; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma18; CHECK-NEXT: vfwcvtbf16.f.f.v v11, v1019; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v820; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v921; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma22; CHECK-NEXT: vfmadd.vv v12, v10, v1123; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma24; CHECK-NEXT: vfncvtbf16.f.f.w v8, v1225; CHECK-NEXT: ret26 %vd = call <vscale x 1 x bfloat> @llvm.fma.v1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x bfloat> %vc)27 ret <vscale x 1 x bfloat> %vd28}29 30define <vscale x 1 x bfloat> @vfmadd_vv_nxv1bf16_commuted(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x bfloat> %vc) {31; CHECK-LABEL: vfmadd_vv_nxv1bf16_commuted:32; CHECK: # %bb.0:33; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma34; CHECK-NEXT: vfwcvtbf16.f.f.v v11, v835; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v936; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v1037; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma38; CHECK-NEXT: vfmadd.vv v9, v8, v1139; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma40; CHECK-NEXT: vfncvtbf16.f.f.w v8, v941; CHECK-NEXT: ret42 %vd = call <vscale x 1 x bfloat> @llvm.fma.v1bf16(<vscale x 1 x bfloat> %vb, <vscale x 1 x bfloat> %vc, <vscale x 1 x bfloat> %va)43 ret <vscale x 1 x bfloat> %vd44}45 46define <vscale x 1 x bfloat> @vfmadd_vf_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, bfloat %c) {47; CHECK-LABEL: vfmadd_vf_nxv1bf16:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma50; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v951; CHECK-NEXT: fcvt.s.bf16 fa5, fa052; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v853; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma54; CHECK-NEXT: vfmadd.vf v9, fa5, v1055; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma56; CHECK-NEXT: vfncvtbf16.f.f.w v8, v957; CHECK-NEXT: ret58 %head = insertelement <vscale x 1 x bfloat> poison, bfloat %c, i32 059 %splat = shufflevector <vscale x 1 x bfloat> %head, <vscale x 1 x bfloat> poison, <vscale x 1 x i32> zeroinitializer60 %vd = call <vscale x 1 x bfloat> @llvm.fma.v1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %splat, <vscale x 1 x bfloat> %vb)61 ret <vscale x 1 x bfloat> %vd62}63 64define <vscale x 2 x bfloat> @vfmadd_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x bfloat> %vc) {65; CHECK-LABEL: vfmadd_vv_nxv2bf16:66; CHECK: # %bb.0:67; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma68; CHECK-NEXT: vfwcvtbf16.f.f.v v11, v969; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v870; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v1071; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma72; CHECK-NEXT: vfmadd.vv v12, v9, v1173; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma74; CHECK-NEXT: vfncvtbf16.f.f.w v8, v1275; CHECK-NEXT: ret76 %vd = call <vscale x 2 x bfloat> @llvm.fma.v2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vc, <vscale x 2 x bfloat> %vb)77 ret <vscale x 2 x bfloat> %vd78}79 80define <vscale x 2 x bfloat> @vfmadd_vf_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, bfloat %c) {81; CHECK-LABEL: vfmadd_vf_nxv2bf16:82; CHECK: # %bb.0:83; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma84; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v885; CHECK-NEXT: fcvt.s.bf16 fa5, fa086; CHECK-NEXT: vfwcvtbf16.f.f.v v11, v987; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma88; CHECK-NEXT: vfmadd.vf v11, fa5, v1089; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma90; CHECK-NEXT: vfncvtbf16.f.f.w v8, v1191; CHECK-NEXT: ret92 %head = insertelement <vscale x 2 x bfloat> poison, bfloat %c, i32 093 %splat = shufflevector <vscale x 2 x bfloat> %head, <vscale x 2 x bfloat> poison, <vscale x 2 x i32> zeroinitializer94 %vd = call <vscale x 2 x bfloat> @llvm.fma.v2bf16(<vscale x 2 x bfloat> %vb, <vscale x 2 x bfloat> %splat, <vscale x 2 x bfloat> %va)95 ret <vscale x 2 x bfloat> %vd96}97 98define <vscale x 4 x bfloat> @vfmadd_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x bfloat> %vc) {99; CHECK-LABEL: vfmadd_vv_nxv4bf16:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma102; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v10103; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9104; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v8105; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma106; CHECK-NEXT: vfmadd.vv v14, v10, v12107; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma108; CHECK-NEXT: vfncvtbf16.f.f.w v8, v14109; CHECK-NEXT: ret110 %vd = call <vscale x 4 x bfloat> @llvm.fma.v4bf16(<vscale x 4 x bfloat> %vb, <vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vc)111 ret <vscale x 4 x bfloat> %vd112}113 114define <vscale x 4 x bfloat> @vfmadd_vf_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, bfloat %c) {115; CHECK-LABEL: vfmadd_vf_nxv4bf16:116; CHECK: # %bb.0:117; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma118; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9119; CHECK-NEXT: fcvt.s.bf16 fa5, fa0120; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8121; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma122; CHECK-NEXT: vfmadd.vf v12, fa5, v10123; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma124; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12125; CHECK-NEXT: ret126 %head = insertelement <vscale x 4 x bfloat> poison, bfloat %c, i32 0127 %splat = shufflevector <vscale x 4 x bfloat> %head, <vscale x 4 x bfloat> poison, <vscale x 4 x i32> zeroinitializer128 %vd = call <vscale x 4 x bfloat> @llvm.fma.v4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %splat, <vscale x 4 x bfloat> %vb)129 ret <vscale x 4 x bfloat> %vd130}131 132define <vscale x 8 x bfloat> @vfmadd_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x bfloat> %vc) {133; CHECK-LABEL: vfmadd_vv_nxv8bf16:134; CHECK: # %bb.0:135; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma136; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8137; CHECK-NEXT: vfwcvtbf16.f.f.v v20, v10138; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12139; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma140; CHECK-NEXT: vfmadd.vv v24, v20, v16141; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma142; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24143; CHECK-NEXT: ret144 %vd = call <vscale x 8 x bfloat> @llvm.fma.v8bf16(<vscale x 8 x bfloat> %vb, <vscale x 8 x bfloat> %vc, <vscale x 8 x bfloat> %va)145 ret <vscale x 8 x bfloat> %vd146}147 148define <vscale x 8 x bfloat> @vfmadd_vf_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, bfloat %c) {149; CHECK-LABEL: vfmadd_vf_nxv8bf16:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma152; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8153; CHECK-NEXT: fcvt.s.bf16 fa5, fa0154; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v10155; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma156; CHECK-NEXT: vfmadd.vf v16, fa5, v12157; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma158; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16159; CHECK-NEXT: ret160 %head = insertelement <vscale x 8 x bfloat> poison, bfloat %c, i32 0161 %splat = shufflevector <vscale x 8 x bfloat> %head, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer162 %vd = call <vscale x 8 x bfloat> @llvm.fma.v8bf16(<vscale x 8 x bfloat> %vb, <vscale x 8 x bfloat> %splat, <vscale x 8 x bfloat> %va)163 ret <vscale x 8 x bfloat> %vd164}165 166define <vscale x 16 x bfloat> @vfmadd_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x bfloat> %vc) {167; CHECK-LABEL: vfmadd_vv_nxv16bf16:168; CHECK: # %bb.0:169; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma170; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12171; CHECK-NEXT: vfwcvtbf16.f.f.v v0, v16172; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8173; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma174; CHECK-NEXT: vfmadd.vv v16, v0, v24175; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma176; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16177; CHECK-NEXT: ret178 %vd = call <vscale x 16 x bfloat> @llvm.fma.v16bf16(<vscale x 16 x bfloat> %vc, <vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb)179 ret <vscale x 16 x bfloat> %vd180}181 182define <vscale x 16 x bfloat> @vfmadd_vf_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, bfloat %c) {183; CHECK-LABEL: vfmadd_vf_nxv16bf16:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma186; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12187; CHECK-NEXT: fcvt.s.bf16 fa5, fa0188; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8189; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma190; CHECK-NEXT: vfmadd.vf v24, fa5, v16191; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma192; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24193; CHECK-NEXT: ret194 %head = insertelement <vscale x 16 x bfloat> poison, bfloat %c, i32 0195 %splat = shufflevector <vscale x 16 x bfloat> %head, <vscale x 16 x bfloat> poison, <vscale x 16 x i32> zeroinitializer196 %vd = call <vscale x 16 x bfloat> @llvm.fma.v16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %splat, <vscale x 16 x bfloat> %vb)197 ret <vscale x 16 x bfloat> %vd198}199 200define <vscale x 32 x bfloat> @vfmadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x bfloat> %vc) {201; ZVFH-LABEL: vfmadd_vv_nxv32bf16:202; ZVFH: # %bb.0:203; ZVFH-NEXT: addi sp, sp, -16204; ZVFH-NEXT: .cfi_def_cfa_offset 16205; ZVFH-NEXT: csrr a1, vlenb206; ZVFH-NEXT: slli a1, a1, 5207; ZVFH-NEXT: sub sp, sp, a1208; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb209; ZVFH-NEXT: vsetvli a1, zero, e16, m4, ta, ma210; ZVFH-NEXT: vmv8r.v v0, v16211; ZVFH-NEXT: csrr a1, vlenb212; ZVFH-NEXT: slli a1, a1, 3213; ZVFH-NEXT: add a1, sp, a1214; ZVFH-NEXT: addi a1, a1, 16215; ZVFH-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill216; ZVFH-NEXT: vl8re16.v v16, (a0)217; ZVFH-NEXT: csrr a0, vlenb218; ZVFH-NEXT: slli a0, a0, 3219; ZVFH-NEXT: mv a1, a0220; ZVFH-NEXT: slli a0, a0, 1221; ZVFH-NEXT: add a0, a0, a1222; ZVFH-NEXT: add a0, sp, a0223; ZVFH-NEXT: addi a0, a0, 16224; ZVFH-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill225; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v8226; ZVFH-NEXT: csrr a0, vlenb227; ZVFH-NEXT: slli a0, a0, 4228; ZVFH-NEXT: add a0, sp, a0229; ZVFH-NEXT: addi a0, a0, 16230; ZVFH-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill231; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v0232; ZVFH-NEXT: addi a0, sp, 16233; ZVFH-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill234; ZVFH-NEXT: csrr a0, vlenb235; ZVFH-NEXT: slli a0, a0, 3236; ZVFH-NEXT: mv a1, a0237; ZVFH-NEXT: slli a0, a0, 1238; ZVFH-NEXT: add a0, a0, a1239; ZVFH-NEXT: add a0, sp, a0240; ZVFH-NEXT: addi a0, a0, 16241; ZVFH-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload242; ZVFH-NEXT: vfwcvtbf16.f.f.v v0, v16243; ZVFH-NEXT: csrr a0, vlenb244; ZVFH-NEXT: slli a0, a0, 4245; ZVFH-NEXT: add a0, sp, a0246; ZVFH-NEXT: addi a0, a0, 16247; ZVFH-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload248; ZVFH-NEXT: addi a0, sp, 16249; ZVFH-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload250; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma251; ZVFH-NEXT: vfmadd.vv v0, v16, v24252; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma253; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v12254; ZVFH-NEXT: csrr a0, vlenb255; ZVFH-NEXT: slli a0, a0, 4256; ZVFH-NEXT: add a0, sp, a0257; ZVFH-NEXT: addi a0, a0, 16258; ZVFH-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill259; ZVFH-NEXT: csrr a0, vlenb260; ZVFH-NEXT: slli a0, a0, 3261; ZVFH-NEXT: add a0, sp, a0262; ZVFH-NEXT: addi a0, a0, 16263; ZVFH-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload264; ZVFH-NEXT: vfwcvtbf16.f.f.v v8, v28265; ZVFH-NEXT: csrr a0, vlenb266; ZVFH-NEXT: slli a0, a0, 3267; ZVFH-NEXT: mv a1, a0268; ZVFH-NEXT: slli a0, a0, 1269; ZVFH-NEXT: add a0, a0, a1270; ZVFH-NEXT: add a0, sp, a0271; ZVFH-NEXT: addi a0, a0, 16272; ZVFH-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload273; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v28274; ZVFH-NEXT: csrr a0, vlenb275; ZVFH-NEXT: slli a0, a0, 4276; ZVFH-NEXT: add a0, sp, a0277; ZVFH-NEXT: addi a0, a0, 16278; ZVFH-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload279; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma280; ZVFH-NEXT: vfmadd.vv v16, v8, v24281; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma282; ZVFH-NEXT: vfncvtbf16.f.f.w v8, v0283; ZVFH-NEXT: vfncvtbf16.f.f.w v12, v16284; ZVFH-NEXT: csrr a0, vlenb285; ZVFH-NEXT: slli a0, a0, 5286; ZVFH-NEXT: add sp, sp, a0287; ZVFH-NEXT: .cfi_def_cfa sp, 16288; ZVFH-NEXT: addi sp, sp, 16289; ZVFH-NEXT: .cfi_def_cfa_offset 0290; ZVFH-NEXT: ret291;292; ZVFHMIN-LABEL: vfmadd_vv_nxv32bf16:293; ZVFHMIN: # %bb.0:294; ZVFHMIN-NEXT: addi sp, sp, -16295; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16296; ZVFHMIN-NEXT: csrr a1, vlenb297; ZVFHMIN-NEXT: slli a1, a1, 5298; ZVFHMIN-NEXT: sub sp, sp, a1299; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb300; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma301; ZVFHMIN-NEXT: vmv8r.v v0, v16302; ZVFHMIN-NEXT: csrr a1, vlenb303; ZVFHMIN-NEXT: slli a1, a1, 3304; ZVFHMIN-NEXT: add a1, sp, a1305; ZVFHMIN-NEXT: addi a1, a1, 16306; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill307; ZVFHMIN-NEXT: vl8re16.v v16, (a0)308; ZVFHMIN-NEXT: csrr a0, vlenb309; ZVFHMIN-NEXT: li a1, 24310; ZVFHMIN-NEXT: mul a0, a0, a1311; ZVFHMIN-NEXT: add a0, sp, a0312; ZVFHMIN-NEXT: addi a0, a0, 16313; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill314; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v8315; ZVFHMIN-NEXT: csrr a0, vlenb316; ZVFHMIN-NEXT: slli a0, a0, 4317; ZVFHMIN-NEXT: add a0, sp, a0318; ZVFHMIN-NEXT: addi a0, a0, 16319; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill320; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v0321; ZVFHMIN-NEXT: addi a0, sp, 16322; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill323; ZVFHMIN-NEXT: csrr a0, vlenb324; ZVFHMIN-NEXT: li a1, 24325; ZVFHMIN-NEXT: mul a0, a0, a1326; ZVFHMIN-NEXT: add a0, sp, a0327; ZVFHMIN-NEXT: addi a0, a0, 16328; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload329; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v0, v16330; ZVFHMIN-NEXT: csrr a0, vlenb331; ZVFHMIN-NEXT: slli a0, a0, 4332; ZVFHMIN-NEXT: add a0, sp, a0333; ZVFHMIN-NEXT: addi a0, a0, 16334; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload335; ZVFHMIN-NEXT: addi a0, sp, 16336; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload337; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma338; ZVFHMIN-NEXT: vfmadd.vv v0, v16, v24339; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma340; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v12341; ZVFHMIN-NEXT: csrr a0, vlenb342; ZVFHMIN-NEXT: slli a0, a0, 4343; ZVFHMIN-NEXT: add a0, sp, a0344; ZVFHMIN-NEXT: addi a0, a0, 16345; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill346; ZVFHMIN-NEXT: csrr a0, vlenb347; ZVFHMIN-NEXT: slli a0, a0, 3348; ZVFHMIN-NEXT: add a0, sp, a0349; ZVFHMIN-NEXT: addi a0, a0, 16350; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload351; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v8, v28352; ZVFHMIN-NEXT: csrr a0, vlenb353; ZVFHMIN-NEXT: li a1, 24354; ZVFHMIN-NEXT: mul a0, a0, a1355; ZVFHMIN-NEXT: add a0, sp, a0356; ZVFHMIN-NEXT: addi a0, a0, 16357; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload358; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v28359; ZVFHMIN-NEXT: csrr a0, vlenb360; ZVFHMIN-NEXT: slli a0, a0, 4361; ZVFHMIN-NEXT: add a0, sp, a0362; ZVFHMIN-NEXT: addi a0, a0, 16363; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload364; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma365; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24366; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma367; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v0368; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v12, v16369; ZVFHMIN-NEXT: csrr a0, vlenb370; ZVFHMIN-NEXT: slli a0, a0, 5371; ZVFHMIN-NEXT: add sp, sp, a0372; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16373; ZVFHMIN-NEXT: addi sp, sp, 16374; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0375; ZVFHMIN-NEXT: ret376 %vd = call <vscale x 32 x bfloat> @llvm.fma.v32bf16(<vscale x 32 x bfloat> %vc, <vscale x 32 x bfloat> %vb, <vscale x 32 x bfloat> %va)377 ret <vscale x 32 x bfloat> %vd378}379 380define <vscale x 32 x bfloat> @vfmadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, bfloat %c) {381; ZVFH-LABEL: vfmadd_vf_nxv32bf16:382; ZVFH: # %bb.0:383; ZVFH-NEXT: addi sp, sp, -16384; ZVFH-NEXT: .cfi_def_cfa_offset 16385; ZVFH-NEXT: csrr a0, vlenb386; ZVFH-NEXT: slli a0, a0, 5387; ZVFH-NEXT: sub sp, sp, a0388; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb389; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma390; ZVFH-NEXT: vmv8r.v v24, v16391; ZVFH-NEXT: csrr a0, vlenb392; ZVFH-NEXT: slli a0, a0, 4393; ZVFH-NEXT: add a0, sp, a0394; ZVFH-NEXT: addi a0, a0, 16395; ZVFH-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill396; ZVFH-NEXT: vmv8r.v v16, v8397; ZVFH-NEXT: addi a0, sp, 16398; ZVFH-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill399; ZVFH-NEXT: fmv.x.h a0, fa0400; ZVFH-NEXT: vfwcvtbf16.f.f.v v8, v16401; ZVFH-NEXT: csrr a1, vlenb402; ZVFH-NEXT: slli a1, a1, 3403; ZVFH-NEXT: mv a2, a1404; ZVFH-NEXT: slli a1, a1, 1405; ZVFH-NEXT: add a1, a1, a2406; ZVFH-NEXT: add a1, sp, a1407; ZVFH-NEXT: addi a1, a1, 16408; ZVFH-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill409; ZVFH-NEXT: vfwcvtbf16.f.f.v v8, v24410; ZVFH-NEXT: csrr a1, vlenb411; ZVFH-NEXT: slli a1, a1, 3412; ZVFH-NEXT: add a1, sp, a1413; ZVFH-NEXT: addi a1, a1, 16414; ZVFH-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill415; ZVFH-NEXT: vsetvli a1, zero, e16, m8, ta, ma416; ZVFH-NEXT: vmv.v.x v8, a0417; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma418; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v8419; ZVFH-NEXT: csrr a0, vlenb420; ZVFH-NEXT: slli a0, a0, 3421; ZVFH-NEXT: mv a1, a0422; ZVFH-NEXT: slli a0, a0, 1423; ZVFH-NEXT: add a0, a0, a1424; ZVFH-NEXT: add a0, sp, a0425; ZVFH-NEXT: addi a0, a0, 16426; ZVFH-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload427; ZVFH-NEXT: csrr a0, vlenb428; ZVFH-NEXT: slli a0, a0, 3429; ZVFH-NEXT: add a0, sp, a0430; ZVFH-NEXT: addi a0, a0, 16431; ZVFH-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload432; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma433; ZVFH-NEXT: vfmadd.vv v24, v16, v0434; ZVFH-NEXT: addi a0, sp, 16435; ZVFH-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload436; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma437; ZVFH-NEXT: vfwcvtbf16.f.f.v v0, v20438; ZVFH-NEXT: csrr a0, vlenb439; ZVFH-NEXT: slli a0, a0, 3440; ZVFH-NEXT: mv a1, a0441; ZVFH-NEXT: slli a0, a0, 1442; ZVFH-NEXT: add a0, a0, a1443; ZVFH-NEXT: add a0, sp, a0444; ZVFH-NEXT: addi a0, a0, 16445; ZVFH-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill446; ZVFH-NEXT: csrr a0, vlenb447; ZVFH-NEXT: slli a0, a0, 4448; ZVFH-NEXT: add a0, sp, a0449; ZVFH-NEXT: addi a0, a0, 16450; ZVFH-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload451; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v4452; ZVFH-NEXT: vfwcvtbf16.f.f.v v0, v12453; ZVFH-NEXT: csrr a0, vlenb454; ZVFH-NEXT: slli a0, a0, 3455; ZVFH-NEXT: mv a1, a0456; ZVFH-NEXT: slli a0, a0, 1457; ZVFH-NEXT: add a0, a0, a1458; ZVFH-NEXT: add a0, sp, a0459; ZVFH-NEXT: addi a0, a0, 16460; ZVFH-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload461; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma462; ZVFH-NEXT: vfmadd.vv v0, v16, v8463; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma464; ZVFH-NEXT: vfncvtbf16.f.f.w v8, v24465; ZVFH-NEXT: vfncvtbf16.f.f.w v12, v0466; ZVFH-NEXT: csrr a0, vlenb467; ZVFH-NEXT: slli a0, a0, 5468; ZVFH-NEXT: add sp, sp, a0469; ZVFH-NEXT: .cfi_def_cfa sp, 16470; ZVFH-NEXT: addi sp, sp, 16471; ZVFH-NEXT: .cfi_def_cfa_offset 0472; ZVFH-NEXT: ret473;474; ZVFHMIN-LABEL: vfmadd_vf_nxv32bf16:475; ZVFHMIN: # %bb.0:476; ZVFHMIN-NEXT: addi sp, sp, -16477; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16478; ZVFHMIN-NEXT: csrr a0, vlenb479; ZVFHMIN-NEXT: slli a0, a0, 5480; ZVFHMIN-NEXT: sub sp, sp, a0481; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb482; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma483; ZVFHMIN-NEXT: vmv8r.v v24, v16484; ZVFHMIN-NEXT: csrr a0, vlenb485; ZVFHMIN-NEXT: slli a0, a0, 4486; ZVFHMIN-NEXT: add a0, sp, a0487; ZVFHMIN-NEXT: addi a0, a0, 16488; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill489; ZVFHMIN-NEXT: vmv8r.v v16, v8490; ZVFHMIN-NEXT: addi a0, sp, 16491; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill492; ZVFHMIN-NEXT: fmv.x.h a0, fa0493; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v8, v16494; ZVFHMIN-NEXT: csrr a1, vlenb495; ZVFHMIN-NEXT: li a2, 24496; ZVFHMIN-NEXT: mul a1, a1, a2497; ZVFHMIN-NEXT: add a1, sp, a1498; ZVFHMIN-NEXT: addi a1, a1, 16499; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill500; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v8, v24501; ZVFHMIN-NEXT: csrr a1, vlenb502; ZVFHMIN-NEXT: slli a1, a1, 3503; ZVFHMIN-NEXT: add a1, sp, a1504; ZVFHMIN-NEXT: addi a1, a1, 16505; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill506; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma507; ZVFHMIN-NEXT: vmv.v.x v8, a0508; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma509; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v8510; ZVFHMIN-NEXT: csrr a0, vlenb511; ZVFHMIN-NEXT: li a1, 24512; ZVFHMIN-NEXT: mul a0, a0, a1513; ZVFHMIN-NEXT: add a0, sp, a0514; ZVFHMIN-NEXT: addi a0, a0, 16515; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload516; ZVFHMIN-NEXT: csrr a0, vlenb517; ZVFHMIN-NEXT: slli a0, a0, 3518; ZVFHMIN-NEXT: add a0, sp, a0519; ZVFHMIN-NEXT: addi a0, a0, 16520; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload521; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma522; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v0523; ZVFHMIN-NEXT: addi a0, sp, 16524; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload525; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma526; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v0, v20527; ZVFHMIN-NEXT: csrr a0, vlenb528; ZVFHMIN-NEXT: li a1, 24529; ZVFHMIN-NEXT: mul a0, a0, a1530; ZVFHMIN-NEXT: add a0, sp, a0531; ZVFHMIN-NEXT: addi a0, a0, 16532; ZVFHMIN-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill533; ZVFHMIN-NEXT: csrr a0, vlenb534; ZVFHMIN-NEXT: slli a0, a0, 4535; ZVFHMIN-NEXT: add a0, sp, a0536; ZVFHMIN-NEXT: addi a0, a0, 16537; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload538; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v4539; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v0, v12540; ZVFHMIN-NEXT: csrr a0, vlenb541; ZVFHMIN-NEXT: li a1, 24542; ZVFHMIN-NEXT: mul a0, a0, a1543; ZVFHMIN-NEXT: add a0, sp, a0544; ZVFHMIN-NEXT: addi a0, a0, 16545; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload546; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma547; ZVFHMIN-NEXT: vfmadd.vv v0, v16, v8548; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma549; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v24550; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v12, v0551; ZVFHMIN-NEXT: csrr a0, vlenb552; ZVFHMIN-NEXT: slli a0, a0, 5553; ZVFHMIN-NEXT: add sp, sp, a0554; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16555; ZVFHMIN-NEXT: addi sp, sp, 16556; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0557; ZVFHMIN-NEXT: ret558 %head = insertelement <vscale x 32 x bfloat> poison, bfloat %c, i32 0559 %splat = shufflevector <vscale x 32 x bfloat> %head, <vscale x 32 x bfloat> poison, <vscale x 32 x i32> zeroinitializer560 %vd = call <vscale x 32 x bfloat> @llvm.fma.v32bf16(<vscale x 32 x bfloat> %vb, <vscale x 32 x bfloat> %splat, <vscale x 32 x bfloat> %va)561 ret <vscale x 32 x bfloat> %vd562}563 564define <vscale x 1 x half> @vfmadd_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x half> %vc) {565; ZVFH-LABEL: vfmadd_vv_nxv1f16:566; ZVFH: # %bb.0:567; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma568; ZVFH-NEXT: vfmadd.vv v8, v9, v10569; ZVFH-NEXT: ret570;571; ZVFHMIN-LABEL: vfmadd_vv_nxv1f16:572; ZVFHMIN: # %bb.0:573; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma574; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v10575; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8576; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9577; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma578; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v11579; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma580; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12581; ZVFHMIN-NEXT: ret582 %vd = call <vscale x 1 x half> @llvm.fma.v1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x half> %vc)583 ret <vscale x 1 x half> %vd584}585 586define <vscale x 1 x half> @vfmadd_vv_nxv1f16_commuted(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x half> %vc) {587; ZVFH-LABEL: vfmadd_vv_nxv1f16_commuted:588; ZVFH: # %bb.0:589; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma590; ZVFH-NEXT: vfmacc.vv v8, v10, v9591; ZVFH-NEXT: ret592;593; ZVFHMIN-LABEL: vfmadd_vv_nxv1f16_commuted:594; ZVFHMIN: # %bb.0:595; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma596; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8597; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9598; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10599; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma600; ZVFHMIN-NEXT: vfmadd.vv v9, v8, v11601; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma602; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9603; ZVFHMIN-NEXT: ret604 %vd = call <vscale x 1 x half> @llvm.fma.v1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %vc, <vscale x 1 x half> %va)605 ret <vscale x 1 x half> %vd606}607 608define <vscale x 1 x half> @vfmadd_vf_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, half %c) {609; ZVFH-LABEL: vfmadd_vf_nxv1f16:610; ZVFH: # %bb.0:611; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma612; ZVFH-NEXT: vfmadd.vf v8, fa0, v9613; ZVFH-NEXT: ret614;615; ZVFHMIN-LABEL: vfmadd_vf_nxv1f16:616; ZVFHMIN: # %bb.0:617; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma618; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9619; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0620; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8621; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma622; ZVFHMIN-NEXT: vfmadd.vf v9, fa5, v10623; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma624; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9625; ZVFHMIN-NEXT: ret626 %head = insertelement <vscale x 1 x half> poison, half %c, i32 0627 %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer628 %vd = call <vscale x 1 x half> @llvm.fma.v1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %splat, <vscale x 1 x half> %vb)629 ret <vscale x 1 x half> %vd630}631 632define <vscale x 2 x half> @vfmadd_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x half> %vc) {633; ZVFH-LABEL: vfmadd_vv_nxv2f16:634; ZVFH: # %bb.0:635; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma636; ZVFH-NEXT: vfmadd.vv v8, v10, v9637; ZVFH-NEXT: ret638;639; ZVFHMIN-LABEL: vfmadd_vv_nxv2f16:640; ZVFHMIN: # %bb.0:641; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma642; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9643; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8644; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10645; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma646; ZVFHMIN-NEXT: vfmadd.vv v12, v9, v11647; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma648; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12649; ZVFHMIN-NEXT: ret650 %vd = call <vscale x 2 x half> @llvm.fma.v2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vc, <vscale x 2 x half> %vb)651 ret <vscale x 2 x half> %vd652}653 654define <vscale x 2 x half> @vfmadd_vf_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, half %c) {655; ZVFH-LABEL: vfmadd_vf_nxv2f16:656; ZVFH: # %bb.0:657; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma658; ZVFH-NEXT: vfmacc.vf v8, fa0, v9659; ZVFH-NEXT: ret660;661; ZVFHMIN-LABEL: vfmadd_vf_nxv2f16:662; ZVFHMIN: # %bb.0:663; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma664; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8665; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0666; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9667; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma668; ZVFHMIN-NEXT: vfmadd.vf v11, fa5, v10669; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma670; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v11671; ZVFHMIN-NEXT: ret672 %head = insertelement <vscale x 2 x half> poison, half %c, i32 0673 %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer674 %vd = call <vscale x 2 x half> @llvm.fma.v2f16(<vscale x 2 x half> %vb, <vscale x 2 x half> %splat, <vscale x 2 x half> %va)675 ret <vscale x 2 x half> %vd676}677 678define <vscale x 4 x half> @vfmadd_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x half> %vc) {679; ZVFH-LABEL: vfmadd_vv_nxv4f16:680; ZVFH: # %bb.0:681; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma682; ZVFH-NEXT: vfmadd.vv v8, v9, v10683; ZVFH-NEXT: ret684;685; ZVFHMIN-LABEL: vfmadd_vv_nxv4f16:686; ZVFHMIN: # %bb.0:687; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma688; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10689; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9690; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8691; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma692; ZVFHMIN-NEXT: vfmadd.vv v14, v10, v12693; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma694; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v14695; ZVFHMIN-NEXT: ret696 %vd = call <vscale x 4 x half> @llvm.fma.v4f16(<vscale x 4 x half> %vb, <vscale x 4 x half> %va, <vscale x 4 x half> %vc)697 ret <vscale x 4 x half> %vd698}699 700define <vscale x 4 x half> @vfmadd_vf_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, half %c) {701; ZVFH-LABEL: vfmadd_vf_nxv4f16:702; ZVFH: # %bb.0:703; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma704; ZVFH-NEXT: vfmadd.vf v8, fa0, v9705; ZVFH-NEXT: ret706;707; ZVFHMIN-LABEL: vfmadd_vf_nxv4f16:708; ZVFHMIN: # %bb.0:709; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma710; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9711; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0712; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8713; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma714; ZVFHMIN-NEXT: vfmadd.vf v12, fa5, v10715; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma716; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12717; ZVFHMIN-NEXT: ret718 %head = insertelement <vscale x 4 x half> poison, half %c, i32 0719 %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer720 %vd = call <vscale x 4 x half> @llvm.fma.v4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %splat, <vscale x 4 x half> %vb)721 ret <vscale x 4 x half> %vd722}723 724define <vscale x 8 x half> @vfmadd_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x half> %vc) {725; ZVFH-LABEL: vfmadd_vv_nxv8f16:726; ZVFH: # %bb.0:727; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma728; ZVFH-NEXT: vfmacc.vv v8, v12, v10729; ZVFH-NEXT: ret730;731; ZVFHMIN-LABEL: vfmadd_vv_nxv8f16:732; ZVFHMIN: # %bb.0:733; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma734; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8735; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10736; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12737; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma738; ZVFHMIN-NEXT: vfmadd.vv v24, v20, v16739; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma740; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24741; ZVFHMIN-NEXT: ret742 %vd = call <vscale x 8 x half> @llvm.fma.v8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %vc, <vscale x 8 x half> %va)743 ret <vscale x 8 x half> %vd744}745 746define <vscale x 8 x half> @vfmadd_vf_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, half %c) {747; ZVFH-LABEL: vfmadd_vf_nxv8f16:748; ZVFH: # %bb.0:749; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma750; ZVFH-NEXT: vfmacc.vf v8, fa0, v10751; ZVFH-NEXT: ret752;753; ZVFHMIN-LABEL: vfmadd_vf_nxv8f16:754; ZVFHMIN: # %bb.0:755; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma756; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8757; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0758; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10759; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma760; ZVFHMIN-NEXT: vfmadd.vf v16, fa5, v12761; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma762; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16763; ZVFHMIN-NEXT: ret764 %head = insertelement <vscale x 8 x half> poison, half %c, i32 0765 %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer766 %vd = call <vscale x 8 x half> @llvm.fma.v8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %splat, <vscale x 8 x half> %va)767 ret <vscale x 8 x half> %vd768}769 770define <vscale x 16 x half> @vfmadd_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x half> %vc) {771; ZVFH-LABEL: vfmadd_vv_nxv16f16:772; ZVFH: # %bb.0:773; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma774; ZVFH-NEXT: vfmadd.vv v8, v16, v12775; ZVFH-NEXT: ret776;777; ZVFHMIN-LABEL: vfmadd_vv_nxv16f16:778; ZVFHMIN: # %bb.0:779; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma780; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12781; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16782; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8783; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma784; ZVFHMIN-NEXT: vfmadd.vv v16, v0, v24785; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma786; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16787; ZVFHMIN-NEXT: ret788 %vd = call <vscale x 16 x half> @llvm.fma.v16f16(<vscale x 16 x half> %vc, <vscale x 16 x half> %va, <vscale x 16 x half> %vb)789 ret <vscale x 16 x half> %vd790}791 792define <vscale x 16 x half> @vfmadd_vf_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, half %c) {793; ZVFH-LABEL: vfmadd_vf_nxv16f16:794; ZVFH: # %bb.0:795; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma796; ZVFH-NEXT: vfmadd.vf v8, fa0, v12797; ZVFH-NEXT: ret798;799; ZVFHMIN-LABEL: vfmadd_vf_nxv16f16:800; ZVFHMIN: # %bb.0:801; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma802; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12803; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0804; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8805; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma806; ZVFHMIN-NEXT: vfmadd.vf v24, fa5, v16807; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma808; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24809; ZVFHMIN-NEXT: ret810 %head = insertelement <vscale x 16 x half> poison, half %c, i32 0811 %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer812 %vd = call <vscale x 16 x half> @llvm.fma.v16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %splat, <vscale x 16 x half> %vb)813 ret <vscale x 16 x half> %vd814}815 816define <vscale x 32 x half> @vfmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x half> %vc) {817; ZVFH-LABEL: vfmadd_vv_nxv32f16:818; ZVFH: # %bb.0:819; ZVFH-NEXT: vl8re16.v v24, (a0)820; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma821; ZVFH-NEXT: vfmacc.vv v8, v16, v24822; ZVFH-NEXT: ret823;824; ZVFHMIN-LABEL: vfmadd_vv_nxv32f16:825; ZVFHMIN: # %bb.0:826; ZVFHMIN-NEXT: addi sp, sp, -16827; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16828; ZVFHMIN-NEXT: csrr a1, vlenb829; ZVFHMIN-NEXT: slli a1, a1, 5830; ZVFHMIN-NEXT: sub sp, sp, a1831; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb832; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma833; ZVFHMIN-NEXT: vmv8r.v v0, v16834; ZVFHMIN-NEXT: csrr a1, vlenb835; ZVFHMIN-NEXT: slli a1, a1, 3836; ZVFHMIN-NEXT: add a1, sp, a1837; ZVFHMIN-NEXT: addi a1, a1, 16838; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill839; ZVFHMIN-NEXT: vl8re16.v v16, (a0)840; ZVFHMIN-NEXT: csrr a0, vlenb841; ZVFHMIN-NEXT: li a1, 24842; ZVFHMIN-NEXT: mul a0, a0, a1843; ZVFHMIN-NEXT: add a0, sp, a0844; ZVFHMIN-NEXT: addi a0, a0, 16845; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill846; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8847; ZVFHMIN-NEXT: csrr a0, vlenb848; ZVFHMIN-NEXT: slli a0, a0, 4849; ZVFHMIN-NEXT: add a0, sp, a0850; ZVFHMIN-NEXT: addi a0, a0, 16851; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill852; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0853; ZVFHMIN-NEXT: addi a0, sp, 16854; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill855; ZVFHMIN-NEXT: csrr a0, vlenb856; ZVFHMIN-NEXT: li a1, 24857; ZVFHMIN-NEXT: mul a0, a0, a1858; ZVFHMIN-NEXT: add a0, sp, a0859; ZVFHMIN-NEXT: addi a0, a0, 16860; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload861; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16862; ZVFHMIN-NEXT: csrr a0, vlenb863; ZVFHMIN-NEXT: slli a0, a0, 4864; ZVFHMIN-NEXT: add a0, sp, a0865; ZVFHMIN-NEXT: addi a0, a0, 16866; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload867; ZVFHMIN-NEXT: addi a0, sp, 16868; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload869; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma870; ZVFHMIN-NEXT: vfmadd.vv v0, v16, v24871; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma872; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12873; ZVFHMIN-NEXT: csrr a0, vlenb874; ZVFHMIN-NEXT: slli a0, a0, 4875; ZVFHMIN-NEXT: add a0, sp, a0876; ZVFHMIN-NEXT: addi a0, a0, 16877; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill878; ZVFHMIN-NEXT: csrr a0, vlenb879; ZVFHMIN-NEXT: slli a0, a0, 3880; ZVFHMIN-NEXT: add a0, sp, a0881; ZVFHMIN-NEXT: addi a0, a0, 16882; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload883; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28884; ZVFHMIN-NEXT: csrr a0, vlenb885; ZVFHMIN-NEXT: li a1, 24886; ZVFHMIN-NEXT: mul a0, a0, a1887; ZVFHMIN-NEXT: add a0, sp, a0888; ZVFHMIN-NEXT: addi a0, a0, 16889; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload890; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28891; ZVFHMIN-NEXT: csrr a0, vlenb892; ZVFHMIN-NEXT: slli a0, a0, 4893; ZVFHMIN-NEXT: add a0, sp, a0894; ZVFHMIN-NEXT: addi a0, a0, 16895; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload896; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma897; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24898; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma899; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0900; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16901; ZVFHMIN-NEXT: csrr a0, vlenb902; ZVFHMIN-NEXT: slli a0, a0, 5903; ZVFHMIN-NEXT: add sp, sp, a0904; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16905; ZVFHMIN-NEXT: addi sp, sp, 16906; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0907; ZVFHMIN-NEXT: ret908 %vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %vc, <vscale x 32 x half> %vb, <vscale x 32 x half> %va)909 ret <vscale x 32 x half> %vd910}911 912define <vscale x 32 x half> @vfmadd_vf_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, half %c) {913; ZVFH-LABEL: vfmadd_vf_nxv32f16:914; ZVFH: # %bb.0:915; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma916; ZVFH-NEXT: vfmacc.vf v8, fa0, v16917; ZVFH-NEXT: ret918;919; ZVFHMIN-LABEL: vfmadd_vf_nxv32f16:920; ZVFHMIN: # %bb.0:921; ZVFHMIN-NEXT: addi sp, sp, -16922; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16923; ZVFHMIN-NEXT: csrr a0, vlenb924; ZVFHMIN-NEXT: slli a0, a0, 5925; ZVFHMIN-NEXT: sub sp, sp, a0926; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb927; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma928; ZVFHMIN-NEXT: vmv8r.v v24, v16929; ZVFHMIN-NEXT: csrr a0, vlenb930; ZVFHMIN-NEXT: slli a0, a0, 4931; ZVFHMIN-NEXT: add a0, sp, a0932; ZVFHMIN-NEXT: addi a0, a0, 16933; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill934; ZVFHMIN-NEXT: vmv8r.v v16, v8935; ZVFHMIN-NEXT: addi a0, sp, 16936; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill937; ZVFHMIN-NEXT: fmv.x.h a0, fa0938; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16939; ZVFHMIN-NEXT: csrr a1, vlenb940; ZVFHMIN-NEXT: li a2, 24941; ZVFHMIN-NEXT: mul a1, a1, a2942; ZVFHMIN-NEXT: add a1, sp, a1943; ZVFHMIN-NEXT: addi a1, a1, 16944; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill945; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24946; ZVFHMIN-NEXT: csrr a1, vlenb947; ZVFHMIN-NEXT: slli a1, a1, 3948; ZVFHMIN-NEXT: add a1, sp, a1949; ZVFHMIN-NEXT: addi a1, a1, 16950; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill951; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma952; ZVFHMIN-NEXT: vmv.v.x v8, a0953; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma954; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8955; ZVFHMIN-NEXT: csrr a0, vlenb956; ZVFHMIN-NEXT: li a1, 24957; ZVFHMIN-NEXT: mul a0, a0, a1958; ZVFHMIN-NEXT: add a0, sp, a0959; ZVFHMIN-NEXT: addi a0, a0, 16960; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload961; ZVFHMIN-NEXT: csrr a0, vlenb962; ZVFHMIN-NEXT: slli a0, a0, 3963; ZVFHMIN-NEXT: add a0, sp, a0964; ZVFHMIN-NEXT: addi a0, a0, 16965; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload966; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma967; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v0968; ZVFHMIN-NEXT: addi a0, sp, 16969; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload970; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma971; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v20972; ZVFHMIN-NEXT: csrr a0, vlenb973; ZVFHMIN-NEXT: li a1, 24974; ZVFHMIN-NEXT: mul a0, a0, a1975; ZVFHMIN-NEXT: add a0, sp, a0976; ZVFHMIN-NEXT: addi a0, a0, 16977; ZVFHMIN-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill978; ZVFHMIN-NEXT: csrr a0, vlenb979; ZVFHMIN-NEXT: slli a0, a0, 4980; ZVFHMIN-NEXT: add a0, sp, a0981; ZVFHMIN-NEXT: addi a0, a0, 16982; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload983; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4984; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v12985; ZVFHMIN-NEXT: csrr a0, vlenb986; ZVFHMIN-NEXT: li a1, 24987; ZVFHMIN-NEXT: mul a0, a0, a1988; ZVFHMIN-NEXT: add a0, sp, a0989; ZVFHMIN-NEXT: addi a0, a0, 16990; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload991; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma992; ZVFHMIN-NEXT: vfmadd.vv v0, v16, v8993; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma994; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24995; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v0996; ZVFHMIN-NEXT: csrr a0, vlenb997; ZVFHMIN-NEXT: slli a0, a0, 5998; ZVFHMIN-NEXT: add sp, sp, a0999; ZVFHMIN-NEXT: .cfi_def_cfa sp, 161000; ZVFHMIN-NEXT: addi sp, sp, 161001; ZVFHMIN-NEXT: .cfi_def_cfa_offset 01002; ZVFHMIN-NEXT: ret1003 %head = insertelement <vscale x 32 x half> poison, half %c, i32 01004 %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> poison, <vscale x 32 x i32> zeroinitializer1005 %vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %vb, <vscale x 32 x half> %splat, <vscale x 32 x half> %va)1006 ret <vscale x 32 x half> %vd1007}1008 1009define <vscale x 1 x float> @vfmadd_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x float> %vc) {1010; CHECK-LABEL: vfmadd_vv_nxv1f32:1011; CHECK: # %bb.0:1012; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1013; CHECK-NEXT: vfmadd.vv v8, v9, v101014; CHECK-NEXT: ret1015 %vd = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x float> %vc)1016 ret <vscale x 1 x float> %vd1017}1018 1019define <vscale x 1 x float> @vfmadd_vf_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, float %c) {1020; CHECK-LABEL: vfmadd_vf_nxv1f32:1021; CHECK: # %bb.0:1022; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1023; CHECK-NEXT: vfmadd.vf v8, fa0, v91024; CHECK-NEXT: ret1025 %head = insertelement <vscale x 1 x float> poison, float %c, i32 01026 %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer1027 %vd = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %splat, <vscale x 1 x float> %vb)1028 ret <vscale x 1 x float> %vd1029}1030 1031define <vscale x 2 x float> @vfmadd_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x float> %vc) {1032; CHECK-LABEL: vfmadd_vv_nxv2f32:1033; CHECK: # %bb.0:1034; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1035; CHECK-NEXT: vfmadd.vv v8, v10, v91036; CHECK-NEXT: ret1037 %vd = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vc, <vscale x 2 x float> %vb)1038 ret <vscale x 2 x float> %vd1039}1040 1041define <vscale x 2 x float> @vfmadd_vf_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, float %c) {1042; CHECK-LABEL: vfmadd_vf_nxv2f32:1043; CHECK: # %bb.0:1044; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1045; CHECK-NEXT: vfmacc.vf v8, fa0, v91046; CHECK-NEXT: ret1047 %head = insertelement <vscale x 2 x float> poison, float %c, i32 01048 %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer1049 %vd = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vb, <vscale x 2 x float> %splat, <vscale x 2 x float> %va)1050 ret <vscale x 2 x float> %vd1051}1052 1053define <vscale x 4 x float> @vfmadd_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x float> %vc) {1054; CHECK-LABEL: vfmadd_vv_nxv4f32:1055; CHECK: # %bb.0:1056; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma1057; CHECK-NEXT: vfmadd.vv v8, v10, v121058; CHECK-NEXT: ret1059 %vd = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vb, <vscale x 4 x float> %va, <vscale x 4 x float> %vc)1060 ret <vscale x 4 x float> %vd1061}1062 1063define <vscale x 4 x float> @vfmadd_vf_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, float %c) {1064; CHECK-LABEL: vfmadd_vf_nxv4f32:1065; CHECK: # %bb.0:1066; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma1067; CHECK-NEXT: vfmadd.vf v8, fa0, v101068; CHECK-NEXT: ret1069 %head = insertelement <vscale x 4 x float> poison, float %c, i32 01070 %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer1071 %vd = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %splat, <vscale x 4 x float> %vb)1072 ret <vscale x 4 x float> %vd1073}1074 1075define <vscale x 8 x float> @vfmadd_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x float> %vc) {1076; CHECK-LABEL: vfmadd_vv_nxv8f32:1077; CHECK: # %bb.0:1078; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1079; CHECK-NEXT: vfmacc.vv v8, v16, v121080; CHECK-NEXT: ret1081 %vd = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vb, <vscale x 8 x float> %vc, <vscale x 8 x float> %va)1082 ret <vscale x 8 x float> %vd1083}1084 1085define <vscale x 8 x float> @vfmadd_vf_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, float %c) {1086; CHECK-LABEL: vfmadd_vf_nxv8f32:1087; CHECK: # %bb.0:1088; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1089; CHECK-NEXT: vfmacc.vf v8, fa0, v121090; CHECK-NEXT: ret1091 %head = insertelement <vscale x 8 x float> poison, float %c, i32 01092 %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer1093 %vd = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vb, <vscale x 8 x float> %splat, <vscale x 8 x float> %va)1094 ret <vscale x 8 x float> %vd1095}1096 1097define <vscale x 16 x float> @vfmadd_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x float> %vc) {1098; CHECK-LABEL: vfmadd_vv_nxv16f32:1099; CHECK: # %bb.0:1100; CHECK-NEXT: vl8re32.v v24, (a0)1101; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma1102; CHECK-NEXT: vfmadd.vv v8, v24, v161103; CHECK-NEXT: ret1104 %vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vc, <vscale x 16 x float> %va, <vscale x 16 x float> %vb)1105 ret <vscale x 16 x float> %vd1106}1107 1108define <vscale x 16 x float> @vfmadd_vf_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, float %c) {1109; CHECK-LABEL: vfmadd_vf_nxv16f32:1110; CHECK: # %bb.0:1111; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma1112; CHECK-NEXT: vfmadd.vf v8, fa0, v161113; CHECK-NEXT: ret1114 %head = insertelement <vscale x 16 x float> poison, float %c, i32 01115 %splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> poison, <vscale x 16 x i32> zeroinitializer1116 %vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %splat, <vscale x 16 x float> %vb)1117 ret <vscale x 16 x float> %vd1118}1119 1120define <vscale x 1 x double> @vfmadd_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x double> %vc) {1121; CHECK-LABEL: vfmadd_vv_nxv1f64:1122; CHECK: # %bb.0:1123; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma1124; CHECK-NEXT: vfmadd.vv v8, v9, v101125; CHECK-NEXT: ret1126 %vd = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x double> %vc)1127 ret <vscale x 1 x double> %vd1128}1129 1130define <vscale x 1 x double> @vfmadd_vf_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, double %c) {1131; CHECK-LABEL: vfmadd_vf_nxv1f64:1132; CHECK: # %bb.0:1133; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma1134; CHECK-NEXT: vfmadd.vf v8, fa0, v91135; CHECK-NEXT: ret1136 %head = insertelement <vscale x 1 x double> poison, double %c, i32 01137 %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer1138 %vd = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %splat, <vscale x 1 x double> %vb)1139 ret <vscale x 1 x double> %vd1140}1141 1142define <vscale x 2 x double> @vfmadd_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x double> %vc) {1143; CHECK-LABEL: vfmadd_vv_nxv2f64:1144; CHECK: # %bb.0:1145; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma1146; CHECK-NEXT: vfmadd.vv v8, v12, v101147; CHECK-NEXT: ret1148 %vd = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vc, <vscale x 2 x double> %vb)1149 ret <vscale x 2 x double> %vd1150}1151 1152define <vscale x 2 x double> @vfmadd_vf_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, double %c) {1153; CHECK-LABEL: vfmadd_vf_nxv2f64:1154; CHECK: # %bb.0:1155; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma1156; CHECK-NEXT: vfmacc.vf v8, fa0, v101157; CHECK-NEXT: ret1158 %head = insertelement <vscale x 2 x double> poison, double %c, i32 01159 %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer1160 %vd = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vb, <vscale x 2 x double> %splat, <vscale x 2 x double> %va)1161 ret <vscale x 2 x double> %vd1162}1163 1164define <vscale x 4 x double> @vfmadd_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x double> %vc) {1165; CHECK-LABEL: vfmadd_vv_nxv4f64:1166; CHECK: # %bb.0:1167; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma1168; CHECK-NEXT: vfmadd.vv v8, v12, v161169; CHECK-NEXT: ret1170 %vd = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vb, <vscale x 4 x double> %va, <vscale x 4 x double> %vc)1171 ret <vscale x 4 x double> %vd1172}1173 1174define <vscale x 4 x double> @vfmadd_vf_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, double %c) {1175; CHECK-LABEL: vfmadd_vf_nxv4f64:1176; CHECK: # %bb.0:1177; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma1178; CHECK-NEXT: vfmadd.vf v8, fa0, v121179; CHECK-NEXT: ret1180 %head = insertelement <vscale x 4 x double> poison, double %c, i32 01181 %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer1182 %vd = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %splat, <vscale x 4 x double> %vb)1183 ret <vscale x 4 x double> %vd1184}1185 1186define <vscale x 8 x double> @vfmadd_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x double> %vc) {1187; CHECK-LABEL: vfmadd_vv_nxv8f64:1188; CHECK: # %bb.0:1189; CHECK-NEXT: vl8re64.v v24, (a0)1190; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1191; CHECK-NEXT: vfmacc.vv v8, v16, v241192; CHECK-NEXT: ret1193 %vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %vc, <vscale x 8 x double> %va)1194 ret <vscale x 8 x double> %vd1195}1196 1197define <vscale x 8 x double> @vfmadd_vf_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, double %c) {1198; CHECK-LABEL: vfmadd_vf_nxv8f64:1199; CHECK: # %bb.0:1200; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1201; CHECK-NEXT: vfmacc.vf v8, fa0, v161202; CHECK-NEXT: ret1203 %head = insertelement <vscale x 8 x double> poison, double %c, i32 01204 %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer1205 %vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %splat, <vscale x 8 x double> %va)1206 ret <vscale x 8 x double> %vd1207}1208