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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN14 15define <vscale x 1 x bfloat> @vfmax_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {16; CHECK-LABEL: vfmax_vv_nxv1bf16:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma19; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9, v0.t20; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t21; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma22; CHECK-NEXT: vfmax.vv v9, v9, v10, v0.t23; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma24; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t25; CHECK-NEXT: ret26 %v = call <vscale x 1 x bfloat> @llvm.vp.maxnum.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 %evl)27 ret <vscale x 1 x bfloat> %v28}29 30define <vscale x 1 x bfloat> @vfmax_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, i32 zeroext %evl) {31; CHECK-LABEL: vfmax_vv_nxv1bf16_unmasked:32; CHECK: # %bb.0:33; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma34; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v935; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v836; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma37; CHECK-NEXT: vfmax.vv v9, v9, v1038; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma39; CHECK-NEXT: vfncvtbf16.f.f.w v8, v940; CHECK-NEXT: ret41 %v = call <vscale x 1 x bfloat> @llvm.vp.maxnum.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)42 ret <vscale x 1 x bfloat> %v43}44 45define <vscale x 2 x bfloat> @vfmax_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {46; CHECK-LABEL: vfmax_vv_nxv2bf16:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma49; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9, v0.t50; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t51; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma52; CHECK-NEXT: vfmax.vv v9, v9, v10, v0.t53; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma54; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t55; CHECK-NEXT: ret56 %v = call <vscale x 2 x bfloat> @llvm.vp.maxnum.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 %evl)57 ret <vscale x 2 x bfloat> %v58}59 60define <vscale x 2 x bfloat> @vfmax_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evl) {61; CHECK-LABEL: vfmax_vv_nxv2bf16_unmasked:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma64; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v965; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v866; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma67; CHECK-NEXT: vfmax.vv v9, v9, v1068; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma69; CHECK-NEXT: vfncvtbf16.f.f.w v8, v970; CHECK-NEXT: ret71 %v = call <vscale x 2 x bfloat> @llvm.vp.maxnum.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)72 ret <vscale x 2 x bfloat> %v73}74 75define <vscale x 4 x bfloat> @vfmax_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {76; CHECK-LABEL: vfmax_vv_nxv4bf16:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma79; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9, v0.t80; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t81; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma82; CHECK-NEXT: vfmax.vv v10, v12, v10, v0.t83; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma84; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t85; CHECK-NEXT: ret86 %v = call <vscale x 4 x bfloat> @llvm.vp.maxnum.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 %evl)87 ret <vscale x 4 x bfloat> %v88}89 90define <vscale x 4 x bfloat> @vfmax_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, i32 zeroext %evl) {91; CHECK-LABEL: vfmax_vv_nxv4bf16_unmasked:92; CHECK: # %bb.0:93; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma94; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v995; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v896; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma97; CHECK-NEXT: vfmax.vv v10, v12, v1098; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma99; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10100; CHECK-NEXT: ret101 %v = call <vscale x 4 x bfloat> @llvm.vp.maxnum.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)102 ret <vscale x 4 x bfloat> %v103}104 105define <vscale x 8 x bfloat> @vfmax_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {106; CHECK-LABEL: vfmax_vv_nxv8bf16:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma109; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v10, v0.t110; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t111; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma112; CHECK-NEXT: vfmax.vv v12, v16, v12, v0.t113; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma114; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t115; CHECK-NEXT: ret116 %v = call <vscale x 8 x bfloat> @llvm.vp.maxnum.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 %evl)117 ret <vscale x 8 x bfloat> %v118}119 120define <vscale x 8 x bfloat> @vfmax_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, i32 zeroext %evl) {121; CHECK-LABEL: vfmax_vv_nxv8bf16_unmasked:122; CHECK: # %bb.0:123; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma124; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v10125; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8126; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma127; CHECK-NEXT: vfmax.vv v12, v16, v12128; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma129; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12130; CHECK-NEXT: ret131 %v = call <vscale x 8 x bfloat> @llvm.vp.maxnum.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)132 ret <vscale x 8 x bfloat> %v133}134 135define <vscale x 16 x bfloat> @vfmax_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {136; CHECK-LABEL: vfmax_vv_nxv16bf16:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma139; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t140; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t141; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma142; CHECK-NEXT: vfmax.vv v16, v24, v16, v0.t143; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma144; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t145; CHECK-NEXT: ret146 %v = call <vscale x 16 x bfloat> @llvm.vp.maxnum.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 %evl)147 ret <vscale x 16 x bfloat> %v148}149 150define <vscale x 16 x bfloat> @vfmax_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, i32 zeroext %evl) {151; CHECK-LABEL: vfmax_vv_nxv16bf16_unmasked:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma154; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12155; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8156; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma157; CHECK-NEXT: vfmax.vv v16, v24, v16158; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma159; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16160; CHECK-NEXT: ret161 %v = call <vscale x 16 x bfloat> @llvm.vp.maxnum.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)162 ret <vscale x 16 x bfloat> %v163}164 165define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {166; CHECK-LABEL: vfmax_vv_nxv32bf16:167; CHECK: # %bb.0:168; CHECK-NEXT: addi sp, sp, -16169; CHECK-NEXT: .cfi_def_cfa_offset 16170; CHECK-NEXT: csrr a1, vlenb171; CHECK-NEXT: slli a1, a1, 3172; CHECK-NEXT: sub sp, sp, a1173; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb174; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma175; CHECK-NEXT: vmv1r.v v7, v0176; CHECK-NEXT: csrr a2, vlenb177; CHECK-NEXT: slli a1, a2, 1178; CHECK-NEXT: srli a2, a2, 2179; CHECK-NEXT: sub a3, a0, a1180; CHECK-NEXT: vslidedown.vx v0, v0, a2181; CHECK-NEXT: sltu a2, a0, a3182; CHECK-NEXT: addi a2, a2, -1183; CHECK-NEXT: and a2, a2, a3184; CHECK-NEXT: addi a3, sp, 16185; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill186; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma187; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t188; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t189; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma190; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t191; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma192; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t193; CHECK-NEXT: bltu a0, a1, .LBB10_2194; CHECK-NEXT: # %bb.1:195; CHECK-NEXT: mv a0, a1196; CHECK-NEXT: .LBB10_2:197; CHECK-NEXT: vmv1r.v v0, v7198; CHECK-NEXT: addi a1, sp, 16199; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload200; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma201; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t202; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t203; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma204; CHECK-NEXT: vfmax.vv v16, v24, v16, v0.t205; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma206; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t207; CHECK-NEXT: csrr a0, vlenb208; CHECK-NEXT: slli a0, a0, 3209; CHECK-NEXT: add sp, sp, a0210; CHECK-NEXT: .cfi_def_cfa sp, 16211; CHECK-NEXT: addi sp, sp, 16212; CHECK-NEXT: .cfi_def_cfa_offset 0213; CHECK-NEXT: ret214 %v = call <vscale x 32 x bfloat> @llvm.vp.maxnum.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 %evl)215 ret <vscale x 32 x bfloat> %v216}217 218define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, i32 zeroext %evl) {219; CHECK-LABEL: vfmax_vv_nxv32bf16_unmasked:220; CHECK: # %bb.0:221; CHECK-NEXT: addi sp, sp, -16222; CHECK-NEXT: .cfi_def_cfa_offset 16223; CHECK-NEXT: csrr a1, vlenb224; CHECK-NEXT: slli a1, a1, 3225; CHECK-NEXT: sub sp, sp, a1226; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb227; CHECK-NEXT: csrr a2, vlenb228; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma229; CHECK-NEXT: vmset.m v24230; CHECK-NEXT: slli a1, a2, 1231; CHECK-NEXT: srli a2, a2, 2232; CHECK-NEXT: sub a3, a0, a1233; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma234; CHECK-NEXT: vslidedown.vx v0, v24, a2235; CHECK-NEXT: sltu a2, a0, a3236; CHECK-NEXT: addi a2, a2, -1237; CHECK-NEXT: and a2, a2, a3238; CHECK-NEXT: addi a3, sp, 16239; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill240; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma241; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t242; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t243; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma244; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t245; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma246; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t247; CHECK-NEXT: bltu a0, a1, .LBB11_2248; CHECK-NEXT: # %bb.1:249; CHECK-NEXT: mv a0, a1250; CHECK-NEXT: .LBB11_2:251; CHECK-NEXT: addi a1, sp, 16252; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload253; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma254; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24255; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8256; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma257; CHECK-NEXT: vfmax.vv v16, v24, v16258; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma259; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16260; CHECK-NEXT: csrr a0, vlenb261; CHECK-NEXT: slli a0, a0, 3262; CHECK-NEXT: add sp, sp, a0263; CHECK-NEXT: .cfi_def_cfa sp, 16264; CHECK-NEXT: addi sp, sp, 16265; CHECK-NEXT: .cfi_def_cfa_offset 0266; CHECK-NEXT: ret267 %v = call <vscale x 32 x bfloat> @llvm.vp.maxnum.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)268 ret <vscale x 32 x bfloat> %v269}270 271define <vscale x 1 x half> @vfmax_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {272; ZVFH-LABEL: vfmax_vv_nxv1f16:273; ZVFH: # %bb.0:274; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma275; ZVFH-NEXT: vfmax.vv v8, v8, v9, v0.t276; ZVFH-NEXT: ret277;278; ZVFHMIN-LABEL: vfmax_vv_nxv1f16:279; ZVFHMIN: # %bb.0:280; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma281; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t282; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t283; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma284; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10, v0.t285; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma286; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t287; ZVFHMIN-NEXT: ret288 %v = call <vscale x 1 x half> @llvm.vp.maxnum.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 %evl)289 ret <vscale x 1 x half> %v290}291 292define <vscale x 1 x half> @vfmax_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, i32 zeroext %evl) {293; ZVFH-LABEL: vfmax_vv_nxv1f16_unmasked:294; ZVFH: # %bb.0:295; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma296; ZVFH-NEXT: vfmax.vv v8, v8, v9297; ZVFH-NEXT: ret298;299; ZVFHMIN-LABEL: vfmax_vv_nxv1f16_unmasked:300; ZVFHMIN: # %bb.0:301; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma302; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9303; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8304; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma305; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10306; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma307; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9308; ZVFHMIN-NEXT: ret309 %v = call <vscale x 1 x half> @llvm.vp.maxnum.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)310 ret <vscale x 1 x half> %v311}312 313define <vscale x 2 x half> @vfmax_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {314; ZVFH-LABEL: vfmax_vv_nxv2f16:315; ZVFH: # %bb.0:316; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma317; ZVFH-NEXT: vfmax.vv v8, v8, v9, v0.t318; ZVFH-NEXT: ret319;320; ZVFHMIN-LABEL: vfmax_vv_nxv2f16:321; ZVFHMIN: # %bb.0:322; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma323; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t324; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t325; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma326; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10, v0.t327; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma328; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t329; ZVFHMIN-NEXT: ret330 %v = call <vscale x 2 x half> @llvm.vp.maxnum.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %m, i32 %evl)331 ret <vscale x 2 x half> %v332}333 334define <vscale x 2 x half> @vfmax_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 zeroext %evl) {335; ZVFH-LABEL: vfmax_vv_nxv2f16_unmasked:336; ZVFH: # %bb.0:337; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma338; ZVFH-NEXT: vfmax.vv v8, v8, v9339; ZVFH-NEXT: ret340;341; ZVFHMIN-LABEL: vfmax_vv_nxv2f16_unmasked:342; ZVFHMIN: # %bb.0:343; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma344; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9345; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8346; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma347; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10348; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma349; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9350; ZVFHMIN-NEXT: ret351 %v = call <vscale x 2 x half> @llvm.vp.maxnum.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)352 ret <vscale x 2 x half> %v353}354 355define <vscale x 4 x half> @vfmax_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {356; ZVFH-LABEL: vfmax_vv_nxv4f16:357; ZVFH: # %bb.0:358; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma359; ZVFH-NEXT: vfmax.vv v8, v8, v9, v0.t360; ZVFH-NEXT: ret361;362; ZVFHMIN-LABEL: vfmax_vv_nxv4f16:363; ZVFHMIN: # %bb.0:364; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma365; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t366; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t367; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma368; ZVFHMIN-NEXT: vfmax.vv v10, v12, v10, v0.t369; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma370; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t371; ZVFHMIN-NEXT: ret372 %v = call <vscale x 4 x half> @llvm.vp.maxnum.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %m, i32 %evl)373 ret <vscale x 4 x half> %v374}375 376define <vscale x 4 x half> @vfmax_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, i32 zeroext %evl) {377; ZVFH-LABEL: vfmax_vv_nxv4f16_unmasked:378; ZVFH: # %bb.0:379; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma380; ZVFH-NEXT: vfmax.vv v8, v8, v9381; ZVFH-NEXT: ret382;383; ZVFHMIN-LABEL: vfmax_vv_nxv4f16_unmasked:384; ZVFHMIN: # %bb.0:385; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma386; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9387; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8388; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma389; ZVFHMIN-NEXT: vfmax.vv v10, v12, v10390; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma391; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10392; ZVFHMIN-NEXT: ret393 %v = call <vscale x 4 x half> @llvm.vp.maxnum.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)394 ret <vscale x 4 x half> %v395}396 397define <vscale x 8 x half> @vfmax_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {398; ZVFH-LABEL: vfmax_vv_nxv8f16:399; ZVFH: # %bb.0:400; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma401; ZVFH-NEXT: vfmax.vv v8, v8, v10, v0.t402; ZVFH-NEXT: ret403;404; ZVFHMIN-LABEL: vfmax_vv_nxv8f16:405; ZVFHMIN: # %bb.0:406; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma407; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t408; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t409; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma410; ZVFHMIN-NEXT: vfmax.vv v12, v16, v12, v0.t411; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma412; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t413; ZVFHMIN-NEXT: ret414 %v = call <vscale x 8 x half> @llvm.vp.maxnum.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 %evl)415 ret <vscale x 8 x half> %v416}417 418define <vscale x 8 x half> @vfmax_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, i32 zeroext %evl) {419; ZVFH-LABEL: vfmax_vv_nxv8f16_unmasked:420; ZVFH: # %bb.0:421; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma422; ZVFH-NEXT: vfmax.vv v8, v8, v10423; ZVFH-NEXT: ret424;425; ZVFHMIN-LABEL: vfmax_vv_nxv8f16_unmasked:426; ZVFHMIN: # %bb.0:427; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma428; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10429; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8430; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma431; ZVFHMIN-NEXT: vfmax.vv v12, v16, v12432; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma433; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12434; ZVFHMIN-NEXT: ret435 %v = call <vscale x 8 x half> @llvm.vp.maxnum.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)436 ret <vscale x 8 x half> %v437}438 439define <vscale x 16 x half> @vfmax_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {440; ZVFH-LABEL: vfmax_vv_nxv16f16:441; ZVFH: # %bb.0:442; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma443; ZVFH-NEXT: vfmax.vv v8, v8, v12, v0.t444; ZVFH-NEXT: ret445;446; ZVFHMIN-LABEL: vfmax_vv_nxv16f16:447; ZVFHMIN: # %bb.0:448; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma449; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t450; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t451; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma452; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16, v0.t453; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma454; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t455; ZVFHMIN-NEXT: ret456 %v = call <vscale x 16 x half> @llvm.vp.maxnum.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %m, i32 %evl)457 ret <vscale x 16 x half> %v458}459 460define <vscale x 16 x half> @vfmax_vv_nxv16f16_unmasked(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, i32 zeroext %evl) {461; ZVFH-LABEL: vfmax_vv_nxv16f16_unmasked:462; ZVFH: # %bb.0:463; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma464; ZVFH-NEXT: vfmax.vv v8, v8, v12465; ZVFH-NEXT: ret466;467; ZVFHMIN-LABEL: vfmax_vv_nxv16f16_unmasked:468; ZVFHMIN: # %bb.0:469; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma470; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12471; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8472; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma473; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16474; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma475; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16476; ZVFHMIN-NEXT: ret477 %v = call <vscale x 16 x half> @llvm.vp.maxnum.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)478 ret <vscale x 16 x half> %v479}480 481define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {482; ZVFH-LABEL: vfmax_vv_nxv32f16:483; ZVFH: # %bb.0:484; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma485; ZVFH-NEXT: vfmax.vv v8, v8, v16, v0.t486; ZVFH-NEXT: ret487;488; ZVFHMIN-LABEL: vfmax_vv_nxv32f16:489; ZVFHMIN: # %bb.0:490; ZVFHMIN-NEXT: addi sp, sp, -16491; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16492; ZVFHMIN-NEXT: csrr a1, vlenb493; ZVFHMIN-NEXT: slli a1, a1, 3494; ZVFHMIN-NEXT: sub sp, sp, a1495; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb496; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma497; ZVFHMIN-NEXT: vmv1r.v v7, v0498; ZVFHMIN-NEXT: csrr a2, vlenb499; ZVFHMIN-NEXT: slli a1, a2, 1500; ZVFHMIN-NEXT: srli a2, a2, 2501; ZVFHMIN-NEXT: sub a3, a0, a1502; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2503; ZVFHMIN-NEXT: sltu a2, a0, a3504; ZVFHMIN-NEXT: addi a2, a2, -1505; ZVFHMIN-NEXT: and a2, a2, a3506; ZVFHMIN-NEXT: addi a3, sp, 16507; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill508; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma509; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t510; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t511; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma512; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t513; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma514; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t515; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2516; ZVFHMIN-NEXT: # %bb.1:517; ZVFHMIN-NEXT: mv a0, a1518; ZVFHMIN-NEXT: .LBB22_2:519; ZVFHMIN-NEXT: vmv1r.v v0, v7520; ZVFHMIN-NEXT: addi a1, sp, 16521; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload522; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma523; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t524; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t525; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma526; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16, v0.t527; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma528; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t529; ZVFHMIN-NEXT: csrr a0, vlenb530; ZVFHMIN-NEXT: slli a0, a0, 3531; ZVFHMIN-NEXT: add sp, sp, a0532; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16533; ZVFHMIN-NEXT: addi sp, sp, 16534; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0535; ZVFHMIN-NEXT: ret536 %v = call <vscale x 32 x half> @llvm.vp.maxnum.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %m, i32 %evl)537 ret <vscale x 32 x half> %v538}539 540define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, i32 zeroext %evl) {541; ZVFH-LABEL: vfmax_vv_nxv32f16_unmasked:542; ZVFH: # %bb.0:543; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma544; ZVFH-NEXT: vfmax.vv v8, v8, v16545; ZVFH-NEXT: ret546;547; ZVFHMIN-LABEL: vfmax_vv_nxv32f16_unmasked:548; ZVFHMIN: # %bb.0:549; ZVFHMIN-NEXT: addi sp, sp, -16550; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16551; ZVFHMIN-NEXT: csrr a1, vlenb552; ZVFHMIN-NEXT: slli a1, a1, 3553; ZVFHMIN-NEXT: sub sp, sp, a1554; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb555; ZVFHMIN-NEXT: csrr a2, vlenb556; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma557; ZVFHMIN-NEXT: vmset.m v24558; ZVFHMIN-NEXT: slli a1, a2, 1559; ZVFHMIN-NEXT: srli a2, a2, 2560; ZVFHMIN-NEXT: sub a3, a0, a1561; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma562; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2563; ZVFHMIN-NEXT: sltu a2, a0, a3564; ZVFHMIN-NEXT: addi a2, a2, -1565; ZVFHMIN-NEXT: and a2, a2, a3566; ZVFHMIN-NEXT: addi a3, sp, 16567; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill568; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma569; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t570; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t571; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma572; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t573; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma574; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t575; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2576; ZVFHMIN-NEXT: # %bb.1:577; ZVFHMIN-NEXT: mv a0, a1578; ZVFHMIN-NEXT: .LBB23_2:579; ZVFHMIN-NEXT: addi a1, sp, 16580; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload581; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma582; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24583; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8584; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma585; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16586; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma587; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16588; ZVFHMIN-NEXT: csrr a0, vlenb589; ZVFHMIN-NEXT: slli a0, a0, 3590; ZVFHMIN-NEXT: add sp, sp, a0591; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16592; ZVFHMIN-NEXT: addi sp, sp, 16593; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0594; ZVFHMIN-NEXT: ret595 %v = call <vscale x 32 x half> @llvm.vp.maxnum.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)596 ret <vscale x 32 x half> %v597}598 599define <vscale x 1 x float> @vfmax_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {600; CHECK-LABEL: vfmax_vv_nxv1f32:601; CHECK: # %bb.0:602; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma603; CHECK-NEXT: vfmax.vv v8, v8, v9, v0.t604; CHECK-NEXT: ret605 %v = call <vscale x 1 x float> @llvm.vp.maxnum.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %m, i32 %evl)606 ret <vscale x 1 x float> %v607}608 609define <vscale x 1 x float> @vfmax_vv_nxv1f32_unmasked(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, i32 zeroext %evl) {610; CHECK-LABEL: vfmax_vv_nxv1f32_unmasked:611; CHECK: # %bb.0:612; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma613; CHECK-NEXT: vfmax.vv v8, v8, v9614; CHECK-NEXT: ret615 %v = call <vscale x 1 x float> @llvm.vp.maxnum.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)616 ret <vscale x 1 x float> %v617}618 619define <vscale x 2 x float> @vfmax_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {620; CHECK-LABEL: vfmax_vv_nxv2f32:621; CHECK: # %bb.0:622; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma623; CHECK-NEXT: vfmax.vv v8, v8, v9, v0.t624; CHECK-NEXT: ret625 %v = call <vscale x 2 x float> @llvm.vp.maxnum.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %m, i32 %evl)626 ret <vscale x 2 x float> %v627}628 629define <vscale x 2 x float> @vfmax_vv_nxv2f32_unmasked(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evl) {630; CHECK-LABEL: vfmax_vv_nxv2f32_unmasked:631; CHECK: # %bb.0:632; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma633; CHECK-NEXT: vfmax.vv v8, v8, v9634; CHECK-NEXT: ret635 %v = call <vscale x 2 x float> @llvm.vp.maxnum.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)636 ret <vscale x 2 x float> %v637}638 639define <vscale x 4 x float> @vfmax_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {640; CHECK-LABEL: vfmax_vv_nxv4f32:641; CHECK: # %bb.0:642; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma643; CHECK-NEXT: vfmax.vv v8, v8, v10, v0.t644; CHECK-NEXT: ret645 %v = call <vscale x 4 x float> @llvm.vp.maxnum.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %m, i32 %evl)646 ret <vscale x 4 x float> %v647}648 649define <vscale x 4 x float> @vfmax_vv_nxv4f32_unmasked(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, i32 zeroext %evl) {650; CHECK-LABEL: vfmax_vv_nxv4f32_unmasked:651; CHECK: # %bb.0:652; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma653; CHECK-NEXT: vfmax.vv v8, v8, v10654; CHECK-NEXT: ret655 %v = call <vscale x 4 x float> @llvm.vp.maxnum.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)656 ret <vscale x 4 x float> %v657}658 659define <vscale x 8 x float> @vfmax_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {660; CHECK-LABEL: vfmax_vv_nxv8f32:661; CHECK: # %bb.0:662; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma663; CHECK-NEXT: vfmax.vv v8, v8, v12, v0.t664; CHECK-NEXT: ret665 %v = call <vscale x 8 x float> @llvm.vp.maxnum.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %m, i32 %evl)666 ret <vscale x 8 x float> %v667}668 669define <vscale x 8 x float> @vfmax_vv_nxv8f32_unmasked(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, i32 zeroext %evl) {670; CHECK-LABEL: vfmax_vv_nxv8f32_unmasked:671; CHECK: # %bb.0:672; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma673; CHECK-NEXT: vfmax.vv v8, v8, v12674; CHECK-NEXT: ret675 %v = call <vscale x 8 x float> @llvm.vp.maxnum.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)676 ret <vscale x 8 x float> %v677}678 679define <vscale x 16 x float> @vfmax_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {680; CHECK-LABEL: vfmax_vv_nxv16f32:681; CHECK: # %bb.0:682; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma683; CHECK-NEXT: vfmax.vv v8, v8, v16, v0.t684; CHECK-NEXT: ret685 %v = call <vscale x 16 x float> @llvm.vp.maxnum.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> %m, i32 %evl)686 ret <vscale x 16 x float> %v687}688 689define <vscale x 16 x float> @vfmax_vv_nxv16f32_unmasked(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, i32 zeroext %evl) {690; CHECK-LABEL: vfmax_vv_nxv16f32_unmasked:691; CHECK: # %bb.0:692; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma693; CHECK-NEXT: vfmax.vv v8, v8, v16694; CHECK-NEXT: ret695 %v = call <vscale x 16 x float> @llvm.vp.maxnum.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)696 ret <vscale x 16 x float> %v697}698 699define <vscale x 1 x double> @vfmax_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {700; CHECK-LABEL: vfmax_vv_nxv1f64:701; CHECK: # %bb.0:702; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma703; CHECK-NEXT: vfmax.vv v8, v8, v9, v0.t704; CHECK-NEXT: ret705 %v = call <vscale x 1 x double> @llvm.vp.maxnum.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 %evl)706 ret <vscale x 1 x double> %v707}708 709define <vscale x 1 x double> @vfmax_vv_nxv1f64_unmasked(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evl) {710; CHECK-LABEL: vfmax_vv_nxv1f64_unmasked:711; CHECK: # %bb.0:712; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma713; CHECK-NEXT: vfmax.vv v8, v8, v9714; CHECK-NEXT: ret715 %v = call <vscale x 1 x double> @llvm.vp.maxnum.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)716 ret <vscale x 1 x double> %v717}718 719define <vscale x 2 x double> @vfmax_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {720; CHECK-LABEL: vfmax_vv_nxv2f64:721; CHECK: # %bb.0:722; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma723; CHECK-NEXT: vfmax.vv v8, v8, v10, v0.t724; CHECK-NEXT: ret725 %v = call <vscale x 2 x double> @llvm.vp.maxnum.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %m, i32 %evl)726 ret <vscale x 2 x double> %v727}728 729define <vscale x 2 x double> @vfmax_vv_nxv2f64_unmasked(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, i32 zeroext %evl) {730; CHECK-LABEL: vfmax_vv_nxv2f64_unmasked:731; CHECK: # %bb.0:732; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma733; CHECK-NEXT: vfmax.vv v8, v8, v10734; CHECK-NEXT: ret735 %v = call <vscale x 2 x double> @llvm.vp.maxnum.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)736 ret <vscale x 2 x double> %v737}738 739define <vscale x 4 x double> @vfmax_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {740; CHECK-LABEL: vfmax_vv_nxv4f64:741; CHECK: # %bb.0:742; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma743; CHECK-NEXT: vfmax.vv v8, v8, v12, v0.t744; CHECK-NEXT: ret745 %v = call <vscale x 4 x double> @llvm.vp.maxnum.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %m, i32 %evl)746 ret <vscale x 4 x double> %v747}748 749define <vscale x 4 x double> @vfmax_vv_nxv4f64_unmasked(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, i32 zeroext %evl) {750; CHECK-LABEL: vfmax_vv_nxv4f64_unmasked:751; CHECK: # %bb.0:752; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma753; CHECK-NEXT: vfmax.vv v8, v8, v12754; CHECK-NEXT: ret755 %v = call <vscale x 4 x double> @llvm.vp.maxnum.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)756 ret <vscale x 4 x double> %v757}758 759define <vscale x 8 x double> @vfmax_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {760; CHECK-LABEL: vfmax_vv_nxv8f64:761; CHECK: # %bb.0:762; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma763; CHECK-NEXT: vfmax.vv v8, v8, v16, v0.t764; CHECK-NEXT: ret765 %v = call <vscale x 8 x double> @llvm.vp.maxnum.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 %evl)766 ret <vscale x 8 x double> %v767}768 769define <vscale x 8 x double> @vfmax_vv_nxv8f64_unmasked(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, i32 zeroext %evl) {770; CHECK-LABEL: vfmax_vv_nxv8f64_unmasked:771; CHECK: # %bb.0:772; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma773; CHECK-NEXT: vfmax.vv v8, v8, v16774; CHECK-NEXT: ret775 %v = call <vscale x 8 x double> @llvm.vp.maxnum.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)776 ret <vscale x 8 x double> %v777}778