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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x bfloat> @intrinsic_vfmin_vv_nxv1bf16_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfmin_vv_nxv1bf16_nxv1bf16_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma11; CHECK-NEXT: vfmin.vv v8, v8, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.nxv1bf16(15 <vscale x 1 x bfloat> poison,16 <vscale x 1 x bfloat> %0,17 <vscale x 1 x bfloat> %1,18 iXLen %2)19 20 ret <vscale x 1 x bfloat> %a21}22 23define <vscale x 1 x bfloat> @intrinsic_vfmin_mask_vv_nxv1bf16_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1bf16_nxv1bf16_nxv1bf16:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu27; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.mask.nxv1bf16.nxv1bf16(31 <vscale x 1 x bfloat> %0,32 <vscale x 1 x bfloat> %1,33 <vscale x 1 x bfloat> %2,34 <vscale x 1 x i1> %3,35 iXLen %4, iXLen 1)36 37 ret <vscale x 1 x bfloat> %a38}39 40define <vscale x 2 x bfloat> @intrinsic_vfmin_vv_nxv2bf16_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vfmin_vv_nxv2bf16_nxv2bf16_nxv2bf16:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma44; CHECK-NEXT: vfmin.vv v8, v8, v945; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.nxv2bf16(48 <vscale x 2 x bfloat> poison,49 <vscale x 2 x bfloat> %0,50 <vscale x 2 x bfloat> %1,51 iXLen %2)52 53 ret <vscale x 2 x bfloat> %a54}55 56define <vscale x 2 x bfloat> @intrinsic_vfmin_mask_vv_nxv2bf16_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2bf16_nxv2bf16_nxv2bf16:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu60; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.mask.nxv2bf16.nxv2bf16(64 <vscale x 2 x bfloat> %0,65 <vscale x 2 x bfloat> %1,66 <vscale x 2 x bfloat> %2,67 <vscale x 2 x i1> %3,68 iXLen %4, iXLen 1)69 70 ret <vscale x 2 x bfloat> %a71}72 73define <vscale x 4 x bfloat> @intrinsic_vfmin_vv_nxv4bf16_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vfmin_vv_nxv4bf16_nxv4bf16_nxv4bf16:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma77; CHECK-NEXT: vfmin.vv v8, v8, v978; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.nxv4bf16(81 <vscale x 4 x bfloat> poison,82 <vscale x 4 x bfloat> %0,83 <vscale x 4 x bfloat> %1,84 iXLen %2)85 86 ret <vscale x 4 x bfloat> %a87}88 89define <vscale x 4 x bfloat> @intrinsic_vfmin_mask_vv_nxv4bf16_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4bf16_nxv4bf16_nxv4bf16:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu93; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.mask.nxv4bf16.nxv4bf16(97 <vscale x 4 x bfloat> %0,98 <vscale x 4 x bfloat> %1,99 <vscale x 4 x bfloat> %2,100 <vscale x 4 x i1> %3,101 iXLen %4, iXLen 1)102 103 ret <vscale x 4 x bfloat> %a104}105 106define <vscale x 8 x bfloat> @intrinsic_vfmin_vv_nxv8bf16_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vfmin_vv_nxv8bf16_nxv8bf16_nxv8bf16:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma110; CHECK-NEXT: vfmin.vv v8, v8, v10111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.nxv8bf16(114 <vscale x 8 x bfloat> poison,115 <vscale x 8 x bfloat> %0,116 <vscale x 8 x bfloat> %1,117 iXLen %2)118 119 ret <vscale x 8 x bfloat> %a120}121 122define <vscale x 8 x bfloat> @intrinsic_vfmin_mask_vv_nxv8bf16_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8bf16_nxv8bf16_nxv8bf16:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu126; CHECK-NEXT: vfmin.vv v8, v10, v12, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.mask.nxv8bf16.nxv8bf16(130 <vscale x 8 x bfloat> %0,131 <vscale x 8 x bfloat> %1,132 <vscale x 8 x bfloat> %2,133 <vscale x 8 x i1> %3,134 iXLen %4, iXLen 1)135 136 ret <vscale x 8 x bfloat> %a137}138 139define <vscale x 16 x bfloat> @intrinsic_vfmin_vv_nxv16bf16_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vfmin_vv_nxv16bf16_nxv16bf16_nxv16bf16:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma143; CHECK-NEXT: vfmin.vv v8, v8, v12144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.nxv16bf16(147 <vscale x 16 x bfloat> poison,148 <vscale x 16 x bfloat> %0,149 <vscale x 16 x bfloat> %1,150 iXLen %2)151 152 ret <vscale x 16 x bfloat> %a153}154 155define <vscale x 16 x bfloat> @intrinsic_vfmin_mask_vv_nxv16bf16_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16bf16_nxv16bf16_nxv16bf16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu159; CHECK-NEXT: vfmin.vv v8, v12, v16, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.mask.nxv16bf16.nxv16bf16(163 <vscale x 16 x bfloat> %0,164 <vscale x 16 x bfloat> %1,165 <vscale x 16 x bfloat> %2,166 <vscale x 16 x i1> %3,167 iXLen %4, iXLen 1)168 169 ret <vscale x 16 x bfloat> %a170}171 172define <vscale x 32 x bfloat> @intrinsic_vfmin_vv_nxv32bf16_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vfmin_vv_nxv32bf16_nxv32bf16_nxv32bf16:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma176; CHECK-NEXT: vfmin.vv v8, v8, v16177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmin.nxv32bf16.nxv32bf16(180 <vscale x 32 x bfloat> poison,181 <vscale x 32 x bfloat> %0,182 <vscale x 32 x bfloat> %1,183 iXLen %2)184 185 ret <vscale x 32 x bfloat> %a186}187 188define <vscale x 32 x bfloat> @intrinsic_vfmin_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vl8re16.v v24, (a0)192; CHECK-NEXT: vsetvli zero, a1, e16alt, m8, ta, mu193; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t194; CHECK-NEXT: ret195entry:196 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmin.mask.nxv32bf16.nxv32bf16(197 <vscale x 32 x bfloat> %0,198 <vscale x 32 x bfloat> %1,199 <vscale x 32 x bfloat> %2,200 <vscale x 32 x i1> %3,201 iXLen %4, iXLen 1)202 203 ret <vscale x 32 x bfloat> %a204}205 206define <vscale x 1 x bfloat> @intrinsic_vfmin_vf_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, bfloat %1, iXLen %2) nounwind {207; CHECK-LABEL: intrinsic_vfmin_vf_nxv1bf16_nxv1bf16_bf16:208; CHECK: # %bb.0: # %entry209; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma210; CHECK-NEXT: vfmin.vf v8, v8, fa0211; CHECK-NEXT: ret212entry:213 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.nxv1bf16.bf16(214 <vscale x 1 x bfloat> poison,215 <vscale x 1 x bfloat> %0,216 bfloat %1,217 iXLen %2)218 219 ret <vscale x 1 x bfloat> %a220}221 222define <vscale x 1 x bfloat> @intrinsic_vfmin_mask_vf_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {223; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1bf16_nxv1bf16_bf16:224; CHECK: # %bb.0: # %entry225; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu226; CHECK-NEXT: vfmin.vf v8, v9, fa0, v0.t227; CHECK-NEXT: ret228entry:229 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmin.mask.nxv1bf16.bf16(230 <vscale x 1 x bfloat> %0,231 <vscale x 1 x bfloat> %1,232 bfloat %2,233 <vscale x 1 x i1> %3,234 iXLen %4, iXLen 1)235 236 ret <vscale x 1 x bfloat> %a237}238 239define <vscale x 2 x bfloat> @intrinsic_vfmin_vf_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, bfloat %1, iXLen %2) nounwind {240; CHECK-LABEL: intrinsic_vfmin_vf_nxv2bf16_nxv2bf16_bf16:241; CHECK: # %bb.0: # %entry242; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma243; CHECK-NEXT: vfmin.vf v8, v8, fa0244; CHECK-NEXT: ret245entry:246 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.nxv2bf16.bf16(247 <vscale x 2 x bfloat> poison,248 <vscale x 2 x bfloat> %0,249 bfloat %1,250 iXLen %2)251 252 ret <vscale x 2 x bfloat> %a253}254 255define <vscale x 2 x bfloat> @intrinsic_vfmin_mask_vf_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {256; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2bf16_nxv2bf16_bf16:257; CHECK: # %bb.0: # %entry258; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu259; CHECK-NEXT: vfmin.vf v8, v9, fa0, v0.t260; CHECK-NEXT: ret261entry:262 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmin.mask.nxv2bf16.bf16(263 <vscale x 2 x bfloat> %0,264 <vscale x 2 x bfloat> %1,265 bfloat %2,266 <vscale x 2 x i1> %3,267 iXLen %4, iXLen 1)268 269 ret <vscale x 2 x bfloat> %a270}271 272define <vscale x 4 x bfloat> @intrinsic_vfmin_vf_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, bfloat %1, iXLen %2) nounwind {273; CHECK-LABEL: intrinsic_vfmin_vf_nxv4bf16_nxv4bf16_bf16:274; CHECK: # %bb.0: # %entry275; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma276; CHECK-NEXT: vfmin.vf v8, v8, fa0277; CHECK-NEXT: ret278entry:279 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.nxv4bf16.bf16(280 <vscale x 4 x bfloat> poison,281 <vscale x 4 x bfloat> %0,282 bfloat %1,283 iXLen %2)284 285 ret <vscale x 4 x bfloat> %a286}287 288define <vscale x 4 x bfloat> @intrinsic_vfmin_mask_vf_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {289; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4bf16_nxv4bf16_bf16:290; CHECK: # %bb.0: # %entry291; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu292; CHECK-NEXT: vfmin.vf v8, v9, fa0, v0.t293; CHECK-NEXT: ret294entry:295 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmin.mask.nxv4bf16.bf16(296 <vscale x 4 x bfloat> %0,297 <vscale x 4 x bfloat> %1,298 bfloat %2,299 <vscale x 4 x i1> %3,300 iXLen %4, iXLen 1)301 302 ret <vscale x 4 x bfloat> %a303}304 305define <vscale x 8 x bfloat> @intrinsic_vfmin_vf_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, bfloat %1, iXLen %2) nounwind {306; CHECK-LABEL: intrinsic_vfmin_vf_nxv8bf16_nxv8bf16_bf16:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma309; CHECK-NEXT: vfmin.vf v8, v8, fa0310; CHECK-NEXT: ret311entry:312 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.nxv8bf16.bf16(313 <vscale x 8 x bfloat> poison,314 <vscale x 8 x bfloat> %0,315 bfloat %1,316 iXLen %2)317 318 ret <vscale x 8 x bfloat> %a319}320 321define <vscale x 8 x bfloat> @intrinsic_vfmin_mask_vf_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {322; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8bf16_nxv8bf16_bf16:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu325; CHECK-NEXT: vfmin.vf v8, v10, fa0, v0.t326; CHECK-NEXT: ret327entry:328 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmin.mask.nxv8bf16.bf16(329 <vscale x 8 x bfloat> %0,330 <vscale x 8 x bfloat> %1,331 bfloat %2,332 <vscale x 8 x i1> %3,333 iXLen %4, iXLen 1)334 335 ret <vscale x 8 x bfloat> %a336}337 338define <vscale x 16 x bfloat> @intrinsic_vfmin_vf_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, bfloat %1, iXLen %2) nounwind {339; CHECK-LABEL: intrinsic_vfmin_vf_nxv16bf16_nxv16bf16_bf16:340; CHECK: # %bb.0: # %entry341; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma342; CHECK-NEXT: vfmin.vf v8, v8, fa0343; CHECK-NEXT: ret344entry:345 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.nxv16bf16.bf16(346 <vscale x 16 x bfloat> poison,347 <vscale x 16 x bfloat> %0,348 bfloat %1,349 iXLen %2)350 351 ret <vscale x 16 x bfloat> %a352}353 354define <vscale x 16 x bfloat> @intrinsic_vfmin_mask_vf_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {355; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv16bf16_nxv16bf16_bf16:356; CHECK: # %bb.0: # %entry357; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu358; CHECK-NEXT: vfmin.vf v8, v12, fa0, v0.t359; CHECK-NEXT: ret360entry:361 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmin.mask.nxv16bf16.bf16(362 <vscale x 16 x bfloat> %0,363 <vscale x 16 x bfloat> %1,364 bfloat %2,365 <vscale x 16 x i1> %3,366 iXLen %4, iXLen 1)367 368 ret <vscale x 16 x bfloat> %a369}370 371define <vscale x 32 x bfloat> @intrinsic_vfmin_vf_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, bfloat %1, iXLen %2) nounwind {372; CHECK-LABEL: intrinsic_vfmin_vf_nxv32bf16_nxv32bf16_bf16:373; CHECK: # %bb.0: # %entry374; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma375; CHECK-NEXT: vfmin.vf v8, v8, fa0376; CHECK-NEXT: ret377entry:378 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmin.nxv32bf16.bf16(379 <vscale x 32 x bfloat> poison,380 <vscale x 32 x bfloat> %0,381 bfloat %1,382 iXLen %2)383 384 ret <vscale x 32 x bfloat> %a385}386 387define <vscale x 32 x bfloat> @intrinsic_vfmin_mask_vf_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {388; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv32bf16_nxv32bf16_bf16:389; CHECK: # %bb.0: # %entry390; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, mu391; CHECK-NEXT: vfmin.vf v8, v16, fa0, v0.t392; CHECK-NEXT: ret393entry:394 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmin.mask.nxv32bf16.bf16(395 <vscale x 32 x bfloat> %0,396 <vscale x 32 x bfloat> %1,397 bfloat %2,398 <vscale x 32 x i1> %3,399 iXLen %4, iXLen 1)400 401 ret <vscale x 32 x bfloat> %a402}403 404