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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x bfloat> @intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, tu, ma12; CHECK-NEXT: vfmsac.vv v8, v9, v1013; CHECK-NEXT: fsrm a114; CHECK-NEXT: ret15entry:16 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16(17 <vscale x 1 x bfloat> %0,18 <vscale x 1 x bfloat> %1,19 <vscale x 1 x bfloat> %2,20 iXLen 0, iXLen %3, iXLen 0)21 22 ret <vscale x 1 x bfloat> %a23}24 25define <vscale x 1 x bfloat> @intrinsic_vfmsac_mask_vv_nxv1bf16_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {26; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1bf16_nxv1bf16_nxv1bf16:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: fsrmi a1, 029; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, tu, mu30; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t31; CHECK-NEXT: fsrm a132; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.mask.nxv1bf16.nxv1bf16(35 <vscale x 1 x bfloat> %0,36 <vscale x 1 x bfloat> %1,37 <vscale x 1 x bfloat> %2,38 <vscale x 1 x i1> %3,39 iXLen 0, iXLen %4, iXLen 0);40 41 ret <vscale x 1 x bfloat> %a42}43 44define <vscale x 2 x bfloat> @intrinsic_vfmsac_vv_nxv2bf16_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {45; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2bf16_nxv2bf16_nxv2bf16:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: fsrmi a1, 048; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, tu, ma49; CHECK-NEXT: vfmsac.vv v8, v9, v1050; CHECK-NEXT: fsrm a151; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16(54 <vscale x 2 x bfloat> %0,55 <vscale x 2 x bfloat> %1,56 <vscale x 2 x bfloat> %2,57 iXLen 0, iXLen %3, iXLen 0)58 59 ret <vscale x 2 x bfloat> %a60}61 62define <vscale x 2 x bfloat> @intrinsic_vfmsac_mask_vv_nxv2bf16_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {63; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2bf16_nxv2bf16_nxv2bf16:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: fsrmi a1, 066; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, tu, mu67; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t68; CHECK-NEXT: fsrm a169; CHECK-NEXT: ret70entry:71 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.mask.nxv2bf16.nxv2bf16(72 <vscale x 2 x bfloat> %0,73 <vscale x 2 x bfloat> %1,74 <vscale x 2 x bfloat> %2,75 <vscale x 2 x i1> %3,76 iXLen 0, iXLen %4, iXLen 0);77 78 ret <vscale x 2 x bfloat> %a79}80 81define <vscale x 4 x bfloat> @intrinsic_vfmsac_vv_nxv4bf16_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, iXLen %3) nounwind {82; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4bf16_nxv4bf16_nxv4bf16:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: fsrmi a1, 085; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, tu, ma86; CHECK-NEXT: vfmsac.vv v8, v9, v1087; CHECK-NEXT: fsrm a188; CHECK-NEXT: ret89entry:90 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16(91 <vscale x 4 x bfloat> %0,92 <vscale x 4 x bfloat> %1,93 <vscale x 4 x bfloat> %2,94 iXLen 0, iXLen %3, iXLen 0)95 96 ret <vscale x 4 x bfloat> %a97}98 99define <vscale x 4 x bfloat> @intrinsic_vfmsac_mask_vv_nxv4bf16_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {100; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4bf16_nxv4bf16_nxv4bf16:101; CHECK: # %bb.0: # %entry102; CHECK-NEXT: fsrmi a1, 0103; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, tu, mu104; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t105; CHECK-NEXT: fsrm a1106; CHECK-NEXT: ret107entry:108 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.mask.nxv4bf16.nxv4bf16(109 <vscale x 4 x bfloat> %0,110 <vscale x 4 x bfloat> %1,111 <vscale x 4 x bfloat> %2,112 <vscale x 4 x i1> %3,113 iXLen 0, iXLen %4, iXLen 0);114 115 ret <vscale x 4 x bfloat> %a116}117 118define <vscale x 8 x bfloat> @intrinsic_vfmsac_vv_nxv8bf16_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {119; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8bf16_nxv8bf16_nxv8bf16:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: fsrmi a1, 0122; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, tu, ma123; CHECK-NEXT: vfmsac.vv v8, v10, v12124; CHECK-NEXT: fsrm a1125; CHECK-NEXT: ret126entry:127 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16(128 <vscale x 8 x bfloat> %0,129 <vscale x 8 x bfloat> %1,130 <vscale x 8 x bfloat> %2,131 iXLen 0, iXLen %3, iXLen 0)132 133 ret <vscale x 8 x bfloat> %a134}135 136define <vscale x 8 x bfloat> @intrinsic_vfmsac_mask_vv_nxv8bf16_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {137; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8bf16_nxv8bf16_nxv8bf16:138; CHECK: # %bb.0: # %entry139; CHECK-NEXT: fsrmi a1, 0140; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, tu, mu141; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t142; CHECK-NEXT: fsrm a1143; CHECK-NEXT: ret144entry:145 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.mask.nxv8bf16.nxv8bf16(146 <vscale x 8 x bfloat> %0,147 <vscale x 8 x bfloat> %1,148 <vscale x 8 x bfloat> %2,149 <vscale x 8 x i1> %3,150 iXLen 0, iXLen %4, iXLen 0);151 152 ret <vscale x 8 x bfloat> %a153}154 155define <vscale x 16 x bfloat> @intrinsic_vfmsac_vv_nxv16bf16_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {156; CHECK-LABEL: intrinsic_vfmsac_vv_nxv16bf16_nxv16bf16_nxv16bf16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: fsrmi a1, 0159; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, tu, ma160; CHECK-NEXT: vfmsac.vv v8, v12, v16161; CHECK-NEXT: fsrm a1162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmsac.nxv16bf16.nxv16bf16(165 <vscale x 16 x bfloat> %0,166 <vscale x 16 x bfloat> %1,167 <vscale x 16 x bfloat> %2,168 iXLen 0, iXLen %3, iXLen 0)169 170 ret <vscale x 16 x bfloat> %a171}172 173define <vscale x 16 x bfloat> @intrinsic_vfmsac_mask_vv_nxv16bf16_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {174; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16bf16_nxv16bf16_nxv16bf16:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: fsrmi a1, 0177; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, tu, mu178; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t179; CHECK-NEXT: fsrm a1180; CHECK-NEXT: ret181entry:182 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmsac.mask.nxv16bf16.nxv16bf16(183 <vscale x 16 x bfloat> %0,184 <vscale x 16 x bfloat> %1,185 <vscale x 16 x bfloat> %2,186 <vscale x 16 x i1> %3,187 iXLen 0, iXLen %4, iXLen 0);188 189 ret <vscale x 16 x bfloat> %a190}191 192define <vscale x 1 x bfloat> @intrinsic_vfmsac_vf_nxv1bf16_bf16_nxv1bf16(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {193; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1bf16_bf16_nxv1bf16:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: fsrmi a1, 0196; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, tu, ma197; CHECK-NEXT: vfmsac.vf v8, fa0, v9198; CHECK-NEXT: fsrm a1199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16(202 <vscale x 1 x bfloat> %0,203 bfloat %1,204 <vscale x 1 x bfloat> %2,205 iXLen 0, iXLen %3, iXLen 0)206 207 ret <vscale x 1 x bfloat> %a208}209 210define <vscale x 1 x bfloat> @intrinsic_vfmsac_mask_vf_nxv1bf16_bf16_nxv1bf16(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {211; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1bf16_bf16_nxv1bf16:212; CHECK: # %bb.0: # %entry213; CHECK-NEXT: fsrmi a1, 0214; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, tu, mu215; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t216; CHECK-NEXT: fsrm a1217; CHECK-NEXT: ret218entry:219 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.mask.nxv1bf16.bf16(220 <vscale x 1 x bfloat> %0,221 bfloat %1,222 <vscale x 1 x bfloat> %2,223 <vscale x 1 x i1> %3,224 iXLen 0, iXLen %4, iXLen 0);225 226 ret <vscale x 1 x bfloat> %a227}228 229define <vscale x 2 x bfloat> @intrinsic_vfmsac_vf_nxv2bf16_bf16_nxv2bf16(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {230; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2bf16_bf16_nxv2bf16:231; CHECK: # %bb.0: # %entry232; CHECK-NEXT: fsrmi a1, 0233; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, tu, ma234; CHECK-NEXT: vfmsac.vf v8, fa0, v9235; CHECK-NEXT: fsrm a1236; CHECK-NEXT: ret237entry:238 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.nxv2bf16.bf16(239 <vscale x 2 x bfloat> %0,240 bfloat %1,241 <vscale x 2 x bfloat> %2,242 iXLen 0, iXLen %3, iXLen 0)243 244 ret <vscale x 2 x bfloat> %a245}246 247define <vscale x 2 x bfloat> @intrinsic_vfmsac_mask_vf_nxv2bf16_bf16_nxv2bf16(<vscale x 2 x bfloat> %0, bfloat %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {248; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2bf16_bf16_nxv2bf16:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: fsrmi a1, 0251; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, tu, mu252; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t253; CHECK-NEXT: fsrm a1254; CHECK-NEXT: ret255entry:256 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmsac.mask.nxv2bf16.bf16(257 <vscale x 2 x bfloat> %0,258 bfloat %1,259 <vscale x 2 x bfloat> %2,260 <vscale x 2 x i1> %3,261 iXLen 0, iXLen %4, iXLen 0);262 263 ret <vscale x 2 x bfloat> %a264}265 266define <vscale x 4 x bfloat> @intrinsic_vfmsac_vf_nxv4bf16_bf16_nxv4bf16(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, iXLen %3) nounwind {267; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4bf16_bf16_nxv4bf16:268; CHECK: # %bb.0: # %entry269; CHECK-NEXT: fsrmi a1, 0270; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, tu, ma271; CHECK-NEXT: vfmsac.vf v8, fa0, v9272; CHECK-NEXT: fsrm a1273; CHECK-NEXT: ret274entry:275 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.nxv4bf16.bf16(276 <vscale x 4 x bfloat> %0,277 bfloat %1,278 <vscale x 4 x bfloat> %2,279 iXLen 0, iXLen %3, iXLen 0)280 281 ret <vscale x 4 x bfloat> %a282}283 284define <vscale x 4 x bfloat> @intrinsic_vfmsac_mask_vf_nxv4bf16_bf16_nxv4bf16(<vscale x 4 x bfloat> %0, bfloat %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {285; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4bf16_bf16_nxv4bf16:286; CHECK: # %bb.0: # %entry287; CHECK-NEXT: fsrmi a1, 0288; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, tu, mu289; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t290; CHECK-NEXT: fsrm a1291; CHECK-NEXT: ret292entry:293 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmsac.mask.nxv4bf16.bf16(294 <vscale x 4 x bfloat> %0,295 bfloat %1,296 <vscale x 4 x bfloat> %2,297 <vscale x 4 x i1> %3,298 iXLen 0, iXLen %4, iXLen 0);299 300 ret <vscale x 4 x bfloat> %a301}302 303define <vscale x 8 x bfloat> @intrinsic_vfmsac_vf_nxv8bf16_bf16_nxv8bf16(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {304; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8bf16_bf16_nxv8bf16:305; CHECK: # %bb.0: # %entry306; CHECK-NEXT: fsrmi a1, 0307; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, tu, ma308; CHECK-NEXT: vfmsac.vf v8, fa0, v10309; CHECK-NEXT: fsrm a1310; CHECK-NEXT: ret311entry:312 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.nxv8bf16.bf16(313 <vscale x 8 x bfloat> %0,314 bfloat %1,315 <vscale x 8 x bfloat> %2,316 iXLen 0, iXLen %3, iXLen 0)317 318 ret <vscale x 8 x bfloat> %a319}320 321define <vscale x 8 x bfloat> @intrinsic_vfmsac_mask_vf_nxv8bf16_bf16_nxv8bf16(<vscale x 8 x bfloat> %0, bfloat %1, <vscale x 8 x bfloat> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {322; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8bf16_bf16_nxv8bf16:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: fsrmi a1, 0325; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, tu, mu326; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t327; CHECK-NEXT: fsrm a1328; CHECK-NEXT: ret329entry:330 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmsac.mask.nxv8bf16.bf16(331 <vscale x 8 x bfloat> %0,332 bfloat %1,333 <vscale x 8 x bfloat> %2,334 <vscale x 8 x i1> %3,335 iXLen 0, iXLen %4, iXLen 0);336 337 ret <vscale x 8 x bfloat> %a338}339 340define <vscale x 16 x bfloat> @intrinsic_vfmsac_vf_nxv16bf16_bf16_nxv16bf16(<vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {341; CHECK-LABEL: intrinsic_vfmsac_vf_nxv16bf16_bf16_nxv16bf16:342; CHECK: # %bb.0: # %entry343; CHECK-NEXT: fsrmi a1, 0344; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, tu, ma345; CHECK-NEXT: vfmsac.vf v8, fa0, v12346; CHECK-NEXT: fsrm a1347; CHECK-NEXT: ret348entry:349 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmsac.nxv16bf16.bf16(350 <vscale x 16 x bfloat> %0,351 bfloat %1,352 <vscale x 16 x bfloat> %2,353 iXLen 0, iXLen %3, iXLen 0)354 355 ret <vscale x 16 x bfloat> %a356}357 358define <vscale x 16 x bfloat> @intrinsic_vfmsac_mask_vf_nxv16bf16_bf16_nxv16bf16(<vscale x 16 x bfloat> %0, bfloat %1, <vscale x 16 x bfloat> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {359; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv16bf16_bf16_nxv16bf16:360; CHECK: # %bb.0: # %entry361; CHECK-NEXT: fsrmi a1, 0362; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, tu, mu363; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t364; CHECK-NEXT: fsrm a1365; CHECK-NEXT: ret366entry:367 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmsac.mask.nxv16bf16.bf16(368 <vscale x 16 x bfloat> %0,369 bfloat %1,370 <vscale x 16 x bfloat> %2,371 <vscale x 16 x i1> %3,372 iXLen 0, iXLen %4, iXLen 0);373 374 ret <vscale x 16 x bfloat> %a375}376 377define <vscale x 1 x bfloat> @intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16_commute(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {378; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16_commute:379; CHECK: # %bb.0: # %entry380; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma381; CHECK-NEXT: vfmsub.vv v8, v10, v9382; CHECK-NEXT: ret383entry:384 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16(385 <vscale x 1 x bfloat> %1,386 <vscale x 1 x bfloat> %0,387 <vscale x 1 x bfloat> %2,388 iXLen 7, iXLen %3, iXLen 3)389 390 ret <vscale x 1 x bfloat> %a391}392 393define <vscale x 1 x bfloat> @intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16_commute2(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {394; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1bf16_nxv1bf16_nxv1bf16_commute2:395; CHECK: # %bb.0: # %entry396; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma397; CHECK-NEXT: vfmsub.vv v8, v10, v9398; CHECK-NEXT: ret399entry:400 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16(401 <vscale x 1 x bfloat> %1,402 <vscale x 1 x bfloat> %2,403 <vscale x 1 x bfloat> %0,404 iXLen 7, iXLen %3, iXLen 3)405 406 ret <vscale x 1 x bfloat> %a407}408 409define <vscale x 1 x bfloat> @intrinsic_vfmsac_vf_nxv1bf16_bf16_nxv1bf16_commute(<vscale x 1 x bfloat> %0, bfloat %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {410; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1bf16_bf16_nxv1bf16_commute:411; CHECK: # %bb.0: # %entry412; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma413; CHECK-NEXT: vfmsub.vf v8, fa0, v9414; CHECK-NEXT: ret415entry:416 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmsac.nxv1bf16.bf16(417 <vscale x 1 x bfloat> %2,418 bfloat %1,419 <vscale x 1 x bfloat> %0,420 iXLen 7, iXLen %3, iXLen 3)421 422 ret <vscale x 1 x bfloat> %a423}424