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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x half> @intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma12; CHECK-NEXT: vfmsac.vv v8, v9, v1013; CHECK-NEXT: fsrm a114; CHECK-NEXT: ret15entry:16 %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16(17 <vscale x 1 x half> %0,18 <vscale x 1 x half> %1,19 <vscale x 1 x half> %2,20 iXLen 0, iXLen %3, iXLen 0)21 22 ret <vscale x 1 x half> %a23}24 25define <vscale x 1 x half> @intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {26; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: fsrmi a1, 029; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu30; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t31; CHECK-NEXT: fsrm a132; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16(35 <vscale x 1 x half> %0,36 <vscale x 1 x half> %1,37 <vscale x 1 x half> %2,38 <vscale x 1 x i1> %3,39 iXLen 0, iXLen %4, iXLen 0);40 41 ret <vscale x 1 x half> %a42}43 44define <vscale x 2 x half> @intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind {45; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: fsrmi a1, 048; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma49; CHECK-NEXT: vfmsac.vv v8, v9, v1050; CHECK-NEXT: fsrm a151; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16(54 <vscale x 2 x half> %0,55 <vscale x 2 x half> %1,56 <vscale x 2 x half> %2,57 iXLen 0, iXLen %3, iXLen 0)58 59 ret <vscale x 2 x half> %a60}61 62define <vscale x 2 x half> @intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {63; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: fsrmi a1, 066; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu67; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t68; CHECK-NEXT: fsrm a169; CHECK-NEXT: ret70entry:71 %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16(72 <vscale x 2 x half> %0,73 <vscale x 2 x half> %1,74 <vscale x 2 x half> %2,75 <vscale x 2 x i1> %3,76 iXLen 0, iXLen %4, iXLen 0);77 78 ret <vscale x 2 x half> %a79}80 81define <vscale x 4 x half> @intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {82; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: fsrmi a1, 085; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma86; CHECK-NEXT: vfmsac.vv v8, v9, v1087; CHECK-NEXT: fsrm a188; CHECK-NEXT: ret89entry:90 %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16(91 <vscale x 4 x half> %0,92 <vscale x 4 x half> %1,93 <vscale x 4 x half> %2,94 iXLen 0, iXLen %3, iXLen 0)95 96 ret <vscale x 4 x half> %a97}98 99define <vscale x 4 x half> @intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {100; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16:101; CHECK: # %bb.0: # %entry102; CHECK-NEXT: fsrmi a1, 0103; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu104; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t105; CHECK-NEXT: fsrm a1106; CHECK-NEXT: ret107entry:108 %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16(109 <vscale x 4 x half> %0,110 <vscale x 4 x half> %1,111 <vscale x 4 x half> %2,112 <vscale x 4 x i1> %3,113 iXLen 0, iXLen %4, iXLen 0);114 115 ret <vscale x 4 x half> %a116}117 118define <vscale x 8 x half> @intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind {119; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: fsrmi a1, 0122; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma123; CHECK-NEXT: vfmsac.vv v8, v10, v12124; CHECK-NEXT: fsrm a1125; CHECK-NEXT: ret126entry:127 %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16(128 <vscale x 8 x half> %0,129 <vscale x 8 x half> %1,130 <vscale x 8 x half> %2,131 iXLen 0, iXLen %3, iXLen 0)132 133 ret <vscale x 8 x half> %a134}135 136define <vscale x 8 x half> @intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {137; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16:138; CHECK: # %bb.0: # %entry139; CHECK-NEXT: fsrmi a1, 0140; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu141; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t142; CHECK-NEXT: fsrm a1143; CHECK-NEXT: ret144entry:145 %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16(146 <vscale x 8 x half> %0,147 <vscale x 8 x half> %1,148 <vscale x 8 x half> %2,149 <vscale x 8 x i1> %3,150 iXLen 0, iXLen %4, iXLen 0);151 152 ret <vscale x 8 x half> %a153}154 155define <vscale x 16 x half> @intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {156; CHECK-LABEL: intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: fsrmi a1, 0159; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma160; CHECK-NEXT: vfmsac.vv v8, v12, v16161; CHECK-NEXT: fsrm a1162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16(165 <vscale x 16 x half> %0,166 <vscale x 16 x half> %1,167 <vscale x 16 x half> %2,168 iXLen 0, iXLen %3, iXLen 0)169 170 ret <vscale x 16 x half> %a171}172 173define <vscale x 16 x half> @intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {174; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: fsrmi a1, 0177; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu178; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t179; CHECK-NEXT: fsrm a1180; CHECK-NEXT: ret181entry:182 %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16(183 <vscale x 16 x half> %0,184 <vscale x 16 x half> %1,185 <vscale x 16 x half> %2,186 <vscale x 16 x i1> %3,187 iXLen 0, iXLen %4, iXLen 0);188 189 ret <vscale x 16 x half> %a190}191 192define <vscale x 1 x float> @intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {193; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: fsrmi a1, 0196; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma197; CHECK-NEXT: vfmsac.vv v8, v9, v10198; CHECK-NEXT: fsrm a1199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32(202 <vscale x 1 x float> %0,203 <vscale x 1 x float> %1,204 <vscale x 1 x float> %2,205 iXLen 0, iXLen %3, iXLen 0)206 207 ret <vscale x 1 x float> %a208}209 210define <vscale x 1 x float> @intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {211; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32:212; CHECK: # %bb.0: # %entry213; CHECK-NEXT: fsrmi a1, 0214; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu215; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t216; CHECK-NEXT: fsrm a1217; CHECK-NEXT: ret218entry:219 %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32(220 <vscale x 1 x float> %0,221 <vscale x 1 x float> %1,222 <vscale x 1 x float> %2,223 <vscale x 1 x i1> %3,224 iXLen 0, iXLen %4, iXLen 0);225 226 ret <vscale x 1 x float> %a227}228 229define <vscale x 2 x float> @intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {230; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32:231; CHECK: # %bb.0: # %entry232; CHECK-NEXT: fsrmi a1, 0233; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma234; CHECK-NEXT: vfmsac.vv v8, v9, v10235; CHECK-NEXT: fsrm a1236; CHECK-NEXT: ret237entry:238 %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32(239 <vscale x 2 x float> %0,240 <vscale x 2 x float> %1,241 <vscale x 2 x float> %2,242 iXLen 0, iXLen %3, iXLen 0)243 244 ret <vscale x 2 x float> %a245}246 247define <vscale x 2 x float> @intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {248; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: fsrmi a1, 0251; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu252; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t253; CHECK-NEXT: fsrm a1254; CHECK-NEXT: ret255entry:256 %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32(257 <vscale x 2 x float> %0,258 <vscale x 2 x float> %1,259 <vscale x 2 x float> %2,260 <vscale x 2 x i1> %3,261 iXLen 0, iXLen %4, iXLen 0);262 263 ret <vscale x 2 x float> %a264}265 266define <vscale x 4 x float> @intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind {267; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32:268; CHECK: # %bb.0: # %entry269; CHECK-NEXT: fsrmi a1, 0270; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma271; CHECK-NEXT: vfmsac.vv v8, v10, v12272; CHECK-NEXT: fsrm a1273; CHECK-NEXT: ret274entry:275 %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32(276 <vscale x 4 x float> %0,277 <vscale x 4 x float> %1,278 <vscale x 4 x float> %2,279 iXLen 0, iXLen %3, iXLen 0)280 281 ret <vscale x 4 x float> %a282}283 284define <vscale x 4 x float> @intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {285; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32:286; CHECK: # %bb.0: # %entry287; CHECK-NEXT: fsrmi a1, 0288; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu289; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t290; CHECK-NEXT: fsrm a1291; CHECK-NEXT: ret292entry:293 %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32(294 <vscale x 4 x float> %0,295 <vscale x 4 x float> %1,296 <vscale x 4 x float> %2,297 <vscale x 4 x i1> %3,298 iXLen 0, iXLen %4, iXLen 0);299 300 ret <vscale x 4 x float> %a301}302 303define <vscale x 8 x float> @intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind {304; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32:305; CHECK: # %bb.0: # %entry306; CHECK-NEXT: fsrmi a1, 0307; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma308; CHECK-NEXT: vfmsac.vv v8, v12, v16309; CHECK-NEXT: fsrm a1310; CHECK-NEXT: ret311entry:312 %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32(313 <vscale x 8 x float> %0,314 <vscale x 8 x float> %1,315 <vscale x 8 x float> %2,316 iXLen 0, iXLen %3, iXLen 0)317 318 ret <vscale x 8 x float> %a319}320 321define <vscale x 8 x float> @intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {322; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: fsrmi a1, 0325; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu326; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t327; CHECK-NEXT: fsrm a1328; CHECK-NEXT: ret329entry:330 %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32(331 <vscale x 8 x float> %0,332 <vscale x 8 x float> %1,333 <vscale x 8 x float> %2,334 <vscale x 8 x i1> %3,335 iXLen 0, iXLen %4, iXLen 0);336 337 ret <vscale x 8 x float> %a338}339 340define <vscale x 1 x double> @intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {341; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64:342; CHECK: # %bb.0: # %entry343; CHECK-NEXT: fsrmi a1, 0344; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma345; CHECK-NEXT: vfmsac.vv v8, v9, v10346; CHECK-NEXT: fsrm a1347; CHECK-NEXT: ret348entry:349 %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64(350 <vscale x 1 x double> %0,351 <vscale x 1 x double> %1,352 <vscale x 1 x double> %2,353 iXLen 0, iXLen %3, iXLen 0)354 355 ret <vscale x 1 x double> %a356}357 358define <vscale x 1 x double> @intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {359; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64:360; CHECK: # %bb.0: # %entry361; CHECK-NEXT: fsrmi a1, 0362; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu363; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t364; CHECK-NEXT: fsrm a1365; CHECK-NEXT: ret366entry:367 %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64(368 <vscale x 1 x double> %0,369 <vscale x 1 x double> %1,370 <vscale x 1 x double> %2,371 <vscale x 1 x i1> %3,372 iXLen 0, iXLen %4, iXLen 0);373 374 ret <vscale x 1 x double> %a375}376 377define <vscale x 2 x double> @intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind {378; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64:379; CHECK: # %bb.0: # %entry380; CHECK-NEXT: fsrmi a1, 0381; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma382; CHECK-NEXT: vfmsac.vv v8, v10, v12383; CHECK-NEXT: fsrm a1384; CHECK-NEXT: ret385entry:386 %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64(387 <vscale x 2 x double> %0,388 <vscale x 2 x double> %1,389 <vscale x 2 x double> %2,390 iXLen 0, iXLen %3, iXLen 0)391 392 ret <vscale x 2 x double> %a393}394 395define <vscale x 2 x double> @intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {396; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64:397; CHECK: # %bb.0: # %entry398; CHECK-NEXT: fsrmi a1, 0399; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu400; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t401; CHECK-NEXT: fsrm a1402; CHECK-NEXT: ret403entry:404 %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64(405 <vscale x 2 x double> %0,406 <vscale x 2 x double> %1,407 <vscale x 2 x double> %2,408 <vscale x 2 x i1> %3,409 iXLen 0, iXLen %4, iXLen 0);410 411 ret <vscale x 2 x double> %a412}413 414define <vscale x 4 x double> @intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind {415; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64:416; CHECK: # %bb.0: # %entry417; CHECK-NEXT: fsrmi a1, 0418; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma419; CHECK-NEXT: vfmsac.vv v8, v12, v16420; CHECK-NEXT: fsrm a1421; CHECK-NEXT: ret422entry:423 %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64(424 <vscale x 4 x double> %0,425 <vscale x 4 x double> %1,426 <vscale x 4 x double> %2,427 iXLen 0, iXLen %3, iXLen 0)428 429 ret <vscale x 4 x double> %a430}431 432define <vscale x 4 x double> @intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {433; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64:434; CHECK: # %bb.0: # %entry435; CHECK-NEXT: fsrmi a1, 0436; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu437; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t438; CHECK-NEXT: fsrm a1439; CHECK-NEXT: ret440entry:441 %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64(442 <vscale x 4 x double> %0,443 <vscale x 4 x double> %1,444 <vscale x 4 x double> %2,445 <vscale x 4 x i1> %3,446 iXLen 0, iXLen %4, iXLen 0);447 448 ret <vscale x 4 x double> %a449}450 451define <vscale x 1 x half> @intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind {452; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16:453; CHECK: # %bb.0: # %entry454; CHECK-NEXT: fsrmi a1, 0455; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma456; CHECK-NEXT: vfmsac.vf v8, fa0, v9457; CHECK-NEXT: fsrm a1458; CHECK-NEXT: ret459entry:460 %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16(461 <vscale x 1 x half> %0,462 half %1,463 <vscale x 1 x half> %2,464 iXLen 0, iXLen %3, iXLen 0)465 466 ret <vscale x 1 x half> %a467}468 469define <vscale x 1 x half> @intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {470; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: fsrmi a1, 0473; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu474; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t475; CHECK-NEXT: fsrm a1476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16(479 <vscale x 1 x half> %0,480 half %1,481 <vscale x 1 x half> %2,482 <vscale x 1 x i1> %3,483 iXLen 0, iXLen %4, iXLen 0);484 485 ret <vscale x 1 x half> %a486}487 488define <vscale x 2 x half> @intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind {489; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16:490; CHECK: # %bb.0: # %entry491; CHECK-NEXT: fsrmi a1, 0492; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma493; CHECK-NEXT: vfmsac.vf v8, fa0, v9494; CHECK-NEXT: fsrm a1495; CHECK-NEXT: ret496entry:497 %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16(498 <vscale x 2 x half> %0,499 half %1,500 <vscale x 2 x half> %2,501 iXLen 0, iXLen %3, iXLen 0)502 503 ret <vscale x 2 x half> %a504}505 506define <vscale x 2 x half> @intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {507; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16:508; CHECK: # %bb.0: # %entry509; CHECK-NEXT: fsrmi a1, 0510; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu511; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t512; CHECK-NEXT: fsrm a1513; CHECK-NEXT: ret514entry:515 %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16(516 <vscale x 2 x half> %0,517 half %1,518 <vscale x 2 x half> %2,519 <vscale x 2 x i1> %3,520 iXLen 0, iXLen %4, iXLen 0);521 522 ret <vscale x 2 x half> %a523}524 525define <vscale x 4 x half> @intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind {526; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16:527; CHECK: # %bb.0: # %entry528; CHECK-NEXT: fsrmi a1, 0529; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma530; CHECK-NEXT: vfmsac.vf v8, fa0, v9531; CHECK-NEXT: fsrm a1532; CHECK-NEXT: ret533entry:534 %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16(535 <vscale x 4 x half> %0,536 half %1,537 <vscale x 4 x half> %2,538 iXLen 0, iXLen %3, iXLen 0)539 540 ret <vscale x 4 x half> %a541}542 543define <vscale x 4 x half> @intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {544; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16:545; CHECK: # %bb.0: # %entry546; CHECK-NEXT: fsrmi a1, 0547; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu548; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t549; CHECK-NEXT: fsrm a1550; CHECK-NEXT: ret551entry:552 %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16(553 <vscale x 4 x half> %0,554 half %1,555 <vscale x 4 x half> %2,556 <vscale x 4 x i1> %3,557 iXLen 0, iXLen %4, iXLen 0);558 559 ret <vscale x 4 x half> %a560}561 562define <vscale x 8 x half> @intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind {563; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16:564; CHECK: # %bb.0: # %entry565; CHECK-NEXT: fsrmi a1, 0566; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma567; CHECK-NEXT: vfmsac.vf v8, fa0, v10568; CHECK-NEXT: fsrm a1569; CHECK-NEXT: ret570entry:571 %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16(572 <vscale x 8 x half> %0,573 half %1,574 <vscale x 8 x half> %2,575 iXLen 0, iXLen %3, iXLen 0)576 577 ret <vscale x 8 x half> %a578}579 580define <vscale x 8 x half> @intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {581; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16:582; CHECK: # %bb.0: # %entry583; CHECK-NEXT: fsrmi a1, 0584; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu585; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t586; CHECK-NEXT: fsrm a1587; CHECK-NEXT: ret588entry:589 %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16(590 <vscale x 8 x half> %0,591 half %1,592 <vscale x 8 x half> %2,593 <vscale x 8 x i1> %3,594 iXLen 0, iXLen %4, iXLen 0);595 596 ret <vscale x 8 x half> %a597}598 599define <vscale x 16 x half> @intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind {600; CHECK-LABEL: intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16:601; CHECK: # %bb.0: # %entry602; CHECK-NEXT: fsrmi a1, 0603; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma604; CHECK-NEXT: vfmsac.vf v8, fa0, v12605; CHECK-NEXT: fsrm a1606; CHECK-NEXT: ret607entry:608 %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16(609 <vscale x 16 x half> %0,610 half %1,611 <vscale x 16 x half> %2,612 iXLen 0, iXLen %3, iXLen 0)613 614 ret <vscale x 16 x half> %a615}616 617define <vscale x 16 x half> @intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {618; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16:619; CHECK: # %bb.0: # %entry620; CHECK-NEXT: fsrmi a1, 0621; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu622; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t623; CHECK-NEXT: fsrm a1624; CHECK-NEXT: ret625entry:626 %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16(627 <vscale x 16 x half> %0,628 half %1,629 <vscale x 16 x half> %2,630 <vscale x 16 x i1> %3,631 iXLen 0, iXLen %4, iXLen 0);632 633 ret <vscale x 16 x half> %a634}635 636define <vscale x 1 x float> @intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind {637; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32:638; CHECK: # %bb.0: # %entry639; CHECK-NEXT: fsrmi a1, 0640; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma641; CHECK-NEXT: vfmsac.vf v8, fa0, v9642; CHECK-NEXT: fsrm a1643; CHECK-NEXT: ret644entry:645 %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32(646 <vscale x 1 x float> %0,647 float %1,648 <vscale x 1 x float> %2,649 iXLen 0, iXLen %3, iXLen 0)650 651 ret <vscale x 1 x float> %a652}653 654define <vscale x 1 x float> @intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {655; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32:656; CHECK: # %bb.0: # %entry657; CHECK-NEXT: fsrmi a1, 0658; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu659; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t660; CHECK-NEXT: fsrm a1661; CHECK-NEXT: ret662entry:663 %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32(664 <vscale x 1 x float> %0,665 float %1,666 <vscale x 1 x float> %2,667 <vscale x 1 x i1> %3,668 iXLen 0, iXLen %4, iXLen 0);669 670 ret <vscale x 1 x float> %a671}672 673define <vscale x 2 x float> @intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind {674; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32:675; CHECK: # %bb.0: # %entry676; CHECK-NEXT: fsrmi a1, 0677; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma678; CHECK-NEXT: vfmsac.vf v8, fa0, v9679; CHECK-NEXT: fsrm a1680; CHECK-NEXT: ret681entry:682 %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32(683 <vscale x 2 x float> %0,684 float %1,685 <vscale x 2 x float> %2,686 iXLen 0, iXLen %3, iXLen 0)687 688 ret <vscale x 2 x float> %a689}690 691define <vscale x 2 x float> @intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {692; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32:693; CHECK: # %bb.0: # %entry694; CHECK-NEXT: fsrmi a1, 0695; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu696; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t697; CHECK-NEXT: fsrm a1698; CHECK-NEXT: ret699entry:700 %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32(701 <vscale x 2 x float> %0,702 float %1,703 <vscale x 2 x float> %2,704 <vscale x 2 x i1> %3,705 iXLen 0, iXLen %4, iXLen 0);706 707 ret <vscale x 2 x float> %a708}709 710define <vscale x 4 x float> @intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind {711; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32:712; CHECK: # %bb.0: # %entry713; CHECK-NEXT: fsrmi a1, 0714; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma715; CHECK-NEXT: vfmsac.vf v8, fa0, v10716; CHECK-NEXT: fsrm a1717; CHECK-NEXT: ret718entry:719 %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32(720 <vscale x 4 x float> %0,721 float %1,722 <vscale x 4 x float> %2,723 iXLen 0, iXLen %3, iXLen 0)724 725 ret <vscale x 4 x float> %a726}727 728define <vscale x 4 x float> @intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {729; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32:730; CHECK: # %bb.0: # %entry731; CHECK-NEXT: fsrmi a1, 0732; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu733; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t734; CHECK-NEXT: fsrm a1735; CHECK-NEXT: ret736entry:737 %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32(738 <vscale x 4 x float> %0,739 float %1,740 <vscale x 4 x float> %2,741 <vscale x 4 x i1> %3,742 iXLen 0, iXLen %4, iXLen 0);743 744 ret <vscale x 4 x float> %a745}746 747define <vscale x 8 x float> @intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind {748; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32:749; CHECK: # %bb.0: # %entry750; CHECK-NEXT: fsrmi a1, 0751; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma752; CHECK-NEXT: vfmsac.vf v8, fa0, v12753; CHECK-NEXT: fsrm a1754; CHECK-NEXT: ret755entry:756 %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32(757 <vscale x 8 x float> %0,758 float %1,759 <vscale x 8 x float> %2,760 iXLen 0, iXLen %3, iXLen 0)761 762 ret <vscale x 8 x float> %a763}764 765define <vscale x 8 x float> @intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {766; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32:767; CHECK: # %bb.0: # %entry768; CHECK-NEXT: fsrmi a1, 0769; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu770; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t771; CHECK-NEXT: fsrm a1772; CHECK-NEXT: ret773entry:774 %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32(775 <vscale x 8 x float> %0,776 float %1,777 <vscale x 8 x float> %2,778 <vscale x 8 x i1> %3,779 iXLen 0, iXLen %4, iXLen 0);780 781 ret <vscale x 8 x float> %a782}783 784define <vscale x 1 x double> @intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind {785; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64:786; CHECK: # %bb.0: # %entry787; CHECK-NEXT: fsrmi a1, 0788; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma789; CHECK-NEXT: vfmsac.vf v8, fa0, v9790; CHECK-NEXT: fsrm a1791; CHECK-NEXT: ret792entry:793 %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64(794 <vscale x 1 x double> %0,795 double %1,796 <vscale x 1 x double> %2,797 iXLen 0, iXLen %3, iXLen 0)798 799 ret <vscale x 1 x double> %a800}801 802define <vscale x 1 x double> @intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {803; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64:804; CHECK: # %bb.0: # %entry805; CHECK-NEXT: fsrmi a1, 0806; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu807; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t808; CHECK-NEXT: fsrm a1809; CHECK-NEXT: ret810entry:811 %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64(812 <vscale x 1 x double> %0,813 double %1,814 <vscale x 1 x double> %2,815 <vscale x 1 x i1> %3,816 iXLen 0, iXLen %4, iXLen 0);817 818 ret <vscale x 1 x double> %a819}820 821define <vscale x 2 x double> @intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind {822; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64:823; CHECK: # %bb.0: # %entry824; CHECK-NEXT: fsrmi a1, 0825; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma826; CHECK-NEXT: vfmsac.vf v8, fa0, v10827; CHECK-NEXT: fsrm a1828; CHECK-NEXT: ret829entry:830 %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64(831 <vscale x 2 x double> %0,832 double %1,833 <vscale x 2 x double> %2,834 iXLen 0, iXLen %3, iXLen 0)835 836 ret <vscale x 2 x double> %a837}838 839define <vscale x 2 x double> @intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {840; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64:841; CHECK: # %bb.0: # %entry842; CHECK-NEXT: fsrmi a1, 0843; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu844; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t845; CHECK-NEXT: fsrm a1846; CHECK-NEXT: ret847entry:848 %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64(849 <vscale x 2 x double> %0,850 double %1,851 <vscale x 2 x double> %2,852 <vscale x 2 x i1> %3,853 iXLen 0, iXLen %4, iXLen 0);854 855 ret <vscale x 2 x double> %a856}857 858define <vscale x 4 x double> @intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind {859; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64:860; CHECK: # %bb.0: # %entry861; CHECK-NEXT: fsrmi a1, 0862; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma863; CHECK-NEXT: vfmsac.vf v8, fa0, v12864; CHECK-NEXT: fsrm a1865; CHECK-NEXT: ret866entry:867 %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64(868 <vscale x 4 x double> %0,869 double %1,870 <vscale x 4 x double> %2,871 iXLen 0, iXLen %3, iXLen 0)872 873 ret <vscale x 4 x double> %a874}875 876define <vscale x 4 x double> @intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {877; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64:878; CHECK: # %bb.0: # %entry879; CHECK-NEXT: fsrmi a1, 0880; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu881; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t882; CHECK-NEXT: fsrm a1883; CHECK-NEXT: ret884entry:885 %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64(886 <vscale x 4 x double> %0,887 double %1,888 <vscale x 4 x double> %2,889 <vscale x 4 x i1> %3,890 iXLen 0, iXLen %4, iXLen 0);891 892 ret <vscale x 4 x double> %a893}894