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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x bfloat> @intrinsic_vfmul_vv_nxv1bf16_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfmul_vv_nxv1bf16_nxv1bf16_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma12; CHECK-NEXT: vfmul.vv v8, v8, v913; CHECK-NEXT: fsrm a114; CHECK-NEXT: ret15entry:16 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.nxv1bf16(17 <vscale x 1 x bfloat> poison,18 <vscale x 1 x bfloat> %0,19 <vscale x 1 x bfloat> %1,20 iXLen 0, iXLen %2)21 22 ret <vscale x 1 x bfloat> %a23}24 25define <vscale x 1 x bfloat> @intrinsic_vfmul_mask_vv_nxv1bf16_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {26; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1bf16_nxv1bf16_nxv1bf16:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: fsrmi a1, 029; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu30; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t31; CHECK-NEXT: fsrm a132; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.mask.nxv1bf16.nxv1bf16(35 <vscale x 1 x bfloat> %0,36 <vscale x 1 x bfloat> %1,37 <vscale x 1 x bfloat> %2,38 <vscale x 1 x i1> %3,39 iXLen 0, iXLen %4, iXLen 1)40 41 ret <vscale x 1 x bfloat> %a42}43 44define <vscale x 2 x bfloat> @intrinsic_vfmul_vv_nxv2bf16_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, iXLen %2) nounwind {45; CHECK-LABEL: intrinsic_vfmul_vv_nxv2bf16_nxv2bf16_nxv2bf16:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: fsrmi a1, 048; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma49; CHECK-NEXT: vfmul.vv v8, v8, v950; CHECK-NEXT: fsrm a151; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.nxv2bf16(54 <vscale x 2 x bfloat> poison,55 <vscale x 2 x bfloat> %0,56 <vscale x 2 x bfloat> %1,57 iXLen 0, iXLen %2)58 59 ret <vscale x 2 x bfloat> %a60}61 62define <vscale x 2 x bfloat> @intrinsic_vfmul_mask_vv_nxv2bf16_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {63; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2bf16_nxv2bf16_nxv2bf16:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: fsrmi a1, 066; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu67; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t68; CHECK-NEXT: fsrm a169; CHECK-NEXT: ret70entry:71 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.mask.nxv2bf16.nxv2bf16(72 <vscale x 2 x bfloat> %0,73 <vscale x 2 x bfloat> %1,74 <vscale x 2 x bfloat> %2,75 <vscale x 2 x i1> %3,76 iXLen 0, iXLen %4, iXLen 1)77 78 ret <vscale x 2 x bfloat> %a79}80 81define <vscale x 4 x bfloat> @intrinsic_vfmul_vv_nxv4bf16_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, iXLen %2) nounwind {82; CHECK-LABEL: intrinsic_vfmul_vv_nxv4bf16_nxv4bf16_nxv4bf16:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: fsrmi a1, 085; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma86; CHECK-NEXT: vfmul.vv v8, v8, v987; CHECK-NEXT: fsrm a188; CHECK-NEXT: ret89entry:90 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.nxv4bf16(91 <vscale x 4 x bfloat> poison,92 <vscale x 4 x bfloat> %0,93 <vscale x 4 x bfloat> %1,94 iXLen 0, iXLen %2)95 96 ret <vscale x 4 x bfloat> %a97}98 99define <vscale x 4 x bfloat> @intrinsic_vfmul_mask_vv_nxv4bf16_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {100; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4bf16_nxv4bf16_nxv4bf16:101; CHECK: # %bb.0: # %entry102; CHECK-NEXT: fsrmi a1, 0103; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu104; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t105; CHECK-NEXT: fsrm a1106; CHECK-NEXT: ret107entry:108 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.mask.nxv4bf16.nxv4bf16(109 <vscale x 4 x bfloat> %0,110 <vscale x 4 x bfloat> %1,111 <vscale x 4 x bfloat> %2,112 <vscale x 4 x i1> %3,113 iXLen 0, iXLen %4, iXLen 1)114 115 ret <vscale x 4 x bfloat> %a116}117 118define <vscale x 8 x bfloat> @intrinsic_vfmul_vv_nxv8bf16_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, iXLen %2) nounwind {119; CHECK-LABEL: intrinsic_vfmul_vv_nxv8bf16_nxv8bf16_nxv8bf16:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: fsrmi a1, 0122; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma123; CHECK-NEXT: vfmul.vv v8, v8, v10124; CHECK-NEXT: fsrm a1125; CHECK-NEXT: ret126entry:127 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.nxv8bf16(128 <vscale x 8 x bfloat> poison,129 <vscale x 8 x bfloat> %0,130 <vscale x 8 x bfloat> %1,131 iXLen 0, iXLen %2)132 133 ret <vscale x 8 x bfloat> %a134}135 136define <vscale x 8 x bfloat> @intrinsic_vfmul_mask_vv_nxv8bf16_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {137; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8bf16_nxv8bf16_nxv8bf16:138; CHECK: # %bb.0: # %entry139; CHECK-NEXT: fsrmi a1, 0140; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu141; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t142; CHECK-NEXT: fsrm a1143; CHECK-NEXT: ret144entry:145 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.mask.nxv8bf16.nxv8bf16(146 <vscale x 8 x bfloat> %0,147 <vscale x 8 x bfloat> %1,148 <vscale x 8 x bfloat> %2,149 <vscale x 8 x i1> %3,150 iXLen 0, iXLen %4, iXLen 1)151 152 ret <vscale x 8 x bfloat> %a153}154 155define <vscale x 16 x bfloat> @intrinsic_vfmul_vv_nxv16bf16_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, iXLen %2) nounwind {156; CHECK-LABEL: intrinsic_vfmul_vv_nxv16bf16_nxv16bf16_nxv16bf16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: fsrmi a1, 0159; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma160; CHECK-NEXT: vfmul.vv v8, v8, v12161; CHECK-NEXT: fsrm a1162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.nxv16bf16(165 <vscale x 16 x bfloat> poison,166 <vscale x 16 x bfloat> %0,167 <vscale x 16 x bfloat> %1,168 iXLen 0, iXLen %2)169 170 ret <vscale x 16 x bfloat> %a171}172 173define <vscale x 16 x bfloat> @intrinsic_vfmul_mask_vv_nxv16bf16_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {174; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16bf16_nxv16bf16_nxv16bf16:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: fsrmi a1, 0177; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu178; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t179; CHECK-NEXT: fsrm a1180; CHECK-NEXT: ret181entry:182 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.mask.nxv16bf16.nxv16bf16(183 <vscale x 16 x bfloat> %0,184 <vscale x 16 x bfloat> %1,185 <vscale x 16 x bfloat> %2,186 <vscale x 16 x i1> %3,187 iXLen 0, iXLen %4, iXLen 1)188 189 ret <vscale x 16 x bfloat> %a190}191 192define <vscale x 32 x bfloat> @intrinsic_vfmul_vv_nxv32bf16_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, iXLen %2) nounwind {193; CHECK-LABEL: intrinsic_vfmul_vv_nxv32bf16_nxv32bf16_nxv32bf16:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: fsrmi a1, 0196; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma197; CHECK-NEXT: vfmul.vv v8, v8, v16198; CHECK-NEXT: fsrm a1199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmul.nxv32bf16.nxv32bf16(202 <vscale x 32 x bfloat> poison,203 <vscale x 32 x bfloat> %0,204 <vscale x 32 x bfloat> %1,205 iXLen 0, iXLen %2)206 207 ret <vscale x 32 x bfloat> %a208}209 210define <vscale x 32 x bfloat> @intrinsic_vfmul_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {211; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16:212; CHECK: # %bb.0: # %entry213; CHECK-NEXT: vl8re16.v v24, (a0)214; CHECK-NEXT: fsrmi a0, 0215; CHECK-NEXT: vsetvli zero, a1, e16alt, m8, ta, mu216; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t217; CHECK-NEXT: fsrm a0218; CHECK-NEXT: ret219entry:220 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmul.mask.nxv32bf16.nxv32bf16(221 <vscale x 32 x bfloat> %0,222 <vscale x 32 x bfloat> %1,223 <vscale x 32 x bfloat> %2,224 <vscale x 32 x i1> %3,225 iXLen 0, iXLen %4, iXLen 1)226 227 ret <vscale x 32 x bfloat> %a228}229 230define <vscale x 1 x bfloat> @intrinsic_vfmul_vf_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, bfloat %1, iXLen %2) nounwind {231; CHECK-LABEL: intrinsic_vfmul_vf_nxv1bf16_nxv1bf16_bf16:232; CHECK: # %bb.0: # %entry233; CHECK-NEXT: fsrmi a1, 0234; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma235; CHECK-NEXT: vfmul.vf v8, v8, fa0236; CHECK-NEXT: fsrm a1237; CHECK-NEXT: ret238entry:239 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.nxv1bf16.bf16(240 <vscale x 1 x bfloat> poison,241 <vscale x 1 x bfloat> %0,242 bfloat %1,243 iXLen 0, iXLen %2)244 245 ret <vscale x 1 x bfloat> %a246}247 248define <vscale x 1 x bfloat> @intrinsic_vfmul_mask_vf_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {249; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1bf16_nxv1bf16_bf16:250; CHECK: # %bb.0: # %entry251; CHECK-NEXT: fsrmi a1, 0252; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu253; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t254; CHECK-NEXT: fsrm a1255; CHECK-NEXT: ret256entry:257 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmul.mask.nxv1bf16.bf16(258 <vscale x 1 x bfloat> %0,259 <vscale x 1 x bfloat> %1,260 bfloat %2,261 <vscale x 1 x i1> %3,262 iXLen 0, iXLen %4, iXLen 1)263 264 ret <vscale x 1 x bfloat> %a265}266 267define <vscale x 2 x bfloat> @intrinsic_vfmul_vf_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, bfloat %1, iXLen %2) nounwind {268; CHECK-LABEL: intrinsic_vfmul_vf_nxv2bf16_nxv2bf16_bf16:269; CHECK: # %bb.0: # %entry270; CHECK-NEXT: fsrmi a1, 0271; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma272; CHECK-NEXT: vfmul.vf v8, v8, fa0273; CHECK-NEXT: fsrm a1274; CHECK-NEXT: ret275entry:276 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.nxv2bf16.bf16(277 <vscale x 2 x bfloat> poison,278 <vscale x 2 x bfloat> %0,279 bfloat %1,280 iXLen 0, iXLen %2)281 282 ret <vscale x 2 x bfloat> %a283}284 285define <vscale x 2 x bfloat> @intrinsic_vfmul_mask_vf_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {286; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2bf16_nxv2bf16_bf16:287; CHECK: # %bb.0: # %entry288; CHECK-NEXT: fsrmi a1, 0289; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu290; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t291; CHECK-NEXT: fsrm a1292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmul.mask.nxv2bf16.bf16(295 <vscale x 2 x bfloat> %0,296 <vscale x 2 x bfloat> %1,297 bfloat %2,298 <vscale x 2 x i1> %3,299 iXLen 0, iXLen %4, iXLen 1)300 301 ret <vscale x 2 x bfloat> %a302}303 304define <vscale x 4 x bfloat> @intrinsic_vfmul_vf_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, bfloat %1, iXLen %2) nounwind {305; CHECK-LABEL: intrinsic_vfmul_vf_nxv4bf16_nxv4bf16_bf16:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: fsrmi a1, 0308; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma309; CHECK-NEXT: vfmul.vf v8, v8, fa0310; CHECK-NEXT: fsrm a1311; CHECK-NEXT: ret312entry:313 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.nxv4bf16.bf16(314 <vscale x 4 x bfloat> poison,315 <vscale x 4 x bfloat> %0,316 bfloat %1,317 iXLen 0, iXLen %2)318 319 ret <vscale x 4 x bfloat> %a320}321 322define <vscale x 4 x bfloat> @intrinsic_vfmul_mask_vf_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {323; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4bf16_nxv4bf16_bf16:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: fsrmi a1, 0326; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu327; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t328; CHECK-NEXT: fsrm a1329; CHECK-NEXT: ret330entry:331 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmul.mask.nxv4bf16.bf16(332 <vscale x 4 x bfloat> %0,333 <vscale x 4 x bfloat> %1,334 bfloat %2,335 <vscale x 4 x i1> %3,336 iXLen 0, iXLen %4, iXLen 1)337 338 ret <vscale x 4 x bfloat> %a339}340 341define <vscale x 8 x bfloat> @intrinsic_vfmul_vf_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, bfloat %1, iXLen %2) nounwind {342; CHECK-LABEL: intrinsic_vfmul_vf_nxv8bf16_nxv8bf16_bf16:343; CHECK: # %bb.0: # %entry344; CHECK-NEXT: fsrmi a1, 0345; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma346; CHECK-NEXT: vfmul.vf v8, v8, fa0347; CHECK-NEXT: fsrm a1348; CHECK-NEXT: ret349entry:350 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.nxv8bf16.bf16(351 <vscale x 8 x bfloat> poison,352 <vscale x 8 x bfloat> %0,353 bfloat %1,354 iXLen 0, iXLen %2)355 356 ret <vscale x 8 x bfloat> %a357}358 359define <vscale x 8 x bfloat> @intrinsic_vfmul_mask_vf_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {360; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8bf16_nxv8bf16_bf16:361; CHECK: # %bb.0: # %entry362; CHECK-NEXT: fsrmi a1, 0363; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu364; CHECK-NEXT: vfmul.vf v8, v10, fa0, v0.t365; CHECK-NEXT: fsrm a1366; CHECK-NEXT: ret367entry:368 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmul.mask.nxv8bf16.bf16(369 <vscale x 8 x bfloat> %0,370 <vscale x 8 x bfloat> %1,371 bfloat %2,372 <vscale x 8 x i1> %3,373 iXLen 0, iXLen %4, iXLen 1)374 375 ret <vscale x 8 x bfloat> %a376}377 378define <vscale x 16 x bfloat> @intrinsic_vfmul_vf_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, bfloat %1, iXLen %2) nounwind {379; CHECK-LABEL: intrinsic_vfmul_vf_nxv16bf16_nxv16bf16_bf16:380; CHECK: # %bb.0: # %entry381; CHECK-NEXT: fsrmi a1, 0382; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma383; CHECK-NEXT: vfmul.vf v8, v8, fa0384; CHECK-NEXT: fsrm a1385; CHECK-NEXT: ret386entry:387 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.nxv16bf16.bf16(388 <vscale x 16 x bfloat> poison,389 <vscale x 16 x bfloat> %0,390 bfloat %1,391 iXLen 0, iXLen %2)392 393 ret <vscale x 16 x bfloat> %a394}395 396define <vscale x 16 x bfloat> @intrinsic_vfmul_mask_vf_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {397; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16bf16_nxv16bf16_bf16:398; CHECK: # %bb.0: # %entry399; CHECK-NEXT: fsrmi a1, 0400; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu401; CHECK-NEXT: vfmul.vf v8, v12, fa0, v0.t402; CHECK-NEXT: fsrm a1403; CHECK-NEXT: ret404entry:405 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmul.mask.nxv16bf16.bf16(406 <vscale x 16 x bfloat> %0,407 <vscale x 16 x bfloat> %1,408 bfloat %2,409 <vscale x 16 x i1> %3,410 iXLen 0, iXLen %4, iXLen 1)411 412 ret <vscale x 16 x bfloat> %a413}414 415define <vscale x 32 x bfloat> @intrinsic_vfmul_vf_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, bfloat %1, iXLen %2) nounwind {416; CHECK-LABEL: intrinsic_vfmul_vf_nxv32bf16_nxv32bf16_bf16:417; CHECK: # %bb.0: # %entry418; CHECK-NEXT: fsrmi a1, 0419; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma420; CHECK-NEXT: vfmul.vf v8, v8, fa0421; CHECK-NEXT: fsrm a1422; CHECK-NEXT: ret423entry:424 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmul.nxv32bf16.bf16(425 <vscale x 32 x bfloat> poison,426 <vscale x 32 x bfloat> %0,427 bfloat %1,428 iXLen 0, iXLen %2)429 430 ret <vscale x 32 x bfloat> %a431}432 433define <vscale x 32 x bfloat> @intrinsic_vfmul_mask_vf_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {434; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv32bf16_nxv32bf16_bf16:435; CHECK: # %bb.0: # %entry436; CHECK-NEXT: fsrmi a1, 0437; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, mu438; CHECK-NEXT: vfmul.vf v8, v16, fa0, v0.t439; CHECK-NEXT: fsrm a1440; CHECK-NEXT: ret441entry:442 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmul.mask.nxv32bf16.bf16(443 <vscale x 32 x bfloat> %0,444 <vscale x 32 x bfloat> %1,445 bfloat %2,446 <vscale x 32 x i1> %3,447 iXLen 0, iXLen %4, iXLen 1)448 449 ret <vscale x 32 x bfloat> %a450}451 452