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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x half> @intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma12; CHECK-NEXT: vfmul.vv v8, v8, v913; CHECK-NEXT: fsrm a114; CHECK-NEXT: ret15entry:16 %a = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16(17 <vscale x 1 x half> poison,18 <vscale x 1 x half> %0,19 <vscale x 1 x half> %1,20 iXLen 0, iXLen %2)21 22 ret <vscale x 1 x half> %a23}24 25define <vscale x 1 x half> @intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {26; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16_nxv1f16:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: fsrmi a1, 029; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu30; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t31; CHECK-NEXT: fsrm a132; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x half> @llvm.riscv.vfmul.mask.nxv1f16.nxv1f16(35 <vscale x 1 x half> %0,36 <vscale x 1 x half> %1,37 <vscale x 1 x half> %2,38 <vscale x 1 x i1> %3,39 iXLen 0, iXLen %4, iXLen 1)40 41 ret <vscale x 1 x half> %a42}43 44define <vscale x 2 x half> @intrinsic_vfmul_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {45; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f16_nxv2f16_nxv2f16:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: fsrmi a1, 048; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma49; CHECK-NEXT: vfmul.vv v8, v8, v950; CHECK-NEXT: fsrm a151; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.nxv2f16(54 <vscale x 2 x half> poison,55 <vscale x 2 x half> %0,56 <vscale x 2 x half> %1,57 iXLen 0, iXLen %2)58 59 ret <vscale x 2 x half> %a60}61 62define <vscale x 2 x half> @intrinsic_vfmul_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {63; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f16_nxv2f16_nxv2f16:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: fsrmi a1, 066; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu67; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t68; CHECK-NEXT: fsrm a169; CHECK-NEXT: ret70entry:71 %a = call <vscale x 2 x half> @llvm.riscv.vfmul.mask.nxv2f16.nxv2f16(72 <vscale x 2 x half> %0,73 <vscale x 2 x half> %1,74 <vscale x 2 x half> %2,75 <vscale x 2 x i1> %3,76 iXLen 0, iXLen %4, iXLen 1)77 78 ret <vscale x 2 x half> %a79}80 81define <vscale x 4 x half> @intrinsic_vfmul_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {82; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f16_nxv4f16_nxv4f16:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: fsrmi a1, 085; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma86; CHECK-NEXT: vfmul.vv v8, v8, v987; CHECK-NEXT: fsrm a188; CHECK-NEXT: ret89entry:90 %a = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.nxv4f16(91 <vscale x 4 x half> poison,92 <vscale x 4 x half> %0,93 <vscale x 4 x half> %1,94 iXLen 0, iXLen %2)95 96 ret <vscale x 4 x half> %a97}98 99define <vscale x 4 x half> @intrinsic_vfmul_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {100; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f16_nxv4f16_nxv4f16:101; CHECK: # %bb.0: # %entry102; CHECK-NEXT: fsrmi a1, 0103; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu104; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t105; CHECK-NEXT: fsrm a1106; CHECK-NEXT: ret107entry:108 %a = call <vscale x 4 x half> @llvm.riscv.vfmul.mask.nxv4f16.nxv4f16(109 <vscale x 4 x half> %0,110 <vscale x 4 x half> %1,111 <vscale x 4 x half> %2,112 <vscale x 4 x i1> %3,113 iXLen 0, iXLen %4, iXLen 1)114 115 ret <vscale x 4 x half> %a116}117 118define <vscale x 8 x half> @intrinsic_vfmul_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {119; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f16_nxv8f16_nxv8f16:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: fsrmi a1, 0122; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma123; CHECK-NEXT: vfmul.vv v8, v8, v10124; CHECK-NEXT: fsrm a1125; CHECK-NEXT: ret126entry:127 %a = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.nxv8f16(128 <vscale x 8 x half> poison,129 <vscale x 8 x half> %0,130 <vscale x 8 x half> %1,131 iXLen 0, iXLen %2)132 133 ret <vscale x 8 x half> %a134}135 136define <vscale x 8 x half> @intrinsic_vfmul_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {137; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f16_nxv8f16_nxv8f16:138; CHECK: # %bb.0: # %entry139; CHECK-NEXT: fsrmi a1, 0140; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu141; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t142; CHECK-NEXT: fsrm a1143; CHECK-NEXT: ret144entry:145 %a = call <vscale x 8 x half> @llvm.riscv.vfmul.mask.nxv8f16.nxv8f16(146 <vscale x 8 x half> %0,147 <vscale x 8 x half> %1,148 <vscale x 8 x half> %2,149 <vscale x 8 x i1> %3,150 iXLen 0, iXLen %4, iXLen 1)151 152 ret <vscale x 8 x half> %a153}154 155define <vscale x 16 x half> @intrinsic_vfmul_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {156; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f16_nxv16f16_nxv16f16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: fsrmi a1, 0159; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma160; CHECK-NEXT: vfmul.vv v8, v8, v12161; CHECK-NEXT: fsrm a1162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.nxv16f16(165 <vscale x 16 x half> poison,166 <vscale x 16 x half> %0,167 <vscale x 16 x half> %1,168 iXLen 0, iXLen %2)169 170 ret <vscale x 16 x half> %a171}172 173define <vscale x 16 x half> @intrinsic_vfmul_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {174; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f16_nxv16f16_nxv16f16:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: fsrmi a1, 0177; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu178; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t179; CHECK-NEXT: fsrm a1180; CHECK-NEXT: ret181entry:182 %a = call <vscale x 16 x half> @llvm.riscv.vfmul.mask.nxv16f16.nxv16f16(183 <vscale x 16 x half> %0,184 <vscale x 16 x half> %1,185 <vscale x 16 x half> %2,186 <vscale x 16 x i1> %3,187 iXLen 0, iXLen %4, iXLen 1)188 189 ret <vscale x 16 x half> %a190}191 192define <vscale x 32 x half> @intrinsic_vfmul_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, iXLen %2) nounwind {193; CHECK-LABEL: intrinsic_vfmul_vv_nxv32f16_nxv32f16_nxv32f16:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: fsrmi a1, 0196; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma197; CHECK-NEXT: vfmul.vv v8, v8, v16198; CHECK-NEXT: fsrm a1199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 32 x half> @llvm.riscv.vfmul.nxv32f16.nxv32f16(202 <vscale x 32 x half> poison,203 <vscale x 32 x half> %0,204 <vscale x 32 x half> %1,205 iXLen 0, iXLen %2)206 207 ret <vscale x 32 x half> %a208}209 210define <vscale x 32 x half> @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {211; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16:212; CHECK: # %bb.0: # %entry213; CHECK-NEXT: vl8re16.v v24, (a0)214; CHECK-NEXT: fsrmi a0, 0215; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu216; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t217; CHECK-NEXT: fsrm a0218; CHECK-NEXT: ret219entry:220 %a = call <vscale x 32 x half> @llvm.riscv.vfmul.mask.nxv32f16.nxv32f16(221 <vscale x 32 x half> %0,222 <vscale x 32 x half> %1,223 <vscale x 32 x half> %2,224 <vscale x 32 x i1> %3,225 iXLen 0, iXLen %4, iXLen 1)226 227 ret <vscale x 32 x half> %a228}229 230define <vscale x 1 x float> @intrinsic_vfmul_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {231; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f32_nxv1f32_nxv1f32:232; CHECK: # %bb.0: # %entry233; CHECK-NEXT: fsrmi a1, 0234; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma235; CHECK-NEXT: vfmul.vv v8, v8, v9236; CHECK-NEXT: fsrm a1237; CHECK-NEXT: ret238entry:239 %a = call <vscale x 1 x float> @llvm.riscv.vfmul.nxv1f32.nxv1f32(240 <vscale x 1 x float> poison,241 <vscale x 1 x float> %0,242 <vscale x 1 x float> %1,243 iXLen 0, iXLen %2)244 245 ret <vscale x 1 x float> %a246}247 248define <vscale x 1 x float> @intrinsic_vfmul_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {249; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f32_nxv1f32_nxv1f32:250; CHECK: # %bb.0: # %entry251; CHECK-NEXT: fsrmi a1, 0252; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu253; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t254; CHECK-NEXT: fsrm a1255; CHECK-NEXT: ret256entry:257 %a = call <vscale x 1 x float> @llvm.riscv.vfmul.mask.nxv1f32.nxv1f32(258 <vscale x 1 x float> %0,259 <vscale x 1 x float> %1,260 <vscale x 1 x float> %2,261 <vscale x 1 x i1> %3,262 iXLen 0, iXLen %4, iXLen 1)263 264 ret <vscale x 1 x float> %a265}266 267define <vscale x 2 x float> @intrinsic_vfmul_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {268; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f32_nxv2f32_nxv2f32:269; CHECK: # %bb.0: # %entry270; CHECK-NEXT: fsrmi a1, 0271; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma272; CHECK-NEXT: vfmul.vv v8, v8, v9273; CHECK-NEXT: fsrm a1274; CHECK-NEXT: ret275entry:276 %a = call <vscale x 2 x float> @llvm.riscv.vfmul.nxv2f32.nxv2f32(277 <vscale x 2 x float> poison,278 <vscale x 2 x float> %0,279 <vscale x 2 x float> %1,280 iXLen 0, iXLen %2)281 282 ret <vscale x 2 x float> %a283}284 285define <vscale x 2 x float> @intrinsic_vfmul_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {286; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f32_nxv2f32_nxv2f32:287; CHECK: # %bb.0: # %entry288; CHECK-NEXT: fsrmi a1, 0289; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu290; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t291; CHECK-NEXT: fsrm a1292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 2 x float> @llvm.riscv.vfmul.mask.nxv2f32.nxv2f32(295 <vscale x 2 x float> %0,296 <vscale x 2 x float> %1,297 <vscale x 2 x float> %2,298 <vscale x 2 x i1> %3,299 iXLen 0, iXLen %4, iXLen 1)300 301 ret <vscale x 2 x float> %a302}303 304define <vscale x 4 x float> @intrinsic_vfmul_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {305; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f32_nxv4f32_nxv4f32:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: fsrmi a1, 0308; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma309; CHECK-NEXT: vfmul.vv v8, v8, v10310; CHECK-NEXT: fsrm a1311; CHECK-NEXT: ret312entry:313 %a = call <vscale x 4 x float> @llvm.riscv.vfmul.nxv4f32.nxv4f32(314 <vscale x 4 x float> poison,315 <vscale x 4 x float> %0,316 <vscale x 4 x float> %1,317 iXLen 0, iXLen %2)318 319 ret <vscale x 4 x float> %a320}321 322define <vscale x 4 x float> @intrinsic_vfmul_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {323; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f32_nxv4f32_nxv4f32:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: fsrmi a1, 0326; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu327; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t328; CHECK-NEXT: fsrm a1329; CHECK-NEXT: ret330entry:331 %a = call <vscale x 4 x float> @llvm.riscv.vfmul.mask.nxv4f32.nxv4f32(332 <vscale x 4 x float> %0,333 <vscale x 4 x float> %1,334 <vscale x 4 x float> %2,335 <vscale x 4 x i1> %3,336 iXLen 0, iXLen %4, iXLen 1)337 338 ret <vscale x 4 x float> %a339}340 341define <vscale x 8 x float> @intrinsic_vfmul_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {342; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f32_nxv8f32_nxv8f32:343; CHECK: # %bb.0: # %entry344; CHECK-NEXT: fsrmi a1, 0345; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma346; CHECK-NEXT: vfmul.vv v8, v8, v12347; CHECK-NEXT: fsrm a1348; CHECK-NEXT: ret349entry:350 %a = call <vscale x 8 x float> @llvm.riscv.vfmul.nxv8f32.nxv8f32(351 <vscale x 8 x float> poison,352 <vscale x 8 x float> %0,353 <vscale x 8 x float> %1,354 iXLen 0, iXLen %2)355 356 ret <vscale x 8 x float> %a357}358 359define <vscale x 8 x float> @intrinsic_vfmul_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {360; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f32_nxv8f32_nxv8f32:361; CHECK: # %bb.0: # %entry362; CHECK-NEXT: fsrmi a1, 0363; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu364; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t365; CHECK-NEXT: fsrm a1366; CHECK-NEXT: ret367entry:368 %a = call <vscale x 8 x float> @llvm.riscv.vfmul.mask.nxv8f32.nxv8f32(369 <vscale x 8 x float> %0,370 <vscale x 8 x float> %1,371 <vscale x 8 x float> %2,372 <vscale x 8 x i1> %3,373 iXLen 0, iXLen %4, iXLen 1)374 375 ret <vscale x 8 x float> %a376}377 378define <vscale x 16 x float> @intrinsic_vfmul_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, iXLen %2) nounwind {379; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f32_nxv16f32_nxv16f32:380; CHECK: # %bb.0: # %entry381; CHECK-NEXT: fsrmi a1, 0382; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma383; CHECK-NEXT: vfmul.vv v8, v8, v16384; CHECK-NEXT: fsrm a1385; CHECK-NEXT: ret386entry:387 %a = call <vscale x 16 x float> @llvm.riscv.vfmul.nxv16f32.nxv16f32(388 <vscale x 16 x float> poison,389 <vscale x 16 x float> %0,390 <vscale x 16 x float> %1,391 iXLen 0, iXLen %2)392 393 ret <vscale x 16 x float> %a394}395 396define <vscale x 16 x float> @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {397; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32:398; CHECK: # %bb.0: # %entry399; CHECK-NEXT: vl8re32.v v24, (a0)400; CHECK-NEXT: fsrmi a0, 0401; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu402; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t403; CHECK-NEXT: fsrm a0404; CHECK-NEXT: ret405entry:406 %a = call <vscale x 16 x float> @llvm.riscv.vfmul.mask.nxv16f32.nxv16f32(407 <vscale x 16 x float> %0,408 <vscale x 16 x float> %1,409 <vscale x 16 x float> %2,410 <vscale x 16 x i1> %3,411 iXLen 0, iXLen %4, iXLen 1)412 413 ret <vscale x 16 x float> %a414}415 416define <vscale x 1 x double> @intrinsic_vfmul_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {417; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f64_nxv1f64_nxv1f64:418; CHECK: # %bb.0: # %entry419; CHECK-NEXT: fsrmi a1, 0420; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma421; CHECK-NEXT: vfmul.vv v8, v8, v9422; CHECK-NEXT: fsrm a1423; CHECK-NEXT: ret424entry:425 %a = call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(426 <vscale x 1 x double> poison,427 <vscale x 1 x double> %0,428 <vscale x 1 x double> %1,429 iXLen 0, iXLen %2)430 431 ret <vscale x 1 x double> %a432}433 434define <vscale x 1 x double> @intrinsic_vfmul_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {435; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f64_nxv1f64_nxv1f64:436; CHECK: # %bb.0: # %entry437; CHECK-NEXT: fsrmi a1, 0438; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu439; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t440; CHECK-NEXT: fsrm a1441; CHECK-NEXT: ret442entry:443 %a = call <vscale x 1 x double> @llvm.riscv.vfmul.mask.nxv1f64.nxv1f64(444 <vscale x 1 x double> %0,445 <vscale x 1 x double> %1,446 <vscale x 1 x double> %2,447 <vscale x 1 x i1> %3,448 iXLen 0, iXLen %4, iXLen 1)449 450 ret <vscale x 1 x double> %a451}452 453define <vscale x 2 x double> @intrinsic_vfmul_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {454; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f64_nxv2f64_nxv2f64:455; CHECK: # %bb.0: # %entry456; CHECK-NEXT: fsrmi a1, 0457; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma458; CHECK-NEXT: vfmul.vv v8, v8, v10459; CHECK-NEXT: fsrm a1460; CHECK-NEXT: ret461entry:462 %a = call <vscale x 2 x double> @llvm.riscv.vfmul.nxv2f64.nxv2f64(463 <vscale x 2 x double> poison,464 <vscale x 2 x double> %0,465 <vscale x 2 x double> %1,466 iXLen 0, iXLen %2)467 468 ret <vscale x 2 x double> %a469}470 471define <vscale x 2 x double> @intrinsic_vfmul_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {472; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f64_nxv2f64_nxv2f64:473; CHECK: # %bb.0: # %entry474; CHECK-NEXT: fsrmi a1, 0475; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu476; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t477; CHECK-NEXT: fsrm a1478; CHECK-NEXT: ret479entry:480 %a = call <vscale x 2 x double> @llvm.riscv.vfmul.mask.nxv2f64.nxv2f64(481 <vscale x 2 x double> %0,482 <vscale x 2 x double> %1,483 <vscale x 2 x double> %2,484 <vscale x 2 x i1> %3,485 iXLen 0, iXLen %4, iXLen 1)486 487 ret <vscale x 2 x double> %a488}489 490define <vscale x 4 x double> @intrinsic_vfmul_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {491; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f64_nxv4f64_nxv4f64:492; CHECK: # %bb.0: # %entry493; CHECK-NEXT: fsrmi a1, 0494; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma495; CHECK-NEXT: vfmul.vv v8, v8, v12496; CHECK-NEXT: fsrm a1497; CHECK-NEXT: ret498entry:499 %a = call <vscale x 4 x double> @llvm.riscv.vfmul.nxv4f64.nxv4f64(500 <vscale x 4 x double> poison,501 <vscale x 4 x double> %0,502 <vscale x 4 x double> %1,503 iXLen 0, iXLen %2)504 505 ret <vscale x 4 x double> %a506}507 508define <vscale x 4 x double> @intrinsic_vfmul_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {509; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f64_nxv4f64_nxv4f64:510; CHECK: # %bb.0: # %entry511; CHECK-NEXT: fsrmi a1, 0512; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu513; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t514; CHECK-NEXT: fsrm a1515; CHECK-NEXT: ret516entry:517 %a = call <vscale x 4 x double> @llvm.riscv.vfmul.mask.nxv4f64.nxv4f64(518 <vscale x 4 x double> %0,519 <vscale x 4 x double> %1,520 <vscale x 4 x double> %2,521 <vscale x 4 x i1> %3,522 iXLen 0, iXLen %4, iXLen 1)523 524 ret <vscale x 4 x double> %a525}526 527define <vscale x 8 x double> @intrinsic_vfmul_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, iXLen %2) nounwind {528; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f64_nxv8f64_nxv8f64:529; CHECK: # %bb.0: # %entry530; CHECK-NEXT: fsrmi a1, 0531; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma532; CHECK-NEXT: vfmul.vv v8, v8, v16533; CHECK-NEXT: fsrm a1534; CHECK-NEXT: ret535entry:536 %a = call <vscale x 8 x double> @llvm.riscv.vfmul.nxv8f64.nxv8f64(537 <vscale x 8 x double> poison,538 <vscale x 8 x double> %0,539 <vscale x 8 x double> %1,540 iXLen 0, iXLen %2)541 542 ret <vscale x 8 x double> %a543}544 545define <vscale x 8 x double> @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {546; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64:547; CHECK: # %bb.0: # %entry548; CHECK-NEXT: vl8re64.v v24, (a0)549; CHECK-NEXT: fsrmi a0, 0550; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu551; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t552; CHECK-NEXT: fsrm a0553; CHECK-NEXT: ret554entry:555 %a = call <vscale x 8 x double> @llvm.riscv.vfmul.mask.nxv8f64.nxv8f64(556 <vscale x 8 x double> %0,557 <vscale x 8 x double> %1,558 <vscale x 8 x double> %2,559 <vscale x 8 x i1> %3,560 iXLen 0, iXLen %4, iXLen 1)561 562 ret <vscale x 8 x double> %a563}564 565define <vscale x 1 x half> @intrinsic_vfmul_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {566; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f16_nxv1f16_f16:567; CHECK: # %bb.0: # %entry568; CHECK-NEXT: fsrmi a1, 0569; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma570; CHECK-NEXT: vfmul.vf v8, v8, fa0571; CHECK-NEXT: fsrm a1572; CHECK-NEXT: ret573entry:574 %a = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.f16(575 <vscale x 1 x half> poison,576 <vscale x 1 x half> %0,577 half %1,578 iXLen 0, iXLen %2)579 580 ret <vscale x 1 x half> %a581}582 583define <vscale x 1 x half> @intrinsic_vfmul_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {584; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f16_nxv1f16_f16:585; CHECK: # %bb.0: # %entry586; CHECK-NEXT: fsrmi a1, 0587; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu588; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t589; CHECK-NEXT: fsrm a1590; CHECK-NEXT: ret591entry:592 %a = call <vscale x 1 x half> @llvm.riscv.vfmul.mask.nxv1f16.f16(593 <vscale x 1 x half> %0,594 <vscale x 1 x half> %1,595 half %2,596 <vscale x 1 x i1> %3,597 iXLen 0, iXLen %4, iXLen 1)598 599 ret <vscale x 1 x half> %a600}601 602define <vscale x 2 x half> @intrinsic_vfmul_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {603; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f16_nxv2f16_f16:604; CHECK: # %bb.0: # %entry605; CHECK-NEXT: fsrmi a1, 0606; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma607; CHECK-NEXT: vfmul.vf v8, v8, fa0608; CHECK-NEXT: fsrm a1609; CHECK-NEXT: ret610entry:611 %a = call <vscale x 2 x half> @llvm.riscv.vfmul.nxv2f16.f16(612 <vscale x 2 x half> poison,613 <vscale x 2 x half> %0,614 half %1,615 iXLen 0, iXLen %2)616 617 ret <vscale x 2 x half> %a618}619 620define <vscale x 2 x half> @intrinsic_vfmul_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {621; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f16_nxv2f16_f16:622; CHECK: # %bb.0: # %entry623; CHECK-NEXT: fsrmi a1, 0624; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu625; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t626; CHECK-NEXT: fsrm a1627; CHECK-NEXT: ret628entry:629 %a = call <vscale x 2 x half> @llvm.riscv.vfmul.mask.nxv2f16.f16(630 <vscale x 2 x half> %0,631 <vscale x 2 x half> %1,632 half %2,633 <vscale x 2 x i1> %3,634 iXLen 0, iXLen %4, iXLen 1)635 636 ret <vscale x 2 x half> %a637}638 639define <vscale x 4 x half> @intrinsic_vfmul_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {640; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f16_nxv4f16_f16:641; CHECK: # %bb.0: # %entry642; CHECK-NEXT: fsrmi a1, 0643; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma644; CHECK-NEXT: vfmul.vf v8, v8, fa0645; CHECK-NEXT: fsrm a1646; CHECK-NEXT: ret647entry:648 %a = call <vscale x 4 x half> @llvm.riscv.vfmul.nxv4f16.f16(649 <vscale x 4 x half> poison,650 <vscale x 4 x half> %0,651 half %1,652 iXLen 0, iXLen %2)653 654 ret <vscale x 4 x half> %a655}656 657define <vscale x 4 x half> @intrinsic_vfmul_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {658; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f16_nxv4f16_f16:659; CHECK: # %bb.0: # %entry660; CHECK-NEXT: fsrmi a1, 0661; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu662; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t663; CHECK-NEXT: fsrm a1664; CHECK-NEXT: ret665entry:666 %a = call <vscale x 4 x half> @llvm.riscv.vfmul.mask.nxv4f16.f16(667 <vscale x 4 x half> %0,668 <vscale x 4 x half> %1,669 half %2,670 <vscale x 4 x i1> %3,671 iXLen 0, iXLen %4, iXLen 1)672 673 ret <vscale x 4 x half> %a674}675 676define <vscale x 8 x half> @intrinsic_vfmul_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {677; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f16_nxv8f16_f16:678; CHECK: # %bb.0: # %entry679; CHECK-NEXT: fsrmi a1, 0680; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma681; CHECK-NEXT: vfmul.vf v8, v8, fa0682; CHECK-NEXT: fsrm a1683; CHECK-NEXT: ret684entry:685 %a = call <vscale x 8 x half> @llvm.riscv.vfmul.nxv8f16.f16(686 <vscale x 8 x half> poison,687 <vscale x 8 x half> %0,688 half %1,689 iXLen 0, iXLen %2)690 691 ret <vscale x 8 x half> %a692}693 694define <vscale x 8 x half> @intrinsic_vfmul_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {695; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f16_nxv8f16_f16:696; CHECK: # %bb.0: # %entry697; CHECK-NEXT: fsrmi a1, 0698; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu699; CHECK-NEXT: vfmul.vf v8, v10, fa0, v0.t700; CHECK-NEXT: fsrm a1701; CHECK-NEXT: ret702entry:703 %a = call <vscale x 8 x half> @llvm.riscv.vfmul.mask.nxv8f16.f16(704 <vscale x 8 x half> %0,705 <vscale x 8 x half> %1,706 half %2,707 <vscale x 8 x i1> %3,708 iXLen 0, iXLen %4, iXLen 1)709 710 ret <vscale x 8 x half> %a711}712 713define <vscale x 16 x half> @intrinsic_vfmul_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {714; CHECK-LABEL: intrinsic_vfmul_vf_nxv16f16_nxv16f16_f16:715; CHECK: # %bb.0: # %entry716; CHECK-NEXT: fsrmi a1, 0717; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma718; CHECK-NEXT: vfmul.vf v8, v8, fa0719; CHECK-NEXT: fsrm a1720; CHECK-NEXT: ret721entry:722 %a = call <vscale x 16 x half> @llvm.riscv.vfmul.nxv16f16.f16(723 <vscale x 16 x half> poison,724 <vscale x 16 x half> %0,725 half %1,726 iXLen 0, iXLen %2)727 728 ret <vscale x 16 x half> %a729}730 731define <vscale x 16 x half> @intrinsic_vfmul_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {732; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16f16_nxv16f16_f16:733; CHECK: # %bb.0: # %entry734; CHECK-NEXT: fsrmi a1, 0735; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu736; CHECK-NEXT: vfmul.vf v8, v12, fa0, v0.t737; CHECK-NEXT: fsrm a1738; CHECK-NEXT: ret739entry:740 %a = call <vscale x 16 x half> @llvm.riscv.vfmul.mask.nxv16f16.f16(741 <vscale x 16 x half> %0,742 <vscale x 16 x half> %1,743 half %2,744 <vscale x 16 x i1> %3,745 iXLen 0, iXLen %4, iXLen 1)746 747 ret <vscale x 16 x half> %a748}749 750define <vscale x 32 x half> @intrinsic_vfmul_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, iXLen %2) nounwind {751; CHECK-LABEL: intrinsic_vfmul_vf_nxv32f16_nxv32f16_f16:752; CHECK: # %bb.0: # %entry753; CHECK-NEXT: fsrmi a1, 0754; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma755; CHECK-NEXT: vfmul.vf v8, v8, fa0756; CHECK-NEXT: fsrm a1757; CHECK-NEXT: ret758entry:759 %a = call <vscale x 32 x half> @llvm.riscv.vfmul.nxv32f16.f16(760 <vscale x 32 x half> poison,761 <vscale x 32 x half> %0,762 half %1,763 iXLen 0, iXLen %2)764 765 ret <vscale x 32 x half> %a766}767 768define <vscale x 32 x half> @intrinsic_vfmul_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {769; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv32f16_nxv32f16_f16:770; CHECK: # %bb.0: # %entry771; CHECK-NEXT: fsrmi a1, 0772; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu773; CHECK-NEXT: vfmul.vf v8, v16, fa0, v0.t774; CHECK-NEXT: fsrm a1775; CHECK-NEXT: ret776entry:777 %a = call <vscale x 32 x half> @llvm.riscv.vfmul.mask.nxv32f16.f16(778 <vscale x 32 x half> %0,779 <vscale x 32 x half> %1,780 half %2,781 <vscale x 32 x i1> %3,782 iXLen 0, iXLen %4, iXLen 1)783 784 ret <vscale x 32 x half> %a785}786 787define <vscale x 1 x float> @intrinsic_vfmul_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {788; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f32_nxv1f32_f32:789; CHECK: # %bb.0: # %entry790; CHECK-NEXT: fsrmi a1, 0791; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma792; CHECK-NEXT: vfmul.vf v8, v8, fa0793; CHECK-NEXT: fsrm a1794; CHECK-NEXT: ret795entry:796 %a = call <vscale x 1 x float> @llvm.riscv.vfmul.nxv1f32.f32(797 <vscale x 1 x float> poison,798 <vscale x 1 x float> %0,799 float %1,800 iXLen 0, iXLen %2)801 802 ret <vscale x 1 x float> %a803}804 805define <vscale x 1 x float> @intrinsic_vfmul_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {806; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f32_nxv1f32_f32:807; CHECK: # %bb.0: # %entry808; CHECK-NEXT: fsrmi a1, 0809; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu810; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t811; CHECK-NEXT: fsrm a1812; CHECK-NEXT: ret813entry:814 %a = call <vscale x 1 x float> @llvm.riscv.vfmul.mask.nxv1f32.f32(815 <vscale x 1 x float> %0,816 <vscale x 1 x float> %1,817 float %2,818 <vscale x 1 x i1> %3,819 iXLen 0, iXLen %4, iXLen 1)820 821 ret <vscale x 1 x float> %a822}823 824define <vscale x 2 x float> @intrinsic_vfmul_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {825; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f32_nxv2f32_f32:826; CHECK: # %bb.0: # %entry827; CHECK-NEXT: fsrmi a1, 0828; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma829; CHECK-NEXT: vfmul.vf v8, v8, fa0830; CHECK-NEXT: fsrm a1831; CHECK-NEXT: ret832entry:833 %a = call <vscale x 2 x float> @llvm.riscv.vfmul.nxv2f32.f32(834 <vscale x 2 x float> poison,835 <vscale x 2 x float> %0,836 float %1,837 iXLen 0, iXLen %2)838 839 ret <vscale x 2 x float> %a840}841 842define <vscale x 2 x float> @intrinsic_vfmul_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {843; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f32_nxv2f32_f32:844; CHECK: # %bb.0: # %entry845; CHECK-NEXT: fsrmi a1, 0846; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu847; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t848; CHECK-NEXT: fsrm a1849; CHECK-NEXT: ret850entry:851 %a = call <vscale x 2 x float> @llvm.riscv.vfmul.mask.nxv2f32.f32(852 <vscale x 2 x float> %0,853 <vscale x 2 x float> %1,854 float %2,855 <vscale x 2 x i1> %3,856 iXLen 0, iXLen %4, iXLen 1)857 858 ret <vscale x 2 x float> %a859}860 861define <vscale x 4 x float> @intrinsic_vfmul_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {862; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f32_nxv4f32_f32:863; CHECK: # %bb.0: # %entry864; CHECK-NEXT: fsrmi a1, 0865; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma866; CHECK-NEXT: vfmul.vf v8, v8, fa0867; CHECK-NEXT: fsrm a1868; CHECK-NEXT: ret869entry:870 %a = call <vscale x 4 x float> @llvm.riscv.vfmul.nxv4f32.f32(871 <vscale x 4 x float> poison,872 <vscale x 4 x float> %0,873 float %1,874 iXLen 0, iXLen %2)875 876 ret <vscale x 4 x float> %a877}878 879define <vscale x 4 x float> @intrinsic_vfmul_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {880; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f32_nxv4f32_f32:881; CHECK: # %bb.0: # %entry882; CHECK-NEXT: fsrmi a1, 0883; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu884; CHECK-NEXT: vfmul.vf v8, v10, fa0, v0.t885; CHECK-NEXT: fsrm a1886; CHECK-NEXT: ret887entry:888 %a = call <vscale x 4 x float> @llvm.riscv.vfmul.mask.nxv4f32.f32(889 <vscale x 4 x float> %0,890 <vscale x 4 x float> %1,891 float %2,892 <vscale x 4 x i1> %3,893 iXLen 0, iXLen %4, iXLen 1)894 895 ret <vscale x 4 x float> %a896}897 898define <vscale x 8 x float> @intrinsic_vfmul_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {899; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f32_nxv8f32_f32:900; CHECK: # %bb.0: # %entry901; CHECK-NEXT: fsrmi a1, 0902; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma903; CHECK-NEXT: vfmul.vf v8, v8, fa0904; CHECK-NEXT: fsrm a1905; CHECK-NEXT: ret906entry:907 %a = call <vscale x 8 x float> @llvm.riscv.vfmul.nxv8f32.f32(908 <vscale x 8 x float> poison,909 <vscale x 8 x float> %0,910 float %1,911 iXLen 0, iXLen %2)912 913 ret <vscale x 8 x float> %a914}915 916define <vscale x 8 x float> @intrinsic_vfmul_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {917; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f32_nxv8f32_f32:918; CHECK: # %bb.0: # %entry919; CHECK-NEXT: fsrmi a1, 0920; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu921; CHECK-NEXT: vfmul.vf v8, v12, fa0, v0.t922; CHECK-NEXT: fsrm a1923; CHECK-NEXT: ret924entry:925 %a = call <vscale x 8 x float> @llvm.riscv.vfmul.mask.nxv8f32.f32(926 <vscale x 8 x float> %0,927 <vscale x 8 x float> %1,928 float %2,929 <vscale x 8 x i1> %3,930 iXLen 0, iXLen %4, iXLen 1)931 932 ret <vscale x 8 x float> %a933}934 935define <vscale x 16 x float> @intrinsic_vfmul_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, iXLen %2) nounwind {936; CHECK-LABEL: intrinsic_vfmul_vf_nxv16f32_nxv16f32_f32:937; CHECK: # %bb.0: # %entry938; CHECK-NEXT: fsrmi a1, 0939; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma940; CHECK-NEXT: vfmul.vf v8, v8, fa0941; CHECK-NEXT: fsrm a1942; CHECK-NEXT: ret943entry:944 %a = call <vscale x 16 x float> @llvm.riscv.vfmul.nxv16f32.f32(945 <vscale x 16 x float> poison,946 <vscale x 16 x float> %0,947 float %1,948 iXLen 0, iXLen %2)949 950 ret <vscale x 16 x float> %a951}952 953define <vscale x 16 x float> @intrinsic_vfmul_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {954; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16f32_nxv16f32_f32:955; CHECK: # %bb.0: # %entry956; CHECK-NEXT: fsrmi a1, 0957; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu958; CHECK-NEXT: vfmul.vf v8, v16, fa0, v0.t959; CHECK-NEXT: fsrm a1960; CHECK-NEXT: ret961entry:962 %a = call <vscale x 16 x float> @llvm.riscv.vfmul.mask.nxv16f32.f32(963 <vscale x 16 x float> %0,964 <vscale x 16 x float> %1,965 float %2,966 <vscale x 16 x i1> %3,967 iXLen 0, iXLen %4, iXLen 1)968 969 ret <vscale x 16 x float> %a970}971 972define <vscale x 1 x double> @intrinsic_vfmul_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {973; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f64_nxv1f64_f64:974; CHECK: # %bb.0: # %entry975; CHECK-NEXT: fsrmi a1, 0976; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma977; CHECK-NEXT: vfmul.vf v8, v8, fa0978; CHECK-NEXT: fsrm a1979; CHECK-NEXT: ret980entry:981 %a = call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.f64(982 <vscale x 1 x double> poison,983 <vscale x 1 x double> %0,984 double %1,985 iXLen 0, iXLen %2)986 987 ret <vscale x 1 x double> %a988}989 990define <vscale x 1 x double> @intrinsic_vfmul_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {991; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f64_nxv1f64_f64:992; CHECK: # %bb.0: # %entry993; CHECK-NEXT: fsrmi a1, 0994; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu995; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t996; CHECK-NEXT: fsrm a1997; CHECK-NEXT: ret998entry:999 %a = call <vscale x 1 x double> @llvm.riscv.vfmul.mask.nxv1f64.f64(1000 <vscale x 1 x double> %0,1001 <vscale x 1 x double> %1,1002 double %2,1003 <vscale x 1 x i1> %3,1004 iXLen 0, iXLen %4, iXLen 1)1005 1006 ret <vscale x 1 x double> %a1007}1008 1009define <vscale x 2 x double> @intrinsic_vfmul_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {1010; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f64_nxv2f64_f64:1011; CHECK: # %bb.0: # %entry1012; CHECK-NEXT: fsrmi a1, 01013; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1014; CHECK-NEXT: vfmul.vf v8, v8, fa01015; CHECK-NEXT: fsrm a11016; CHECK-NEXT: ret1017entry:1018 %a = call <vscale x 2 x double> @llvm.riscv.vfmul.nxv2f64.f64(1019 <vscale x 2 x double> poison,1020 <vscale x 2 x double> %0,1021 double %1,1022 iXLen 0, iXLen %2)1023 1024 ret <vscale x 2 x double> %a1025}1026 1027define <vscale x 2 x double> @intrinsic_vfmul_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1028; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f64_nxv2f64_f64:1029; CHECK: # %bb.0: # %entry1030; CHECK-NEXT: fsrmi a1, 01031; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu1032; CHECK-NEXT: vfmul.vf v8, v10, fa0, v0.t1033; CHECK-NEXT: fsrm a11034; CHECK-NEXT: ret1035entry:1036 %a = call <vscale x 2 x double> @llvm.riscv.vfmul.mask.nxv2f64.f64(1037 <vscale x 2 x double> %0,1038 <vscale x 2 x double> %1,1039 double %2,1040 <vscale x 2 x i1> %3,1041 iXLen 0, iXLen %4, iXLen 1)1042 1043 ret <vscale x 2 x double> %a1044}1045 1046define <vscale x 4 x double> @intrinsic_vfmul_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {1047; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f64_nxv4f64_f64:1048; CHECK: # %bb.0: # %entry1049; CHECK-NEXT: fsrmi a1, 01050; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1051; CHECK-NEXT: vfmul.vf v8, v8, fa01052; CHECK-NEXT: fsrm a11053; CHECK-NEXT: ret1054entry:1055 %a = call <vscale x 4 x double> @llvm.riscv.vfmul.nxv4f64.f64(1056 <vscale x 4 x double> poison,1057 <vscale x 4 x double> %0,1058 double %1,1059 iXLen 0, iXLen %2)1060 1061 ret <vscale x 4 x double> %a1062}1063 1064define <vscale x 4 x double> @intrinsic_vfmul_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1065; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f64_nxv4f64_f64:1066; CHECK: # %bb.0: # %entry1067; CHECK-NEXT: fsrmi a1, 01068; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu1069; CHECK-NEXT: vfmul.vf v8, v12, fa0, v0.t1070; CHECK-NEXT: fsrm a11071; CHECK-NEXT: ret1072entry:1073 %a = call <vscale x 4 x double> @llvm.riscv.vfmul.mask.nxv4f64.f64(1074 <vscale x 4 x double> %0,1075 <vscale x 4 x double> %1,1076 double %2,1077 <vscale x 4 x i1> %3,1078 iXLen 0, iXLen %4, iXLen 1)1079 1080 ret <vscale x 4 x double> %a1081}1082 1083define <vscale x 8 x double> @intrinsic_vfmul_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, iXLen %2) nounwind {1084; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f64_nxv8f64_f64:1085; CHECK: # %bb.0: # %entry1086; CHECK-NEXT: fsrmi a1, 01087; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1088; CHECK-NEXT: vfmul.vf v8, v8, fa01089; CHECK-NEXT: fsrm a11090; CHECK-NEXT: ret1091entry:1092 %a = call <vscale x 8 x double> @llvm.riscv.vfmul.nxv8f64.f64(1093 <vscale x 8 x double> poison,1094 <vscale x 8 x double> %0,1095 double %1,1096 iXLen 0, iXLen %2)1097 1098 ret <vscale x 8 x double> %a1099}1100 1101define <vscale x 8 x double> @intrinsic_vfmul_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1102; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f64_nxv8f64_f64:1103; CHECK: # %bb.0: # %entry1104; CHECK-NEXT: fsrmi a1, 01105; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu1106; CHECK-NEXT: vfmul.vf v8, v16, fa0, v0.t1107; CHECK-NEXT: fsrm a11108; CHECK-NEXT: ret1109entry:1110 %a = call <vscale x 8 x double> @llvm.riscv.vfmul.mask.nxv8f64.f64(1111 <vscale x 8 x double> %0,1112 <vscale x 8 x double> %1,1113 double %2,1114 <vscale x 8 x i1> %3,1115 iXLen 0, iXLen %4, iXLen 1)1116 1117 ret <vscale x 8 x double> %a1118}1119