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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+zvfh -target-abi lp64d -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+zvfh -target-abi ilp32d -verify-machineinstrs < %s | FileCheck %s4 5define half @intrinsic_vfmv.f.s_s_nxv1f16(<vscale x 1 x half> %0) nounwind {6; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f16:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma9; CHECK-NEXT: vfmv.f.s fa0, v810; CHECK-NEXT: ret11entry:12 %a = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0)13 ret half %a14}15 16define half @intrinsic_vfmv.f.s_s_nxv2f16(<vscale x 2 x half> %0) nounwind {17; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv2f16:18; CHECK: # %bb.0: # %entry19; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma20; CHECK-NEXT: vfmv.f.s fa0, v821; CHECK-NEXT: ret22entry:23 %a = call half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half> %0)24 ret half %a25}26 27define half @intrinsic_vfmv.f.s_s_nxv4f16(<vscale x 4 x half> %0) nounwind {28; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv4f16:29; CHECK: # %bb.0: # %entry30; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma31; CHECK-NEXT: vfmv.f.s fa0, v832; CHECK-NEXT: ret33entry:34 %a = call half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half> %0)35 ret half %a36}37 38define half @intrinsic_vfmv.f.s_s_nxv8f16(<vscale x 8 x half> %0) nounwind {39; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv8f16:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma42; CHECK-NEXT: vfmv.f.s fa0, v843; CHECK-NEXT: ret44entry:45 %a = call half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half> %0)46 ret half %a47}48 49define half @intrinsic_vfmv.f.s_s_nxv16f16(<vscale x 16 x half> %0) nounwind {50; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv16f16:51; CHECK: # %bb.0: # %entry52; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma53; CHECK-NEXT: vfmv.f.s fa0, v854; CHECK-NEXT: ret55entry:56 %a = call half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half> %0)57 ret half %a58}59 60define half @intrinsic_vfmv.f.s_s_nxv32f16(<vscale x 32 x half> %0) nounwind {61; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv32f16:62; CHECK: # %bb.0: # %entry63; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma64; CHECK-NEXT: vfmv.f.s fa0, v865; CHECK-NEXT: ret66entry:67 %a = call half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half> %0)68 ret half %a69}70 71define float @intrinsic_vfmv.f.s_s_nxv1f32(<vscale x 1 x float> %0) nounwind {72; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f32:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma75; CHECK-NEXT: vfmv.f.s fa0, v876; CHECK-NEXT: ret77entry:78 %a = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> %0)79 ret float %a80}81 82define float @intrinsic_vfmv.f.s_s_nxv2f32(<vscale x 2 x float> %0) nounwind {83; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv2f32:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma86; CHECK-NEXT: vfmv.f.s fa0, v887; CHECK-NEXT: ret88entry:89 %a = call float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float> %0)90 ret float %a91}92 93define float @intrinsic_vfmv.f.s_s_nxv4f32(<vscale x 4 x float> %0) nounwind {94; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv4f32:95; CHECK: # %bb.0: # %entry96; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma97; CHECK-NEXT: vfmv.f.s fa0, v898; CHECK-NEXT: ret99entry:100 %a = call float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float> %0)101 ret float %a102}103 104define float @intrinsic_vfmv.f.s_s_nxv8f32(<vscale x 8 x float> %0) nounwind {105; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv8f32:106; CHECK: # %bb.0: # %entry107; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma108; CHECK-NEXT: vfmv.f.s fa0, v8109; CHECK-NEXT: ret110entry:111 %a = call float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float> %0)112 ret float %a113}114 115define float @intrinsic_vfmv.f.s_s_nxv16f32(<vscale x 16 x float> %0) nounwind {116; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv16f32:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma119; CHECK-NEXT: vfmv.f.s fa0, v8120; CHECK-NEXT: ret121entry:122 %a = call float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float> %0)123 ret float %a124}125 126define double @intrinsic_vfmv.f.s_s_nxv1f64(<vscale x 1 x double> %0) nounwind {127; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f64:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma130; CHECK-NEXT: vfmv.f.s fa0, v8131; CHECK-NEXT: ret132entry:133 %a = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> %0)134 ret double %a135}136 137define double @intrinsic_vfmv.f.s_s_nxv2f64(<vscale x 2 x double> %0) nounwind {138; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv2f64:139; CHECK: # %bb.0: # %entry140; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma141; CHECK-NEXT: vfmv.f.s fa0, v8142; CHECK-NEXT: ret143entry:144 %a = call double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double> %0)145 ret double %a146}147 148define double @intrinsic_vfmv.f.s_s_nxv4f64(<vscale x 4 x double> %0) nounwind {149; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv4f64:150; CHECK: # %bb.0: # %entry151; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma152; CHECK-NEXT: vfmv.f.s fa0, v8153; CHECK-NEXT: ret154entry:155 %a = call double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double> %0)156 ret double %a157}158 159define double @intrinsic_vfmv.f.s_s_nxv8f64(<vscale x 8 x double> %0) nounwind {160; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv8f64:161; CHECK: # %bb.0: # %entry162; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma163; CHECK-NEXT: vfmv.f.s fa0, v8164; CHECK-NEXT: ret165entry:166 %a = call double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double> %0)167 ret double %a168}169