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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma11; CHECK-NEXT: vfmv.s.f v8, fa012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half> %0, half %1, iXLen %2)15 ret <vscale x 1 x half> %a16}17 18define <vscale x 2 x half> @intrinsic_vfmv.s.f_f_nxv2f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {19; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f16:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma22; CHECK-NEXT: vfmv.s.f v8, fa023; CHECK-NEXT: ret24entry:25 %a = call <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half> %0, half %1, iXLen %2)26 ret <vscale x 2 x half> %a27}28 29define <vscale x 4 x half> @intrinsic_vfmv.s.f_f_nxv4f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {30; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f16:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma33; CHECK-NEXT: vfmv.s.f v8, fa034; CHECK-NEXT: ret35entry:36 %a = call <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half> %0, half %1, iXLen %2)37 ret <vscale x 4 x half> %a38}39 40define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_nxv8f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f16:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma44; CHECK-NEXT: vfmv.s.f v8, fa045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half> %0, half %1, iXLen %2)48 ret <vscale x 8 x half> %a49}50 51define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_nxv16f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {52; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f16:53; CHECK: # %bb.0: # %entry54; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma55; CHECK-NEXT: vfmv.s.f v8, fa056; CHECK-NEXT: ret57entry:58 %a = call <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half> %0, half %1, iXLen %2)59 ret <vscale x 16 x half> %a60}61 62define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_nxv32f16(<vscale x 32 x half> %0, half %1, iXLen %2) nounwind {63; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv32f16:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma66; CHECK-NEXT: vfmv.s.f v8, fa067; CHECK-NEXT: ret68entry:69 %a = call <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half> %0, half %1, iXLen %2)70 ret <vscale x 32 x half> %a71}72 73define <vscale x 1 x float> @intrinsic_vfmv.s.f_f_nxv1f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f32:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma77; CHECK-NEXT: vfmv.s.f v8, fa078; CHECK-NEXT: ret79entry:80 %a = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float> %0, float %1, iXLen %2)81 ret <vscale x 1 x float> %a82}83 84define <vscale x 2 x float> @intrinsic_vfmv.s.f_f_nxv2f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {85; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f32:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma88; CHECK-NEXT: vfmv.s.f v8, fa089; CHECK-NEXT: ret90entry:91 %a = call <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32(<vscale x 2 x float> %0, float %1, iXLen %2)92 ret <vscale x 2 x float> %a93}94 95define <vscale x 4 x float> @intrinsic_vfmv.s.f_f_nxv4f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {96; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f32:97; CHECK: # %bb.0: # %entry98; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma99; CHECK-NEXT: vfmv.s.f v8, fa0100; CHECK-NEXT: ret101entry:102 %a = call <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float> %0, float %1, iXLen %2)103 ret <vscale x 4 x float> %a104}105 106define <vscale x 8 x float> @intrinsic_vfmv.s.f_f_nxv8f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f32:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma110; CHECK-NEXT: vfmv.s.f v8, fa0111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float> %0, float %1, iXLen %2)114 ret <vscale x 8 x float> %a115}116 117define <vscale x 16 x float> @intrinsic_vfmv.s.f_f_nxv16f32(<vscale x 16 x float> %0, float %1, iXLen %2) nounwind {118; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f32:119; CHECK: # %bb.0: # %entry120; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma121; CHECK-NEXT: vfmv.s.f v8, fa0122; CHECK-NEXT: ret123entry:124 %a = call <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float> %0, float %1, iXLen %2)125 ret <vscale x 16 x float> %a126}127 128define <vscale x 1 x double> @intrinsic_vfmv.s.f_f_nxv1f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {129; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f64:130; CHECK: # %bb.0: # %entry131; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma132; CHECK-NEXT: vfmv.s.f v8, fa0133; CHECK-NEXT: ret134entry:135 %a = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double> %0, double %1, iXLen %2)136 ret <vscale x 1 x double> %a137}138 139define <vscale x 2 x double> @intrinsic_vfmv.s.f_f_nxv2f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f64:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma143; CHECK-NEXT: vfmv.s.f v8, fa0144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double> %0, double %1, iXLen %2)147 ret <vscale x 2 x double> %a148}149 150define <vscale x 4 x double> @intrinsic_vfmv.s.f_f_nxv4f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {151; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f64:152; CHECK: # %bb.0: # %entry153; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma154; CHECK-NEXT: vfmv.s.f v8, fa0155; CHECK-NEXT: ret156entry:157 %a = call <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double> %0, double %1, iXLen %2)158 ret <vscale x 4 x double> %a159}160 161define <vscale x 8 x double> @intrinsic_vfmv.s.f_f_nxv8f64(<vscale x 8 x double> %0, double %1, iXLen %2) nounwind {162; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f64:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma165; CHECK-NEXT: vfmv.s.f v8, fa0166; CHECK-NEXT: ret167entry:168 %a = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> %0, double %1, iXLen %2)169 ret <vscale x 8 x double> %a170}171 172define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_zero_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {173; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv1f16:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma176; CHECK-NEXT: vmv.s.x v8, zero177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half> %0, half 0.0, iXLen %1)180 ret <vscale x 1 x half> %a181}182 183define <vscale x 2 x half> @intrinsic_vfmv.s.f_f_zero_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {184; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv2f16:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma187; CHECK-NEXT: vmv.s.x v8, zero188; CHECK-NEXT: ret189entry:190 %a = call <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half> %0, half 0.0, iXLen %1)191 ret <vscale x 2 x half> %a192}193 194define <vscale x 4 x half> @intrinsic_vfmv.s.f_f_zero_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {195; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv4f16:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma198; CHECK-NEXT: vmv.s.x v8, zero199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half> %0, half 0.0, iXLen %1)202 ret <vscale x 4 x half> %a203}204 205define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_zero_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {206; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv8f16:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma209; CHECK-NEXT: vmv.s.x v8, zero210; CHECK-NEXT: ret211entry:212 %a = call <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half> %0, half 0.0, iXLen %1)213 ret <vscale x 8 x half> %a214}215 216define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_zero_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {217; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv16f16:218; CHECK: # %bb.0: # %entry219; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma220; CHECK-NEXT: vmv.s.x v8, zero221; CHECK-NEXT: ret222entry:223 %a = call <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half> %0, half 0.0, iXLen %1)224 ret <vscale x 16 x half> %a225}226 227define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_zero_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {228; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv32f16:229; CHECK: # %bb.0: # %entry230; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma231; CHECK-NEXT: vmv.s.x v8, zero232; CHECK-NEXT: ret233entry:234 %a = call <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half> %0, half 0.0, iXLen %1)235 ret <vscale x 32 x half> %a236}237 238define <vscale x 1 x float> @intrinsic_vfmv.s.f_f_zero_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {239; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv1f32:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma242; CHECK-NEXT: vmv.s.x v8, zero243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float> %0, float 0.0, iXLen %1)246 ret <vscale x 1 x float> %a247}248 249define <vscale x 2 x float> @intrinsic_vfmv.s.f_f_zero_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {250; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv2f32:251; CHECK: # %bb.0: # %entry252; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma253; CHECK-NEXT: vmv.s.x v8, zero254; CHECK-NEXT: ret255entry:256 %a = call <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32(<vscale x 2 x float> %0, float 0.0, iXLen %1)257 ret <vscale x 2 x float> %a258}259 260define <vscale x 4 x float> @intrinsic_vfmv.s.f_f_zero_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {261; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv4f32:262; CHECK: # %bb.0: # %entry263; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma264; CHECK-NEXT: vmv.s.x v8, zero265; CHECK-NEXT: ret266entry:267 %a = call <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float> %0, float 0.0, iXLen %1)268 ret <vscale x 4 x float> %a269}270 271define <vscale x 8 x float> @intrinsic_vfmv.s.f_f_zero_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {272; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv8f32:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma275; CHECK-NEXT: vmv.s.x v8, zero276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float> %0, float 0.0, iXLen %1)279 ret <vscale x 8 x float> %a280}281 282define <vscale x 16 x float> @intrinsic_vfmv.s.f_f_zero_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {283; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv16f32:284; CHECK: # %bb.0: # %entry285; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma286; CHECK-NEXT: vmv.s.x v8, zero287; CHECK-NEXT: ret288entry:289 %a = call <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float> %0, float 0.0, iXLen %1)290 ret <vscale x 16 x float> %a291}292 293define <vscale x 1 x double> @intrinsic_vfmv.s.f_f_zero_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {294; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv1f64:295; CHECK: # %bb.0: # %entry296; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma297; CHECK-NEXT: vmv.s.x v8, zero298; CHECK-NEXT: ret299entry:300 %a = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double> %0, double 0.0, iXLen %1)301 ret <vscale x 1 x double> %a302}303 304define <vscale x 2 x double> @intrinsic_vfmv.s.f_f_zero_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {305; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv2f64:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma308; CHECK-NEXT: vmv.s.x v8, zero309; CHECK-NEXT: ret310entry:311 %a = call <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double> %0, double 0.0, iXLen %1)312 ret <vscale x 2 x double> %a313}314 315define <vscale x 4 x double> @intrinsic_vfmv.s.f_f_zero_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {316; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv4f64:317; CHECK: # %bb.0: # %entry318; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma319; CHECK-NEXT: vmv.s.x v8, zero320; CHECK-NEXT: ret321entry:322 %a = call <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double> %0, double 0.0, iXLen %1)323 ret <vscale x 4 x double> %a324}325 326define <vscale x 8 x double> @intrinsic_vfmv.s.f_f_zero_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {327; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv8f64:328; CHECK: # %bb.0: # %entry329; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma330; CHECK-NEXT: vmv.s.x v8, zero331; CHECK-NEXT: ret332entry:333 %a = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> %0, double 0.0, iXLen %1)334 ret <vscale x 8 x double> %a335}336 337define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16_negzero(<vscale x 1 x half> %0, iXLen %1) nounwind {338; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16_negzero:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: lui a1, 1048568341; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma342; CHECK-NEXT: vmv.s.x v8, a1343; CHECK-NEXT: ret344entry:345 %a = call <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half> %0, half -0.0, iXLen %1)346 ret <vscale x 1 x half> %a347}348 349define <vscale x 1 x float> @intrinsic_vfmv.s.f_f_nxv1f32_negzero(<vscale x 1 x float> %0, iXLen %1) nounwind {350; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f32_negzero:351; CHECK: # %bb.0: # %entry352; CHECK-NEXT: lui a1, 524288353; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma354; CHECK-NEXT: vmv.s.x v8, a1355; CHECK-NEXT: ret356entry:357 %a = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float> %0, float -0.0, iXLen %1)358 ret <vscale x 1 x float> %a359}360 361define <vscale x 1 x double> @intrinsic_vfmv.s.f_f_nxv1f64_negzero(<vscale x 1 x double> %0, iXLen %1) nounwind {362; RV32-LABEL: intrinsic_vfmv.s.f_f_nxv1f64_negzero:363; RV32: # %bb.0: # %entry364; RV32-NEXT: fcvt.d.w fa5, zero365; RV32-NEXT: fneg.d fa5, fa5366; RV32-NEXT: vsetvli zero, a0, e64, m1, tu, ma367; RV32-NEXT: vfmv.s.f v8, fa5368; RV32-NEXT: ret369;370; RV64-LABEL: intrinsic_vfmv.s.f_f_nxv1f64_negzero:371; RV64: # %bb.0: # %entry372; RV64-NEXT: li a1, -1373; RV64-NEXT: slli a1, a1, 63374; RV64-NEXT: vsetvli zero, a0, e64, m1, tu, ma375; RV64-NEXT: vmv.s.x v8, a1376; RV64-NEXT: ret377entry:378 %a = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double> %0, double -0.0, iXLen %1)379 ret <vscale x 1 x double> %a380}381