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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x half> @intrinsic_vfmv.v.f_f_nxv1f16(half %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vfmv.v.f v8, fa012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(15 <vscale x 1 x half> poison,16 half %0,17 iXLen %1)18 19 ret <vscale x 1 x half> %a20}21 22define <vscale x 2 x half> @intrinsic_vfmv.v.f_f_nxv2f16(half %0, iXLen %1) nounwind {23; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma26; CHECK-NEXT: vfmv.v.f v8, fa027; CHECK-NEXT: ret28entry:29 %a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16(30 <vscale x 2 x half> poison,31 half %0,32 iXLen %1)33 34 ret <vscale x 2 x half> %a35}36 37define <vscale x 4 x half> @intrinsic_vfmv.v.f_f_nxv4f16(half %0, iXLen %1) nounwind {38; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma41; CHECK-NEXT: vfmv.v.f v8, fa042; CHECK-NEXT: ret43entry:44 %a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16(45 <vscale x 4 x half> poison,46 half %0,47 iXLen %1)48 49 ret <vscale x 4 x half> %a50}51 52define <vscale x 8 x half> @intrinsic_vfmv.v.f_f_nxv8f16(half %0, iXLen %1) nounwind {53; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma56; CHECK-NEXT: vfmv.v.f v8, fa057; CHECK-NEXT: ret58entry:59 %a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16(60 <vscale x 8 x half> poison,61 half %0,62 iXLen %1)63 64 ret <vscale x 8 x half> %a65}66 67define <vscale x 16 x half> @intrinsic_vfmv.v.f_f_nxv16f16(half %0, iXLen %1) nounwind {68; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma71; CHECK-NEXT: vfmv.v.f v8, fa072; CHECK-NEXT: ret73entry:74 %a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16(75 <vscale x 16 x half> poison,76 half %0,77 iXLen %1)78 79 ret <vscale x 16 x half> %a80}81 82define <vscale x 32 x half> @intrinsic_vfmv.v.f_f_nxv32f16(half %0, iXLen %1) nounwind {83; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma86; CHECK-NEXT: vfmv.v.f v8, fa087; CHECK-NEXT: ret88entry:89 %a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16(90 <vscale x 32 x half> poison,91 half %0,92 iXLen %1)93 94 ret <vscale x 32 x half> %a95}96 97define <vscale x 1 x float> @intrinsic_vfmv.v.f_f_nxv1f32(float %0, iXLen %1) nounwind {98; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f32:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma101; CHECK-NEXT: vfmv.v.f v8, fa0102; CHECK-NEXT: ret103entry:104 %a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(105 <vscale x 1 x float> poison,106 float %0,107 iXLen %1)108 109 ret <vscale x 1 x float> %a110}111 112define <vscale x 2 x float> @intrinsic_vfmv.v.f_f_nxv2f32(float %0, iXLen %1) nounwind {113; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f32:114; CHECK: # %bb.0: # %entry115; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma116; CHECK-NEXT: vfmv.v.f v8, fa0117; CHECK-NEXT: ret118entry:119 %a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32(120 <vscale x 2 x float> poison,121 float %0,122 iXLen %1)123 124 ret <vscale x 2 x float> %a125}126 127define <vscale x 4 x float> @intrinsic_vfmv.v.f_f_nxv4f32(float %0, iXLen %1) nounwind {128; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f32:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma131; CHECK-NEXT: vfmv.v.f v8, fa0132; CHECK-NEXT: ret133entry:134 %a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32(135 <vscale x 4 x float> poison,136 float %0,137 iXLen %1)138 139 ret <vscale x 4 x float> %a140}141 142define <vscale x 8 x float> @intrinsic_vfmv.v.f_f_nxv8f32(float %0, iXLen %1) nounwind {143; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f32:144; CHECK: # %bb.0: # %entry145; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma146; CHECK-NEXT: vfmv.v.f v8, fa0147; CHECK-NEXT: ret148entry:149 %a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32(150 <vscale x 8 x float> poison,151 float %0,152 iXLen %1)153 154 ret <vscale x 8 x float> %a155}156 157define <vscale x 16 x float> @intrinsic_vfmv.v.f_f_nxv16f32(float %0, iXLen %1) nounwind {158; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f32:159; CHECK: # %bb.0: # %entry160; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma161; CHECK-NEXT: vfmv.v.f v8, fa0162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32(165 <vscale x 16 x float> poison,166 float %0,167 iXLen %1)168 169 ret <vscale x 16 x float> %a170}171 172define <vscale x 1 x double> @intrinsic_vfmv.v.f_f_nxv1f64(double %0, iXLen %1) nounwind {173; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f64:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma176; CHECK-NEXT: vfmv.v.f v8, fa0177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(180 <vscale x 1 x double> poison,181 double %0,182 iXLen %1)183 184 ret <vscale x 1 x double> %a185}186 187define <vscale x 2 x double> @intrinsic_vfmv.v.f_f_nxv2f64(double %0, iXLen %1) nounwind {188; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f64:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma191; CHECK-NEXT: vfmv.v.f v8, fa0192; CHECK-NEXT: ret193entry:194 %a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64(195 <vscale x 2 x double> poison,196 double %0,197 iXLen %1)198 199 ret <vscale x 2 x double> %a200}201 202define <vscale x 4 x double> @intrinsic_vfmv.v.f_f_nxv4f64(double %0, iXLen %1) nounwind {203; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f64:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma206; CHECK-NEXT: vfmv.v.f v8, fa0207; CHECK-NEXT: ret208entry:209 %a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64(210 <vscale x 4 x double> poison,211 double %0,212 iXLen %1)213 214 ret <vscale x 4 x double> %a215}216 217define <vscale x 8 x double> @intrinsic_vfmv.v.f_f_nxv8f64(double %0, iXLen %1) nounwind {218; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f64:219; CHECK: # %bb.0: # %entry220; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma221; CHECK-NEXT: vfmv.v.f v8, fa0222; CHECK-NEXT: ret223entry:224 %a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64(225 <vscale x 8 x double> poison,226 double %0,227 iXLen %1)228 229 ret <vscale x 8 x double> %a230}231 232define <vscale x 1 x half> @intrinsic_vfmv.v.f_zero_nxv1f16(iXLen %0) nounwind {233; CHECK-LABEL: intrinsic_vfmv.v.f_zero_nxv1f16:234; CHECK: # %bb.0: # %entry235; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma236; CHECK-NEXT: vmv.v.i v8, 0237; CHECK-NEXT: ret238entry:239 %a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(240 <vscale x 1 x half> poison,241 half 0.0,242 iXLen %0)243 244 ret <vscale x 1 x half> %a245}246 247define <vscale x 2 x half> @intrinsic_vmv.v.i_zero_nxv2f16(iXLen %0) nounwind {248; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f16:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma251; CHECK-NEXT: vmv.v.i v8, 0252; CHECK-NEXT: ret253entry:254 %a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16(255 <vscale x 2 x half> poison,256 half 0.0,257 iXLen %0)258 259 ret <vscale x 2 x half> %a260}261 262define <vscale x 4 x half> @intrinsic_vmv.v.i_zero_nxv4f16(iXLen %0) nounwind {263; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f16:264; CHECK: # %bb.0: # %entry265; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma266; CHECK-NEXT: vmv.v.i v8, 0267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16(270 <vscale x 4 x half> poison,271 half 0.0,272 iXLen %0)273 274 ret <vscale x 4 x half> %a275}276 277define <vscale x 8 x half> @intrinsic_vmv.v.i_zero_nxv8f16(iXLen %0) nounwind {278; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f16:279; CHECK: # %bb.0: # %entry280; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma281; CHECK-NEXT: vmv.v.i v8, 0282; CHECK-NEXT: ret283entry:284 %a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16(285 <vscale x 8 x half> poison,286 half 0.0,287 iXLen %0)288 289 ret <vscale x 8 x half> %a290}291 292define <vscale x 16 x half> @intrinsic_vmv.v.i_zero_nxv16f16(iXLen %0) nounwind {293; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f16:294; CHECK: # %bb.0: # %entry295; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma296; CHECK-NEXT: vmv.v.i v8, 0297; CHECK-NEXT: ret298entry:299 %a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16(300 <vscale x 16 x half> poison,301 half 0.0,302 iXLen %0)303 304 ret <vscale x 16 x half> %a305}306 307define <vscale x 32 x half> @intrinsic_vmv.v.i_zero_nxv32f16(iXLen %0) nounwind {308; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv32f16:309; CHECK: # %bb.0: # %entry310; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma311; CHECK-NEXT: vmv.v.i v8, 0312; CHECK-NEXT: ret313entry:314 %a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16(315 <vscale x 32 x half> poison,316 half 0.0,317 iXLen %0)318 319 ret <vscale x 32 x half> %a320}321 322define <vscale x 1 x float> @intrinsic_vmv.v.i_zero_nxv1f32(iXLen %0) nounwind {323; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f32:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma326; CHECK-NEXT: vmv.v.i v8, 0327; CHECK-NEXT: ret328entry:329 %a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(330 <vscale x 1 x float> poison,331 float 0.0,332 iXLen %0)333 334 ret <vscale x 1 x float> %a335}336 337define <vscale x 2 x float> @intrinsic_vmv.v.i_zero_nxv2f32(iXLen %0) nounwind {338; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f32:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma341; CHECK-NEXT: vmv.v.i v8, 0342; CHECK-NEXT: ret343entry:344 %a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32(345 <vscale x 2 x float> poison,346 float 0.0,347 iXLen %0)348 349 ret <vscale x 2 x float> %a350}351 352define <vscale x 4 x float> @intrinsic_vmv.v.i_zero_nxv4f32(iXLen %0) nounwind {353; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f32:354; CHECK: # %bb.0: # %entry355; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma356; CHECK-NEXT: vmv.v.i v8, 0357; CHECK-NEXT: ret358entry:359 %a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32(360 <vscale x 4 x float> poison,361 float 0.0,362 iXLen %0)363 364 ret <vscale x 4 x float> %a365}366 367define <vscale x 8 x float> @intrinsic_vmv.v.i_zero_nxv8f32(iXLen %0) nounwind {368; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f32:369; CHECK: # %bb.0: # %entry370; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma371; CHECK-NEXT: vmv.v.i v8, 0372; CHECK-NEXT: ret373entry:374 %a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32(375 <vscale x 8 x float> poison,376 float 0.0,377 iXLen %0)378 379 ret <vscale x 8 x float> %a380}381 382define <vscale x 16 x float> @intrinsic_vmv.v.i_zero_nxv16f32(iXLen %0) nounwind {383; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f32:384; CHECK: # %bb.0: # %entry385; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma386; CHECK-NEXT: vmv.v.i v8, 0387; CHECK-NEXT: ret388entry:389 %a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32(390 <vscale x 16 x float> poison,391 float 0.0,392 iXLen %0)393 394 ret <vscale x 16 x float> %a395}396 397define <vscale x 1 x double> @intrinsic_vmv.v.i_zero_nxv1f64(iXLen %0) nounwind {398; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f64:399; CHECK: # %bb.0: # %entry400; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma401; CHECK-NEXT: vmv.v.i v8, 0402; CHECK-NEXT: ret403entry:404 %a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64(405 <vscale x 1 x double> poison,406 double 0.0,407 iXLen %0)408 409 ret <vscale x 1 x double> %a410}411 412define <vscale x 2 x double> @intrinsic_vmv.v.i_zero_nxv2f64(iXLen %0) nounwind {413; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f64:414; CHECK: # %bb.0: # %entry415; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma416; CHECK-NEXT: vmv.v.i v8, 0417; CHECK-NEXT: ret418entry:419 %a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64(420 <vscale x 2 x double> poison,421 double 0.0,422 iXLen %0)423 424 ret <vscale x 2 x double> %a425}426 427define <vscale x 4 x double> @intrinsic_vmv.v.i_zero_nxv4f64(iXLen %0) nounwind {428; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f64:429; CHECK: # %bb.0: # %entry430; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma431; CHECK-NEXT: vmv.v.i v8, 0432; CHECK-NEXT: ret433entry:434 %a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64(435 <vscale x 4 x double> poison,436 double 0.0,437 iXLen %0)438 439 ret <vscale x 4 x double> %a440}441 442define <vscale x 8 x double> @intrinsic_vmv.v.i_zero_nxv8f64(iXLen %0) nounwind {443; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f64:444; CHECK: # %bb.0: # %entry445; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma446; CHECK-NEXT: vmv.v.i v8, 0447; CHECK-NEXT: ret448entry:449 %a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64(450 <vscale x 8 x double> poison,451 double 0.0,452 iXLen %0)453 454 ret <vscale x 8 x double> %a455}456