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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin \7; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s8; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin \9; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s10 11define <vscale x 1 x half> @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {12; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: fsrmi a1, 015; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma16; CHECK-NEXT: vfncvt.f.f.w v9, v817; CHECK-NEXT: fsrm a118; CHECK-NEXT: vmv1r.v v8, v919; CHECK-NEXT: ret20entry:21 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32(22 <vscale x 1 x half> poison,23 <vscale x 1 x float> %0,24 iXLen 0, iXLen %1)25 26 ret <vscale x 1 x half> %a27}28 29define <vscale x 1 x half> @intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32(<vscale x 1 x half> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {30; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: fsrmi a1, 033; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu34; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t35; CHECK-NEXT: fsrm a136; CHECK-NEXT: ret37entry:38 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32(39 <vscale x 1 x half> %0,40 <vscale x 1 x float> %1,41 <vscale x 1 x i1> %2,42 iXLen 0, iXLen %3, iXLen 1)43 44 ret <vscale x 1 x half> %a45}46 47define <vscale x 2 x half> @intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {48; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32:49; CHECK: # %bb.0: # %entry50; CHECK-NEXT: fsrmi a1, 051; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma52; CHECK-NEXT: vfncvt.f.f.w v9, v853; CHECK-NEXT: fsrm a154; CHECK-NEXT: vmv1r.v v8, v955; CHECK-NEXT: ret56entry:57 %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32(58 <vscale x 2 x half> poison,59 <vscale x 2 x float> %0,60 iXLen 0, iXLen %1)61 62 ret <vscale x 2 x half> %a63}64 65define <vscale x 2 x half> @intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32(<vscale x 2 x half> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {66; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: fsrmi a1, 069; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu70; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t71; CHECK-NEXT: fsrm a172; CHECK-NEXT: ret73entry:74 %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32(75 <vscale x 2 x half> %0,76 <vscale x 2 x float> %1,77 <vscale x 2 x i1> %2,78 iXLen 0, iXLen %3, iXLen 1)79 80 ret <vscale x 2 x half> %a81}82 83define <vscale x 4 x half> @intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {84; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32:85; CHECK: # %bb.0: # %entry86; CHECK-NEXT: fsrmi a1, 087; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma88; CHECK-NEXT: vfncvt.f.f.w v10, v889; CHECK-NEXT: fsrm a190; CHECK-NEXT: vmv.v.v v8, v1091; CHECK-NEXT: ret92entry:93 %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32(94 <vscale x 4 x half> poison,95 <vscale x 4 x float> %0,96 iXLen 0, iXLen %1)97 98 ret <vscale x 4 x half> %a99}100 101define <vscale x 4 x half> @intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32(<vscale x 4 x half> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {102; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32:103; CHECK: # %bb.0: # %entry104; CHECK-NEXT: fsrmi a1, 0105; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu106; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t107; CHECK-NEXT: fsrm a1108; CHECK-NEXT: ret109entry:110 %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv4f16.nxv4f32(111 <vscale x 4 x half> %0,112 <vscale x 4 x float> %1,113 <vscale x 4 x i1> %2,114 iXLen 0, iXLen %3, iXLen 1)115 116 ret <vscale x 4 x half> %a117}118 119define <vscale x 8 x half> @intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {120; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: fsrmi a1, 0123; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma124; CHECK-NEXT: vfncvt.f.f.w v12, v8125; CHECK-NEXT: fsrm a1126; CHECK-NEXT: vmv.v.v v8, v12127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32(130 <vscale x 8 x half> poison,131 <vscale x 8 x float> %0,132 iXLen 0, iXLen %1)133 134 ret <vscale x 8 x half> %a135}136 137define <vscale x 8 x half> @intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32(<vscale x 8 x half> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {138; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32:139; CHECK: # %bb.0: # %entry140; CHECK-NEXT: fsrmi a1, 0141; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu142; CHECK-NEXT: vfncvt.f.f.w v8, v12, v0.t143; CHECK-NEXT: fsrm a1144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv8f16.nxv8f32(147 <vscale x 8 x half> %0,148 <vscale x 8 x float> %1,149 <vscale x 8 x i1> %2,150 iXLen 0, iXLen %3, iXLen 1)151 152 ret <vscale x 8 x half> %a153}154 155define <vscale x 16 x half> @intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {156; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: fsrmi a1, 0159; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma160; CHECK-NEXT: vfncvt.f.f.w v16, v8161; CHECK-NEXT: fsrm a1162; CHECK-NEXT: vmv.v.v v8, v16163; CHECK-NEXT: ret164entry:165 %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32(166 <vscale x 16 x half> poison,167 <vscale x 16 x float> %0,168 iXLen 0, iXLen %1)169 170 ret <vscale x 16 x half> %a171}172 173define <vscale x 16 x half> @intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32(<vscale x 16 x half> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {174; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: fsrmi a1, 0177; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu178; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t179; CHECK-NEXT: fsrm a1180; CHECK-NEXT: ret181entry:182 %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv16f16.nxv16f32(183 <vscale x 16 x half> %0,184 <vscale x 16 x float> %1,185 <vscale x 16 x i1> %2,186 iXLen 0, iXLen %3, iXLen 1)187 188 ret <vscale x 16 x half> %a189}190 191define <vscale x 1 x float> @intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {192; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64:193; CHECK: # %bb.0: # %entry194; CHECK-NEXT: fsrmi a1, 0195; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma196; CHECK-NEXT: vfncvt.f.f.w v9, v8197; CHECK-NEXT: fsrm a1198; CHECK-NEXT: vmv1r.v v8, v9199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64(202 <vscale x 1 x float> poison,203 <vscale x 1 x double> %0,204 iXLen 0, iXLen %1)205 206 ret <vscale x 1 x float> %a207}208 209define <vscale x 1 x float> @intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {210; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64:211; CHECK: # %bb.0: # %entry212; CHECK-NEXT: fsrmi a1, 0213; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu214; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t215; CHECK-NEXT: fsrm a1216; CHECK-NEXT: ret217entry:218 %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f32.nxv1f64(219 <vscale x 1 x float> %0,220 <vscale x 1 x double> %1,221 <vscale x 1 x i1> %2,222 iXLen 0, iXLen %3, iXLen 1)223 224 ret <vscale x 1 x float> %a225}226 227define <vscale x 2 x float> @intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {228; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64:229; CHECK: # %bb.0: # %entry230; CHECK-NEXT: fsrmi a1, 0231; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma232; CHECK-NEXT: vfncvt.f.f.w v10, v8233; CHECK-NEXT: fsrm a1234; CHECK-NEXT: vmv.v.v v8, v10235; CHECK-NEXT: ret236entry:237 %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64(238 <vscale x 2 x float> poison,239 <vscale x 2 x double> %0,240 iXLen 0, iXLen %1)241 242 ret <vscale x 2 x float> %a243}244 245define <vscale x 2 x float> @intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {246; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64:247; CHECK: # %bb.0: # %entry248; CHECK-NEXT: fsrmi a1, 0249; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu250; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t251; CHECK-NEXT: fsrm a1252; CHECK-NEXT: ret253entry:254 %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f32.nxv2f64(255 <vscale x 2 x float> %0,256 <vscale x 2 x double> %1,257 <vscale x 2 x i1> %2,258 iXLen 0, iXLen %3, iXLen 1)259 260 ret <vscale x 2 x float> %a261}262 263define <vscale x 4 x float> @intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {264; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64:265; CHECK: # %bb.0: # %entry266; CHECK-NEXT: fsrmi a1, 0267; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma268; CHECK-NEXT: vfncvt.f.f.w v12, v8269; CHECK-NEXT: fsrm a1270; CHECK-NEXT: vmv.v.v v8, v12271; CHECK-NEXT: ret272entry:273 %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64(274 <vscale x 4 x float> poison,275 <vscale x 4 x double> %0,276 iXLen 0, iXLen %1)277 278 ret <vscale x 4 x float> %a279}280 281define <vscale x 4 x float> @intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {282; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64:283; CHECK: # %bb.0: # %entry284; CHECK-NEXT: fsrmi a1, 0285; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu286; CHECK-NEXT: vfncvt.f.f.w v8, v12, v0.t287; CHECK-NEXT: fsrm a1288; CHECK-NEXT: ret289entry:290 %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv4f32.nxv4f64(291 <vscale x 4 x float> %0,292 <vscale x 4 x double> %1,293 <vscale x 4 x i1> %2,294 iXLen 0, iXLen %3, iXLen 1)295 296 ret <vscale x 4 x float> %a297}298 299define <vscale x 8 x float> @intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {300; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64:301; CHECK: # %bb.0: # %entry302; CHECK-NEXT: fsrmi a1, 0303; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma304; CHECK-NEXT: vfncvt.f.f.w v16, v8305; CHECK-NEXT: fsrm a1306; CHECK-NEXT: vmv.v.v v8, v16307; CHECK-NEXT: ret308entry:309 %a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64(310 <vscale x 8 x float> poison,311 <vscale x 8 x double> %0,312 iXLen 0, iXLen %1)313 314 ret <vscale x 8 x float> %a315}316 317define <vscale x 8 x float> @intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {318; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64:319; CHECK: # %bb.0: # %entry320; CHECK-NEXT: fsrmi a1, 0321; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu322; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t323; CHECK-NEXT: fsrm a1324; CHECK-NEXT: ret325entry:326 %a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv8f32.nxv8f64(327 <vscale x 8 x float> %0,328 <vscale x 8 x double> %1,329 <vscale x 8 x i1> %2,330 iXLen 0, iXLen %3, iXLen 1)331 332 ret <vscale x 8 x float> %a333}334