330 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x half> @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma12; CHECK-NEXT: vfncvt.f.xu.w v9, v813; CHECK-NEXT: fsrm a114; CHECK-NEXT: vmv1r.v v8, v915; CHECK-NEXT: ret16entry:17 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32(18 <vscale x 1 x half> poison,19 <vscale x 1 x i32> %0,20 iXLen 0, iXLen %1)21 22 ret <vscale x 1 x half> %a23}24 25define <vscale x 1 x half> @intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {26; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: fsrmi a1, 029; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu30; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t31; CHECK-NEXT: fsrm a132; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32(35 <vscale x 1 x half> %0,36 <vscale x 1 x i32> %1,37 <vscale x 1 x i1> %2,38 iXLen 0, iXLen %3, iXLen 1)39 40 ret <vscale x 1 x half> %a41}42 43define <vscale x 2 x half> @intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {44; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: fsrmi a1, 047; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma48; CHECK-NEXT: vfncvt.f.xu.w v9, v849; CHECK-NEXT: fsrm a150; CHECK-NEXT: vmv1r.v v8, v951; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32(54 <vscale x 2 x half> poison,55 <vscale x 2 x i32> %0,56 iXLen 0, iXLen %1)57 58 ret <vscale x 2 x half> %a59}60 61define <vscale x 2 x half> @intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32(<vscale x 2 x half> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {62; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: fsrmi a1, 065; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu66; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t67; CHECK-NEXT: fsrm a168; CHECK-NEXT: ret69entry:70 %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32(71 <vscale x 2 x half> %0,72 <vscale x 2 x i32> %1,73 <vscale x 2 x i1> %2,74 iXLen 0, iXLen %3, iXLen 1)75 76 ret <vscale x 2 x half> %a77}78 79define <vscale x 4 x half> @intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {80; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: fsrmi a1, 083; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma84; CHECK-NEXT: vfncvt.f.xu.w v10, v885; CHECK-NEXT: fsrm a186; CHECK-NEXT: vmv.v.v v8, v1087; CHECK-NEXT: ret88entry:89 %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32(90 <vscale x 4 x half> poison,91 <vscale x 4 x i32> %0,92 iXLen 0, iXLen %1)93 94 ret <vscale x 4 x half> %a95}96 97define <vscale x 4 x half> @intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32(<vscale x 4 x half> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {98; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: fsrmi a1, 0101; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu102; CHECK-NEXT: vfncvt.f.xu.w v8, v10, v0.t103; CHECK-NEXT: fsrm a1104; CHECK-NEXT: ret105entry:106 %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32(107 <vscale x 4 x half> %0,108 <vscale x 4 x i32> %1,109 <vscale x 4 x i1> %2,110 iXLen 0, iXLen %3, iXLen 1)111 112 ret <vscale x 4 x half> %a113}114 115define <vscale x 8 x half> @intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {116; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: fsrmi a1, 0119; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma120; CHECK-NEXT: vfncvt.f.xu.w v12, v8121; CHECK-NEXT: fsrm a1122; CHECK-NEXT: vmv.v.v v8, v12123; CHECK-NEXT: ret124entry:125 %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32(126 <vscale x 8 x half> poison,127 <vscale x 8 x i32> %0,128 iXLen 0, iXLen %1)129 130 ret <vscale x 8 x half> %a131}132 133define <vscale x 8 x half> @intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32(<vscale x 8 x half> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {134; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32:135; CHECK: # %bb.0: # %entry136; CHECK-NEXT: fsrmi a1, 0137; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu138; CHECK-NEXT: vfncvt.f.xu.w v8, v12, v0.t139; CHECK-NEXT: fsrm a1140; CHECK-NEXT: ret141entry:142 %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32(143 <vscale x 8 x half> %0,144 <vscale x 8 x i32> %1,145 <vscale x 8 x i1> %2,146 iXLen 0, iXLen %3, iXLen 1)147 148 ret <vscale x 8 x half> %a149}150 151define <vscale x 16 x half> @intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {152; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: fsrmi a1, 0155; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma156; CHECK-NEXT: vfncvt.f.xu.w v16, v8157; CHECK-NEXT: fsrm a1158; CHECK-NEXT: vmv.v.v v8, v16159; CHECK-NEXT: ret160entry:161 %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32(162 <vscale x 16 x half> poison,163 <vscale x 16 x i32> %0,164 iXLen 0, iXLen %1)165 166 ret <vscale x 16 x half> %a167}168 169define <vscale x 16 x half> @intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32(<vscale x 16 x half> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {170; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32:171; CHECK: # %bb.0: # %entry172; CHECK-NEXT: fsrmi a1, 0173; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu174; CHECK-NEXT: vfncvt.f.xu.w v8, v16, v0.t175; CHECK-NEXT: fsrm a1176; CHECK-NEXT: ret177entry:178 %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32(179 <vscale x 16 x half> %0,180 <vscale x 16 x i32> %1,181 <vscale x 16 x i1> %2,182 iXLen 0, iXLen %3, iXLen 1)183 184 ret <vscale x 16 x half> %a185}186 187define <vscale x 1 x float> @intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {188; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: fsrmi a1, 0191; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma192; CHECK-NEXT: vfncvt.f.xu.w v9, v8193; CHECK-NEXT: fsrm a1194; CHECK-NEXT: vmv1r.v v8, v9195; CHECK-NEXT: ret196entry:197 %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64(198 <vscale x 1 x float> poison,199 <vscale x 1 x i64> %0,200 iXLen 0, iXLen %1)201 202 ret <vscale x 1 x float> %a203}204 205define <vscale x 1 x float> @intrinsic_vfncvt_mask_f.xu.w_nxv1f32_nxv1i64(<vscale x 1 x float> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {206; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f32_nxv1i64:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: fsrmi a1, 0209; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu210; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t211; CHECK-NEXT: fsrm a1212; CHECK-NEXT: ret213entry:214 %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64(215 <vscale x 1 x float> %0,216 <vscale x 1 x i64> %1,217 <vscale x 1 x i1> %2,218 iXLen 0, iXLen %3, iXLen 1)219 220 ret <vscale x 1 x float> %a221}222 223define <vscale x 2 x float> @intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {224; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64:225; CHECK: # %bb.0: # %entry226; CHECK-NEXT: fsrmi a1, 0227; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma228; CHECK-NEXT: vfncvt.f.xu.w v10, v8229; CHECK-NEXT: fsrm a1230; CHECK-NEXT: vmv.v.v v8, v10231; CHECK-NEXT: ret232entry:233 %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64(234 <vscale x 2 x float> poison,235 <vscale x 2 x i64> %0,236 iXLen 0, iXLen %1)237 238 ret <vscale x 2 x float> %a239}240 241define <vscale x 2 x float> @intrinsic_vfncvt_mask_f.xu.w_nxv2f32_nxv2i64(<vscale x 2 x float> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {242; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f32_nxv2i64:243; CHECK: # %bb.0: # %entry244; CHECK-NEXT: fsrmi a1, 0245; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu246; CHECK-NEXT: vfncvt.f.xu.w v8, v10, v0.t247; CHECK-NEXT: fsrm a1248; CHECK-NEXT: ret249entry:250 %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64(251 <vscale x 2 x float> %0,252 <vscale x 2 x i64> %1,253 <vscale x 2 x i1> %2,254 iXLen 0, iXLen %3, iXLen 1)255 256 ret <vscale x 2 x float> %a257}258 259define <vscale x 4 x float> @intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {260; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64:261; CHECK: # %bb.0: # %entry262; CHECK-NEXT: fsrmi a1, 0263; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma264; CHECK-NEXT: vfncvt.f.xu.w v12, v8265; CHECK-NEXT: fsrm a1266; CHECK-NEXT: vmv.v.v v8, v12267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64(270 <vscale x 4 x float> poison,271 <vscale x 4 x i64> %0,272 iXLen 0, iXLen %1)273 274 ret <vscale x 4 x float> %a275}276 277define <vscale x 4 x float> @intrinsic_vfncvt_mask_f.xu.w_nxv4f32_nxv4i64(<vscale x 4 x float> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {278; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f32_nxv4i64:279; CHECK: # %bb.0: # %entry280; CHECK-NEXT: fsrmi a1, 0281; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu282; CHECK-NEXT: vfncvt.f.xu.w v8, v12, v0.t283; CHECK-NEXT: fsrm a1284; CHECK-NEXT: ret285entry:286 %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64(287 <vscale x 4 x float> %0,288 <vscale x 4 x i64> %1,289 <vscale x 4 x i1> %2,290 iXLen 0, iXLen %3, iXLen 1)291 292 ret <vscale x 4 x float> %a293}294 295define <vscale x 8 x float> @intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {296; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64:297; CHECK: # %bb.0: # %entry298; CHECK-NEXT: fsrmi a1, 0299; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma300; CHECK-NEXT: vfncvt.f.xu.w v16, v8301; CHECK-NEXT: fsrm a1302; CHECK-NEXT: vmv.v.v v8, v16303; CHECK-NEXT: ret304entry:305 %a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64(306 <vscale x 8 x float> poison,307 <vscale x 8 x i64> %0,308 iXLen 0, iXLen %1)309 310 ret <vscale x 8 x float> %a311}312 313define <vscale x 8 x float> @intrinsic_vfncvt_mask_f.xu.w_nxv8f32_nxv8i64(<vscale x 8 x float> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {314; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f32_nxv8i64:315; CHECK: # %bb.0: # %entry316; CHECK-NEXT: fsrmi a1, 0317; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu318; CHECK-NEXT: vfncvt.f.xu.w v8, v16, v0.t319; CHECK-NEXT: fsrm a1320; CHECK-NEXT: ret321entry:322 %a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64(323 <vscale x 8 x float> %0,324 <vscale x 8 x i64> %1,325 <vscale x 8 x i1> %2,326 iXLen 0, iXLen %3, iXLen 1)327 328 ret <vscale x 8 x float> %a329}330