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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x half> @intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vfncvt.rod.f.f.w v9, v812; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32(16 <vscale x 1 x half> poison,17 <vscale x 1 x float> %0,18 iXLen %1)19 20 ret <vscale x 1 x half> %a21}22 23define <vscale x 1 x half> @intrinsic_vfncvt_mask_rod.f.f.w_nxv1f16_nxv1f32(<vscale x 1 x half> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {24; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv1f16_nxv1f32:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu27; CHECK-NEXT: vfncvt.rod.f.f.w v8, v9, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32(31 <vscale x 1 x half> %0,32 <vscale x 1 x float> %1,33 <vscale x 1 x i1> %2,34 iXLen %3, iXLen 1)35 36 ret <vscale x 1 x half> %a37}38 39define <vscale x 2 x half> @intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {40; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma43; CHECK-NEXT: vfncvt.rod.f.f.w v9, v844; CHECK-NEXT: vmv1r.v v8, v945; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32(48 <vscale x 2 x half> poison,49 <vscale x 2 x float> %0,50 iXLen %1)51 52 ret <vscale x 2 x half> %a53}54 55define <vscale x 2 x half> @intrinsic_vfncvt_mask_rod.f.f.w_nxv2f16_nxv2f32(<vscale x 2 x half> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {56; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv2f16_nxv2f32:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu59; CHECK-NEXT: vfncvt.rod.f.f.w v8, v9, v0.t60; CHECK-NEXT: ret61entry:62 %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32(63 <vscale x 2 x half> %0,64 <vscale x 2 x float> %1,65 <vscale x 2 x i1> %2,66 iXLen %3, iXLen 1)67 68 ret <vscale x 2 x half> %a69}70 71define <vscale x 4 x half> @intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {72; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma75; CHECK-NEXT: vfncvt.rod.f.f.w v10, v876; CHECK-NEXT: vmv.v.v v8, v1077; CHECK-NEXT: ret78entry:79 %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32(80 <vscale x 4 x half> poison,81 <vscale x 4 x float> %0,82 iXLen %1)83 84 ret <vscale x 4 x half> %a85}86 87define <vscale x 4 x half> @intrinsic_vfncvt_mask_rod.f.f.w_nxv4f16_nxv4f32(<vscale x 4 x half> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {88; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv4f16_nxv4f32:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu91; CHECK-NEXT: vfncvt.rod.f.f.w v8, v10, v0.t92; CHECK-NEXT: ret93entry:94 %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f16.nxv4f32(95 <vscale x 4 x half> %0,96 <vscale x 4 x float> %1,97 <vscale x 4 x i1> %2,98 iXLen %3, iXLen 1)99 100 ret <vscale x 4 x half> %a101}102 103define <vscale x 8 x half> @intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {104; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma107; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8108; CHECK-NEXT: vmv.v.v v8, v12109; CHECK-NEXT: ret110entry:111 %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32(112 <vscale x 8 x half> poison,113 <vscale x 8 x float> %0,114 iXLen %1)115 116 ret <vscale x 8 x half> %a117}118 119define <vscale x 8 x half> @intrinsic_vfncvt_mask_rod.f.f.w_nxv8f16_nxv8f32(<vscale x 8 x half> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {120; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv8f16_nxv8f32:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu123; CHECK-NEXT: vfncvt.rod.f.f.w v8, v12, v0.t124; CHECK-NEXT: ret125entry:126 %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8f16.nxv8f32(127 <vscale x 8 x half> %0,128 <vscale x 8 x float> %1,129 <vscale x 8 x i1> %2,130 iXLen %3, iXLen 1)131 132 ret <vscale x 8 x half> %a133}134 135define <vscale x 16 x half> @intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {136; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma139; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8140; CHECK-NEXT: vmv.v.v v8, v16141; CHECK-NEXT: ret142entry:143 %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32(144 <vscale x 16 x half> poison,145 <vscale x 16 x float> %0,146 iXLen %1)147 148 ret <vscale x 16 x half> %a149}150 151define <vscale x 16 x half> @intrinsic_vfncvt_mask_rod.f.f.w_nxv16f16_nxv16f32(<vscale x 16 x half> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {152; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv16f16_nxv16f32:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu155; CHECK-NEXT: vfncvt.rod.f.f.w v8, v16, v0.t156; CHECK-NEXT: ret157entry:158 %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16f16.nxv16f32(159 <vscale x 16 x half> %0,160 <vscale x 16 x float> %1,161 <vscale x 16 x i1> %2,162 iXLen %3, iXLen 1)163 164 ret <vscale x 16 x half> %a165}166 167define <vscale x 1 x float> @intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {168; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma171; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8172; CHECK-NEXT: vmv1r.v v8, v9173; CHECK-NEXT: ret174entry:175 %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64(176 <vscale x 1 x float> poison,177 <vscale x 1 x double> %0,178 iXLen %1)179 180 ret <vscale x 1 x float> %a181}182 183define <vscale x 1 x float> @intrinsic_vfncvt_mask_rod.f.f.w_nxv1f32_nxv1f64(<vscale x 1 x float> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {184; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv1f32_nxv1f64:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu187; CHECK-NEXT: vfncvt.rod.f.f.w v8, v9, v0.t188; CHECK-NEXT: ret189entry:190 %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f32.nxv1f64(191 <vscale x 1 x float> %0,192 <vscale x 1 x double> %1,193 <vscale x 1 x i1> %2,194 iXLen %3, iXLen 1)195 196 ret <vscale x 1 x float> %a197}198 199define <vscale x 2 x float> @intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {200; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64:201; CHECK: # %bb.0: # %entry202; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma203; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8204; CHECK-NEXT: vmv.v.v v8, v10205; CHECK-NEXT: ret206entry:207 %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64(208 <vscale x 2 x float> poison,209 <vscale x 2 x double> %0,210 iXLen %1)211 212 ret <vscale x 2 x float> %a213}214 215define <vscale x 2 x float> @intrinsic_vfncvt_mask_rod.f.f.w_nxv2f32_nxv2f64(<vscale x 2 x float> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {216; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv2f32_nxv2f64:217; CHECK: # %bb.0: # %entry218; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu219; CHECK-NEXT: vfncvt.rod.f.f.w v8, v10, v0.t220; CHECK-NEXT: ret221entry:222 %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f32.nxv2f64(223 <vscale x 2 x float> %0,224 <vscale x 2 x double> %1,225 <vscale x 2 x i1> %2,226 iXLen %3, iXLen 1)227 228 ret <vscale x 2 x float> %a229}230 231define <vscale x 4 x float> @intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {232; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64:233; CHECK: # %bb.0: # %entry234; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma235; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8236; CHECK-NEXT: vmv.v.v v8, v12237; CHECK-NEXT: ret238entry:239 %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64(240 <vscale x 4 x float> poison,241 <vscale x 4 x double> %0,242 iXLen %1)243 244 ret <vscale x 4 x float> %a245}246 247define <vscale x 4 x float> @intrinsic_vfncvt_mask_rod.f.f.w_nxv4f32_nxv4f64(<vscale x 4 x float> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {248; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv4f32_nxv4f64:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu251; CHECK-NEXT: vfncvt.rod.f.f.w v8, v12, v0.t252; CHECK-NEXT: ret253entry:254 %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f32.nxv4f64(255 <vscale x 4 x float> %0,256 <vscale x 4 x double> %1,257 <vscale x 4 x i1> %2,258 iXLen %3, iXLen 1)259 260 ret <vscale x 4 x float> %a261}262 263define <vscale x 8 x float> @intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {264; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64:265; CHECK: # %bb.0: # %entry266; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma267; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8268; CHECK-NEXT: vmv.v.v v8, v16269; CHECK-NEXT: ret270entry:271 %a = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64(272 <vscale x 8 x float> poison,273 <vscale x 8 x double> %0,274 iXLen %1)275 276 ret <vscale x 8 x float> %a277}278 279define <vscale x 8 x float> @intrinsic_vfncvt_mask_rod.f.f.w_nxv8f32_nxv8f64(<vscale x 8 x float> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {280; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv8f32_nxv8f64:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu283; CHECK-NEXT: vfncvt.rod.f.f.w v8, v16, v0.t284; CHECK-NEXT: ret285entry:286 %a = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8f32.nxv8f64(287 <vscale x 8 x float> %0,288 <vscale x 8 x double> %1,289 <vscale x 8 x i1> %2,290 iXLen %3, iXLen 1)291 292 ret <vscale x 8 x float> %a293}294