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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v812; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16(16 <vscale x 1 x i8> poison,17 <vscale x 1 x half> %0,18 iXLen %1)19 20 ret <vscale x 1 x i8> %a21}22 23define <vscale x 1 x i8> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i8_nxv1f16(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {24; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i8_nxv1f16:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu27; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i8.nxv1f16(31 <vscale x 1 x i8> %0,32 <vscale x 1 x half> %1,33 <vscale x 1 x i1> %2,34 iXLen %3, iXLen 1)35 36 ret <vscale x 1 x i8> %a37}38 39define <vscale x 2 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {40; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma43; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v844; CHECK-NEXT: vmv1r.v v8, v945; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16(48 <vscale x 2 x i8> poison,49 <vscale x 2 x half> %0,50 iXLen %1)51 52 ret <vscale x 2 x i8> %a53}54 55define <vscale x 2 x i8> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i8_nxv2f16(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {56; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i8_nxv2f16:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu59; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t60; CHECK-NEXT: ret61entry:62 %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i8.nxv2f16(63 <vscale x 2 x i8> %0,64 <vscale x 2 x half> %1,65 <vscale x 2 x i1> %2,66 iXLen %3, iXLen 1)67 68 ret <vscale x 2 x i8> %a69}70 71define <vscale x 4 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {72; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma75; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v876; CHECK-NEXT: vmv1r.v v8, v977; CHECK-NEXT: ret78entry:79 %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16(80 <vscale x 4 x i8> poison,81 <vscale x 4 x half> %0,82 iXLen %1)83 84 ret <vscale x 4 x i8> %a85}86 87define <vscale x 4 x i8> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i8_nxv4f16(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {88; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i8_nxv4f16:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu91; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t92; CHECK-NEXT: ret93entry:94 %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i8.nxv4f16(95 <vscale x 4 x i8> %0,96 <vscale x 4 x half> %1,97 <vscale x 4 x i1> %2,98 iXLen %3, iXLen 1)99 100 ret <vscale x 4 x i8> %a101}102 103define <vscale x 8 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {104; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma107; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8108; CHECK-NEXT: vmv.v.v v8, v10109; CHECK-NEXT: ret110entry:111 %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16(112 <vscale x 8 x i8> poison,113 <vscale x 8 x half> %0,114 iXLen %1)115 116 ret <vscale x 8 x i8> %a117}118 119define <vscale x 8 x i8> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i8_nxv8f16(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {120; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i8_nxv8f16:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu123; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10, v0.t124; CHECK-NEXT: ret125entry:126 %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i8.nxv8f16(127 <vscale x 8 x i8> %0,128 <vscale x 8 x half> %1,129 <vscale x 8 x i1> %2,130 iXLen %3, iXLen 1)131 132 ret <vscale x 8 x i8> %a133}134 135define <vscale x 16 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {136; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma139; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8140; CHECK-NEXT: vmv.v.v v8, v12141; CHECK-NEXT: ret142entry:143 %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16(144 <vscale x 16 x i8> poison,145 <vscale x 16 x half> %0,146 iXLen %1)147 148 ret <vscale x 16 x i8> %a149}150 151define <vscale x 16 x i8> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i8_nxv16f16(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {152; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i8_nxv16f16:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu155; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12, v0.t156; CHECK-NEXT: ret157entry:158 %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i8.nxv16f16(159 <vscale x 16 x i8> %0,160 <vscale x 16 x half> %1,161 <vscale x 16 x i1> %2,162 iXLen %3, iXLen 1)163 164 ret <vscale x 16 x i8> %a165}166 167define <vscale x 32 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {168; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma171; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8172; CHECK-NEXT: vmv.v.v v8, v16173; CHECK-NEXT: ret174entry:175 %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16(176 <vscale x 32 x i8> poison,177 <vscale x 32 x half> %0,178 iXLen %1)179 180 ret <vscale x 32 x i8> %a181}182 183define <vscale x 32 x i8> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv32i8_nxv32f16(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {184; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv32i8_nxv32f16:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu187; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t188; CHECK-NEXT: ret189entry:190 %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv32i8.nxv32f16(191 <vscale x 32 x i8> %0,192 <vscale x 32 x half> %1,193 <vscale x 32 x i1> %2,194 iXLen %3, iXLen 1)195 196 ret <vscale x 32 x i8> %a197}198 199define <vscale x 1 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {200; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32:201; CHECK: # %bb.0: # %entry202; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma203; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8204; CHECK-NEXT: vmv1r.v v8, v9205; CHECK-NEXT: ret206entry:207 %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32(208 <vscale x 1 x i16> poison,209 <vscale x 1 x float> %0,210 iXLen %1)211 212 ret <vscale x 1 x i16> %a213}214 215define <vscale x 1 x i16> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i16_nxv1f32(<vscale x 1 x i16> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {216; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i16_nxv1f32:217; CHECK: # %bb.0: # %entry218; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu219; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t220; CHECK-NEXT: ret221entry:222 %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i16.nxv1f32(223 <vscale x 1 x i16> %0,224 <vscale x 1 x float> %1,225 <vscale x 1 x i1> %2,226 iXLen %3, iXLen 1)227 228 ret <vscale x 1 x i16> %a229}230 231define <vscale x 2 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {232; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32:233; CHECK: # %bb.0: # %entry234; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma235; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8236; CHECK-NEXT: vmv1r.v v8, v9237; CHECK-NEXT: ret238entry:239 %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32(240 <vscale x 2 x i16> poison,241 <vscale x 2 x float> %0,242 iXLen %1)243 244 ret <vscale x 2 x i16> %a245}246 247define <vscale x 2 x i16> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i16_nxv2f32(<vscale x 2 x i16> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {248; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i16_nxv2f32:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu251; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t252; CHECK-NEXT: ret253entry:254 %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i16.nxv2f32(255 <vscale x 2 x i16> %0,256 <vscale x 2 x float> %1,257 <vscale x 2 x i1> %2,258 iXLen %3, iXLen 1)259 260 ret <vscale x 2 x i16> %a261}262 263define <vscale x 4 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {264; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32:265; CHECK: # %bb.0: # %entry266; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma267; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8268; CHECK-NEXT: vmv.v.v v8, v10269; CHECK-NEXT: ret270entry:271 %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32(272 <vscale x 4 x i16> poison,273 <vscale x 4 x float> %0,274 iXLen %1)275 276 ret <vscale x 4 x i16> %a277}278 279define <vscale x 4 x i16> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i16_nxv4f32(<vscale x 4 x i16> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {280; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i16_nxv4f32:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu283; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10, v0.t284; CHECK-NEXT: ret285entry:286 %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i16.nxv4f32(287 <vscale x 4 x i16> %0,288 <vscale x 4 x float> %1,289 <vscale x 4 x i1> %2,290 iXLen %3, iXLen 1)291 292 ret <vscale x 4 x i16> %a293}294 295define <vscale x 8 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {296; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32:297; CHECK: # %bb.0: # %entry298; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma299; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8300; CHECK-NEXT: vmv.v.v v8, v12301; CHECK-NEXT: ret302entry:303 %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32(304 <vscale x 8 x i16> poison,305 <vscale x 8 x float> %0,306 iXLen %1)307 308 ret <vscale x 8 x i16> %a309}310 311define <vscale x 8 x i16> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i16_nxv8f32(<vscale x 8 x i16> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {312; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i16_nxv8f32:313; CHECK: # %bb.0: # %entry314; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu315; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12, v0.t316; CHECK-NEXT: ret317entry:318 %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i16.nxv8f32(319 <vscale x 8 x i16> %0,320 <vscale x 8 x float> %1,321 <vscale x 8 x i1> %2,322 iXLen %3, iXLen 1)323 324 ret <vscale x 8 x i16> %a325}326 327define <vscale x 16 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {328; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32:329; CHECK: # %bb.0: # %entry330; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma331; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8332; CHECK-NEXT: vmv.v.v v8, v16333; CHECK-NEXT: ret334entry:335 %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32(336 <vscale x 16 x i16> poison,337 <vscale x 16 x float> %0,338 iXLen %1)339 340 ret <vscale x 16 x i16> %a341}342 343define <vscale x 16 x i16> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i16_nxv16f32(<vscale x 16 x i16> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {344; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i16_nxv16f32:345; CHECK: # %bb.0: # %entry346; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu347; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t348; CHECK-NEXT: ret349entry:350 %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i16.nxv16f32(351 <vscale x 16 x i16> %0,352 <vscale x 16 x float> %1,353 <vscale x 16 x i1> %2,354 iXLen %3, iXLen 1)355 356 ret <vscale x 16 x i16> %a357}358 359define <vscale x 1 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {360; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64:361; CHECK: # %bb.0: # %entry362; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma363; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8364; CHECK-NEXT: vmv1r.v v8, v9365; CHECK-NEXT: ret366entry:367 %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64(368 <vscale x 1 x i32> poison,369 <vscale x 1 x double> %0,370 iXLen %1)371 372 ret <vscale x 1 x i32> %a373}374 375define <vscale x 1 x i32> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i32_nxv1f64(<vscale x 1 x i32> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {376; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i32_nxv1f64:377; CHECK: # %bb.0: # %entry378; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu379; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t380; CHECK-NEXT: ret381entry:382 %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i32.nxv1f64(383 <vscale x 1 x i32> %0,384 <vscale x 1 x double> %1,385 <vscale x 1 x i1> %2,386 iXLen %3, iXLen 1)387 388 ret <vscale x 1 x i32> %a389}390 391define <vscale x 2 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {392; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64:393; CHECK: # %bb.0: # %entry394; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma395; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8396; CHECK-NEXT: vmv.v.v v8, v10397; CHECK-NEXT: ret398entry:399 %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64(400 <vscale x 2 x i32> poison,401 <vscale x 2 x double> %0,402 iXLen %1)403 404 ret <vscale x 2 x i32> %a405}406 407define <vscale x 2 x i32> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i32_nxv2f64(<vscale x 2 x i32> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {408; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i32_nxv2f64:409; CHECK: # %bb.0: # %entry410; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu411; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10, v0.t412; CHECK-NEXT: ret413entry:414 %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i32.nxv2f64(415 <vscale x 2 x i32> %0,416 <vscale x 2 x double> %1,417 <vscale x 2 x i1> %2,418 iXLen %3, iXLen 1)419 420 ret <vscale x 2 x i32> %a421}422 423define <vscale x 4 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {424; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64:425; CHECK: # %bb.0: # %entry426; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma427; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8428; CHECK-NEXT: vmv.v.v v8, v12429; CHECK-NEXT: ret430entry:431 %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64(432 <vscale x 4 x i32> poison,433 <vscale x 4 x double> %0,434 iXLen %1)435 436 ret <vscale x 4 x i32> %a437}438 439define <vscale x 4 x i32> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i32_nxv4f64(<vscale x 4 x i32> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {440; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i32_nxv4f64:441; CHECK: # %bb.0: # %entry442; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu443; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12, v0.t444; CHECK-NEXT: ret445entry:446 %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i32.nxv4f64(447 <vscale x 4 x i32> %0,448 <vscale x 4 x double> %1,449 <vscale x 4 x i1> %2,450 iXLen %3, iXLen 1)451 452 ret <vscale x 4 x i32> %a453}454 455define <vscale x 8 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {456; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64:457; CHECK: # %bb.0: # %entry458; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma459; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8460; CHECK-NEXT: vmv.v.v v8, v16461; CHECK-NEXT: ret462entry:463 %a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64(464 <vscale x 8 x i32> poison,465 <vscale x 8 x double> %0,466 iXLen %1)467 468 ret <vscale x 8 x i32> %a469}470 471define <vscale x 8 x i32> @intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i32_nxv8f64(<vscale x 8 x i32> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {472; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i32_nxv8f64:473; CHECK: # %bb.0: # %entry474; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu475; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i32.nxv8f64(479 <vscale x 8 x i32> %0,480 <vscale x 8 x double> %1,481 <vscale x 8 x i1> %2,482 iXLen %3, iXLen 1)483 484 ret <vscale x 8 x i32> %a485}486