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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8alt, mf8, ta, ma11; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v812; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16(16 <vscale x 1 x i8> poison,17 <vscale x 1 x bfloat> %0,18 iXLen %1)19 20 ret <vscale x 1 x i8> %a21}22 23define <vscale x 1 x i8> @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i8_nxv1bf16(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {24; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i8_nxv1bf16:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e8alt, mf8, ta, mu27; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i8.nxv1bf16(31 <vscale x 1 x i8> %0,32 <vscale x 1 x bfloat> %1,33 <vscale x 1 x i1> %2,34 iXLen %3, iXLen 1)35 36 ret <vscale x 1 x i8> %a37}38 39define <vscale x 2 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1) nounwind {40; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2bf16:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e8alt, mf4, ta, ma43; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v844; CHECK-NEXT: vmv1r.v v8, v945; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16(48 <vscale x 2 x i8> poison,49 <vscale x 2 x bfloat> %0,50 iXLen %1)51 52 ret <vscale x 2 x i8> %a53}54 55define <vscale x 2 x i8> @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i8_nxv2bf16(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {56; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i8_nxv2bf16:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a0, e8alt, mf4, ta, mu59; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t60; CHECK-NEXT: ret61entry:62 %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i8.nxv2bf16(63 <vscale x 2 x i8> %0,64 <vscale x 2 x bfloat> %1,65 <vscale x 2 x i1> %2,66 iXLen %3, iXLen 1)67 68 ret <vscale x 2 x i8> %a69}70 71define <vscale x 4 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1) nounwind {72; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4bf16:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a0, e8alt, mf2, ta, ma75; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v876; CHECK-NEXT: vmv1r.v v8, v977; CHECK-NEXT: ret78entry:79 %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16(80 <vscale x 4 x i8> poison,81 <vscale x 4 x bfloat> %0,82 iXLen %1)83 84 ret <vscale x 4 x i8> %a85}86 87define <vscale x 4 x i8> @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i8_nxv4bf16(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {88; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i8_nxv4bf16:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vsetvli zero, a0, e8alt, mf2, ta, mu91; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t92; CHECK-NEXT: ret93entry:94 %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i8.nxv4bf16(95 <vscale x 4 x i8> %0,96 <vscale x 4 x bfloat> %1,97 <vscale x 4 x i1> %2,98 iXLen %3, iXLen 1)99 100 ret <vscale x 4 x i8> %a101}102 103define <vscale x 8 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1) nounwind {104; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8bf16:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetvli zero, a0, e8alt, m1, ta, ma107; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8108; CHECK-NEXT: vmv.v.v v8, v10109; CHECK-NEXT: ret110entry:111 %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16(112 <vscale x 8 x i8> poison,113 <vscale x 8 x bfloat> %0,114 iXLen %1)115 116 ret <vscale x 8 x i8> %a117}118 119define <vscale x 8 x i8> @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i8_nxv8bf16(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {120; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i8_nxv8bf16:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: vsetvli zero, a0, e8alt, m1, ta, mu123; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10, v0.t124; CHECK-NEXT: ret125entry:126 %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i8.nxv8bf16(127 <vscale x 8 x i8> %0,128 <vscale x 8 x bfloat> %1,129 <vscale x 8 x i1> %2,130 iXLen %3, iXLen 1)131 132 ret <vscale x 8 x i8> %a133}134 135define <vscale x 16 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1) nounwind {136; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16bf16:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: vsetvli zero, a0, e8alt, m2, ta, ma139; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8140; CHECK-NEXT: vmv.v.v v8, v12141; CHECK-NEXT: ret142entry:143 %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16(144 <vscale x 16 x i8> poison,145 <vscale x 16 x bfloat> %0,146 iXLen %1)147 148 ret <vscale x 16 x i8> %a149}150 151define <vscale x 16 x i8> @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i8_nxv16bf16(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {152; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i8_nxv16bf16:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: vsetvli zero, a0, e8alt, m2, ta, mu155; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v12, v0.t156; CHECK-NEXT: ret157entry:158 %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv16i8.nxv16bf16(159 <vscale x 16 x i8> %0,160 <vscale x 16 x bfloat> %1,161 <vscale x 16 x i1> %2,162 iXLen %3, iXLen 1)163 164 ret <vscale x 16 x i8> %a165}166 167define <vscale x 32 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32bf16(<vscale x 32 x bfloat> %0, iXLen %1) nounwind {168; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32bf16:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: vsetvli zero, a0, e8alt, m4, ta, ma171; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8172; CHECK-NEXT: vmv.v.v v8, v16173; CHECK-NEXT: ret174entry:175 %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16(176 <vscale x 32 x i8> poison,177 <vscale x 32 x bfloat> %0,178 iXLen %1)179 180 ret <vscale x 32 x i8> %a181}182 183define <vscale x 32 x i8> @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv32i8_nxv32bf16(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {184; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv32i8_nxv32bf16:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: vsetvli zero, a0, e8alt, m4, ta, mu187; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16, v0.t188; CHECK-NEXT: ret189entry:190 %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv32i8.nxv32bf16(191 <vscale x 32 x i8> %0,192 <vscale x 32 x bfloat> %1,193 <vscale x 32 x i1> %2,194 iXLen %3, iXLen 1)195 196 ret <vscale x 32 x i8> %a197}198 199