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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e8alt, mf8, ta, ma12; CHECK-NEXT: vfncvt.x.f.w v9, v813; CHECK-NEXT: fsrm a114; CHECK-NEXT: vmv1r.v v8, v915; CHECK-NEXT: ret16entry:17 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16(18 <vscale x 1 x i8> poison,19 <vscale x 1 x bfloat> %0,20 iXLen 0, iXLen %1)21 22 ret <vscale x 1 x i8> %a23}24 25define <vscale x 1 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1bf16(<vscale x 1 x i8> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {26; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1bf16:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: fsrmi a1, 029; CHECK-NEXT: vsetvli zero, a0, e8alt, mf8, ta, mu30; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t31; CHECK-NEXT: fsrm a132; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1bf16(35 <vscale x 1 x i8> %0,36 <vscale x 1 x bfloat> %1,37 <vscale x 1 x i1> %2,38 iXLen 0, iXLen %3, iXLen 1)39 40 ret <vscale x 1 x i8> %a41}42 43define <vscale x 2 x i8> @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1) nounwind {44; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2bf16:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: fsrmi a1, 047; CHECK-NEXT: vsetvli zero, a0, e8alt, mf4, ta, ma48; CHECK-NEXT: vfncvt.x.f.w v9, v849; CHECK-NEXT: fsrm a150; CHECK-NEXT: vmv1r.v v8, v951; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16(54 <vscale x 2 x i8> poison,55 <vscale x 2 x bfloat> %0,56 iXLen 0, iXLen %1)57 58 ret <vscale x 2 x i8> %a59}60 61define <vscale x 2 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2bf16(<vscale x 2 x i8> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {62; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2bf16:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: fsrmi a1, 065; CHECK-NEXT: vsetvli zero, a0, e8alt, mf4, ta, mu66; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t67; CHECK-NEXT: fsrm a168; CHECK-NEXT: ret69entry:70 %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2bf16(71 <vscale x 2 x i8> %0,72 <vscale x 2 x bfloat> %1,73 <vscale x 2 x i1> %2,74 iXLen 0, iXLen %3, iXLen 1)75 76 ret <vscale x 2 x i8> %a77}78 79define <vscale x 4 x i8> @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1) nounwind {80; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4bf16:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: fsrmi a1, 083; CHECK-NEXT: vsetvli zero, a0, e8alt, mf2, ta, ma84; CHECK-NEXT: vfncvt.x.f.w v9, v885; CHECK-NEXT: fsrm a186; CHECK-NEXT: vmv1r.v v8, v987; CHECK-NEXT: ret88entry:89 %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16(90 <vscale x 4 x i8> poison,91 <vscale x 4 x bfloat> %0,92 iXLen 0, iXLen %1)93 94 ret <vscale x 4 x i8> %a95}96 97define <vscale x 4 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4bf16(<vscale x 4 x i8> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {98; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4bf16:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: fsrmi a1, 0101; CHECK-NEXT: vsetvli zero, a0, e8alt, mf2, ta, mu102; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t103; CHECK-NEXT: fsrm a1104; CHECK-NEXT: ret105entry:106 %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4bf16(107 <vscale x 4 x i8> %0,108 <vscale x 4 x bfloat> %1,109 <vscale x 4 x i1> %2,110 iXLen 0, iXLen %3, iXLen 1)111 112 ret <vscale x 4 x i8> %a113}114 115define <vscale x 8 x i8> @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1) nounwind {116; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8bf16:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: fsrmi a1, 0119; CHECK-NEXT: vsetvli zero, a0, e8alt, m1, ta, ma120; CHECK-NEXT: vfncvt.x.f.w v10, v8121; CHECK-NEXT: fsrm a1122; CHECK-NEXT: vmv.v.v v8, v10123; CHECK-NEXT: ret124entry:125 %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16(126 <vscale x 8 x i8> poison,127 <vscale x 8 x bfloat> %0,128 iXLen 0, iXLen %1)129 130 ret <vscale x 8 x i8> %a131}132 133define <vscale x 8 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8bf16(<vscale x 8 x i8> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {134; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8bf16:135; CHECK: # %bb.0: # %entry136; CHECK-NEXT: fsrmi a1, 0137; CHECK-NEXT: vsetvli zero, a0, e8alt, m1, ta, mu138; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t139; CHECK-NEXT: fsrm a1140; CHECK-NEXT: ret141entry:142 %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8bf16(143 <vscale x 8 x i8> %0,144 <vscale x 8 x bfloat> %1,145 <vscale x 8 x i1> %2,146 iXLen 0, iXLen %3, iXLen 1)147 148 ret <vscale x 8 x i8> %a149}150 151define <vscale x 16 x i8> @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1) nounwind {152; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16bf16:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: fsrmi a1, 0155; CHECK-NEXT: vsetvli zero, a0, e8alt, m2, ta, ma156; CHECK-NEXT: vfncvt.x.f.w v12, v8157; CHECK-NEXT: fsrm a1158; CHECK-NEXT: vmv.v.v v8, v12159; CHECK-NEXT: ret160entry:161 %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16(162 <vscale x 16 x i8> poison,163 <vscale x 16 x bfloat> %0,164 iXLen 0, iXLen %1)165 166 ret <vscale x 16 x i8> %a167}168 169define <vscale x 16 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16bf16(<vscale x 16 x i8> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {170; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16bf16:171; CHECK: # %bb.0: # %entry172; CHECK-NEXT: fsrmi a1, 0173; CHECK-NEXT: vsetvli zero, a0, e8alt, m2, ta, mu174; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t175; CHECK-NEXT: fsrm a1176; CHECK-NEXT: ret177entry:178 %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16bf16(179 <vscale x 16 x i8> %0,180 <vscale x 16 x bfloat> %1,181 <vscale x 16 x i1> %2,182 iXLen 0, iXLen %3, iXLen 1)183 184 ret <vscale x 16 x i8> %a185}186 187define <vscale x 32 x i8> @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32bf16(<vscale x 32 x bfloat> %0, iXLen %1) nounwind {188; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32bf16:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: fsrmi a1, 0191; CHECK-NEXT: vsetvli zero, a0, e8alt, m4, ta, ma192; CHECK-NEXT: vfncvt.x.f.w v16, v8193; CHECK-NEXT: fsrm a1194; CHECK-NEXT: vmv.v.v v8, v16195; CHECK-NEXT: ret196entry:197 %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16(198 <vscale x 32 x i8> poison,199 <vscale x 32 x bfloat> %0,200 iXLen 0, iXLen %1)201 202 ret <vscale x 32 x i8> %a203}204 205define <vscale x 32 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32bf16(<vscale x 32 x i8> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {206; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32bf16:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: fsrmi a1, 0209; CHECK-NEXT: vsetvli zero, a0, e8alt, m4, ta, mu210; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t211; CHECK-NEXT: fsrm a1212; CHECK-NEXT: ret213entry:214 %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32bf16(215 <vscale x 32 x i8> %0,216 <vscale x 32 x bfloat> %1,217 <vscale x 32 x i1> %2,218 iXLen 0, iXLen %3, iXLen 1)219 220 ret <vscale x 32 x i8> %a221}222 223