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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma12; CHECK-NEXT: vfncvt.x.f.w v9, v813; CHECK-NEXT: fsrm a114; CHECK-NEXT: vmv1r.v v8, v915; CHECK-NEXT: ret16entry:17 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16(18 <vscale x 1 x i8> poison,19 <vscale x 1 x half> %0,20 iXLen 0, iXLen %1)21 22 ret <vscale x 1 x i8> %a23}24 25define <vscale x 1 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {26; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: fsrmi a1, 029; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu30; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t31; CHECK-NEXT: fsrm a132; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16(35 <vscale x 1 x i8> %0,36 <vscale x 1 x half> %1,37 <vscale x 1 x i1> %2,38 iXLen 0, iXLen %3, iXLen 1)39 40 ret <vscale x 1 x i8> %a41}42 43define <vscale x 2 x i8> @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {44; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: fsrmi a1, 047; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma48; CHECK-NEXT: vfncvt.x.f.w v9, v849; CHECK-NEXT: fsrm a150; CHECK-NEXT: vmv1r.v v8, v951; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16(54 <vscale x 2 x i8> poison,55 <vscale x 2 x half> %0,56 iXLen 0, iXLen %1)57 58 ret <vscale x 2 x i8> %a59}60 61define <vscale x 2 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16(<vscale x 2 x i8> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {62; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: fsrmi a1, 065; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu66; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t67; CHECK-NEXT: fsrm a168; CHECK-NEXT: ret69entry:70 %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16(71 <vscale x 2 x i8> %0,72 <vscale x 2 x half> %1,73 <vscale x 2 x i1> %2,74 iXLen 0, iXLen %3, iXLen 1)75 76 ret <vscale x 2 x i8> %a77}78 79define <vscale x 4 x i8> @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {80; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: fsrmi a1, 083; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma84; CHECK-NEXT: vfncvt.x.f.w v9, v885; CHECK-NEXT: fsrm a186; CHECK-NEXT: vmv1r.v v8, v987; CHECK-NEXT: ret88entry:89 %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16(90 <vscale x 4 x i8> poison,91 <vscale x 4 x half> %0,92 iXLen 0, iXLen %1)93 94 ret <vscale x 4 x i8> %a95}96 97define <vscale x 4 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16(<vscale x 4 x i8> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {98; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: fsrmi a1, 0101; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu102; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t103; CHECK-NEXT: fsrm a1104; CHECK-NEXT: ret105entry:106 %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16(107 <vscale x 4 x i8> %0,108 <vscale x 4 x half> %1,109 <vscale x 4 x i1> %2,110 iXLen 0, iXLen %3, iXLen 1)111 112 ret <vscale x 4 x i8> %a113}114 115define <vscale x 8 x i8> @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {116; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: fsrmi a1, 0119; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma120; CHECK-NEXT: vfncvt.x.f.w v10, v8121; CHECK-NEXT: fsrm a1122; CHECK-NEXT: vmv.v.v v8, v10123; CHECK-NEXT: ret124entry:125 %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16(126 <vscale x 8 x i8> poison,127 <vscale x 8 x half> %0,128 iXLen 0, iXLen %1)129 130 ret <vscale x 8 x i8> %a131}132 133define <vscale x 8 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16(<vscale x 8 x i8> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {134; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16:135; CHECK: # %bb.0: # %entry136; CHECK-NEXT: fsrmi a1, 0137; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu138; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t139; CHECK-NEXT: fsrm a1140; CHECK-NEXT: ret141entry:142 %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16(143 <vscale x 8 x i8> %0,144 <vscale x 8 x half> %1,145 <vscale x 8 x i1> %2,146 iXLen 0, iXLen %3, iXLen 1)147 148 ret <vscale x 8 x i8> %a149}150 151define <vscale x 16 x i8> @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {152; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: fsrmi a1, 0155; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma156; CHECK-NEXT: vfncvt.x.f.w v12, v8157; CHECK-NEXT: fsrm a1158; CHECK-NEXT: vmv.v.v v8, v12159; CHECK-NEXT: ret160entry:161 %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16(162 <vscale x 16 x i8> poison,163 <vscale x 16 x half> %0,164 iXLen 0, iXLen %1)165 166 ret <vscale x 16 x i8> %a167}168 169define <vscale x 16 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16(<vscale x 16 x i8> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {170; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16:171; CHECK: # %bb.0: # %entry172; CHECK-NEXT: fsrmi a1, 0173; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu174; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t175; CHECK-NEXT: fsrm a1176; CHECK-NEXT: ret177entry:178 %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16(179 <vscale x 16 x i8> %0,180 <vscale x 16 x half> %1,181 <vscale x 16 x i1> %2,182 iXLen 0, iXLen %3, iXLen 1)183 184 ret <vscale x 16 x i8> %a185}186 187define <vscale x 32 x i8> @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {188; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: fsrmi a1, 0191; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma192; CHECK-NEXT: vfncvt.x.f.w v16, v8193; CHECK-NEXT: fsrm a1194; CHECK-NEXT: vmv.v.v v8, v16195; CHECK-NEXT: ret196entry:197 %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16(198 <vscale x 32 x i8> poison,199 <vscale x 32 x half> %0,200 iXLen 0, iXLen %1)201 202 ret <vscale x 32 x i8> %a203}204 205define <vscale x 32 x i8> @intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16(<vscale x 32 x i8> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {206; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: fsrmi a1, 0209; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu210; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t211; CHECK-NEXT: fsrm a1212; CHECK-NEXT: ret213entry:214 %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16(215 <vscale x 32 x i8> %0,216 <vscale x 32 x half> %1,217 <vscale x 32 x i1> %2,218 iXLen 0, iXLen %3, iXLen 1)219 220 ret <vscale x 32 x i8> %a221}222 223define <vscale x 1 x i16> @intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {224; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32:225; CHECK: # %bb.0: # %entry226; CHECK-NEXT: fsrmi a1, 0227; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma228; CHECK-NEXT: vfncvt.x.f.w v9, v8229; CHECK-NEXT: fsrm a1230; CHECK-NEXT: vmv1r.v v8, v9231; CHECK-NEXT: ret232entry:233 %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32(234 <vscale x 1 x i16> poison,235 <vscale x 1 x float> %0,236 iXLen 0, iXLen %1)237 238 ret <vscale x 1 x i16> %a239}240 241define <vscale x 1 x i16> @intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32(<vscale x 1 x i16> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {242; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32:243; CHECK: # %bb.0: # %entry244; CHECK-NEXT: fsrmi a1, 0245; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu246; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t247; CHECK-NEXT: fsrm a1248; CHECK-NEXT: ret249entry:250 %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32(251 <vscale x 1 x i16> %0,252 <vscale x 1 x float> %1,253 <vscale x 1 x i1> %2,254 iXLen 0, iXLen %3, iXLen 1)255 256 ret <vscale x 1 x i16> %a257}258 259define <vscale x 2 x i16> @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {260; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32:261; CHECK: # %bb.0: # %entry262; CHECK-NEXT: fsrmi a1, 0263; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma264; CHECK-NEXT: vfncvt.x.f.w v9, v8265; CHECK-NEXT: fsrm a1266; CHECK-NEXT: vmv1r.v v8, v9267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32(270 <vscale x 2 x i16> poison,271 <vscale x 2 x float> %0,272 iXLen 0, iXLen %1)273 274 ret <vscale x 2 x i16> %a275}276 277define <vscale x 2 x i16> @intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32(<vscale x 2 x i16> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {278; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32:279; CHECK: # %bb.0: # %entry280; CHECK-NEXT: fsrmi a1, 0281; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu282; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t283; CHECK-NEXT: fsrm a1284; CHECK-NEXT: ret285entry:286 %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32(287 <vscale x 2 x i16> %0,288 <vscale x 2 x float> %1,289 <vscale x 2 x i1> %2,290 iXLen 0, iXLen %3, iXLen 1)291 292 ret <vscale x 2 x i16> %a293}294 295define <vscale x 4 x i16> @intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {296; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32:297; CHECK: # %bb.0: # %entry298; CHECK-NEXT: fsrmi a1, 0299; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma300; CHECK-NEXT: vfncvt.x.f.w v10, v8301; CHECK-NEXT: fsrm a1302; CHECK-NEXT: vmv.v.v v8, v10303; CHECK-NEXT: ret304entry:305 %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32(306 <vscale x 4 x i16> poison,307 <vscale x 4 x float> %0,308 iXLen 0, iXLen %1)309 310 ret <vscale x 4 x i16> %a311}312 313define <vscale x 4 x i16> @intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32(<vscale x 4 x i16> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {314; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32:315; CHECK: # %bb.0: # %entry316; CHECK-NEXT: fsrmi a1, 0317; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu318; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t319; CHECK-NEXT: fsrm a1320; CHECK-NEXT: ret321entry:322 %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32(323 <vscale x 4 x i16> %0,324 <vscale x 4 x float> %1,325 <vscale x 4 x i1> %2,326 iXLen 0, iXLen %3, iXLen 1)327 328 ret <vscale x 4 x i16> %a329}330 331define <vscale x 8 x i16> @intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {332; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32:333; CHECK: # %bb.0: # %entry334; CHECK-NEXT: fsrmi a1, 0335; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma336; CHECK-NEXT: vfncvt.x.f.w v12, v8337; CHECK-NEXT: fsrm a1338; CHECK-NEXT: vmv.v.v v8, v12339; CHECK-NEXT: ret340entry:341 %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32(342 <vscale x 8 x i16> poison,343 <vscale x 8 x float> %0,344 iXLen 0, iXLen %1)345 346 ret <vscale x 8 x i16> %a347}348 349define <vscale x 8 x i16> @intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32(<vscale x 8 x i16> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {350; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32:351; CHECK: # %bb.0: # %entry352; CHECK-NEXT: fsrmi a1, 0353; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu354; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t355; CHECK-NEXT: fsrm a1356; CHECK-NEXT: ret357entry:358 %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32(359 <vscale x 8 x i16> %0,360 <vscale x 8 x float> %1,361 <vscale x 8 x i1> %2,362 iXLen 0, iXLen %3, iXLen 1)363 364 ret <vscale x 8 x i16> %a365}366 367define <vscale x 16 x i16> @intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {368; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32:369; CHECK: # %bb.0: # %entry370; CHECK-NEXT: fsrmi a1, 0371; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma372; CHECK-NEXT: vfncvt.x.f.w v16, v8373; CHECK-NEXT: fsrm a1374; CHECK-NEXT: vmv.v.v v8, v16375; CHECK-NEXT: ret376entry:377 %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32(378 <vscale x 16 x i16> poison,379 <vscale x 16 x float> %0,380 iXLen 0, iXLen %1)381 382 ret <vscale x 16 x i16> %a383}384 385define <vscale x 16 x i16> @intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32(<vscale x 16 x i16> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {386; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32:387; CHECK: # %bb.0: # %entry388; CHECK-NEXT: fsrmi a1, 0389; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu390; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t391; CHECK-NEXT: fsrm a1392; CHECK-NEXT: ret393entry:394 %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32(395 <vscale x 16 x i16> %0,396 <vscale x 16 x float> %1,397 <vscale x 16 x i1> %2,398 iXLen 0, iXLen %3, iXLen 1)399 400 ret <vscale x 16 x i16> %a401}402 403define <vscale x 1 x i32> @intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {404; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: fsrmi a1, 0407; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma408; CHECK-NEXT: vfncvt.x.f.w v9, v8409; CHECK-NEXT: fsrm a1410; CHECK-NEXT: vmv1r.v v8, v9411; CHECK-NEXT: ret412entry:413 %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64(414 <vscale x 1 x i32> poison,415 <vscale x 1 x double> %0,416 iXLen 0, iXLen %1)417 418 ret <vscale x 1 x i32> %a419}420 421define <vscale x 1 x i32> @intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64(<vscale x 1 x i32> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {422; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64:423; CHECK: # %bb.0: # %entry424; CHECK-NEXT: fsrmi a1, 0425; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu426; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t427; CHECK-NEXT: fsrm a1428; CHECK-NEXT: ret429entry:430 %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64(431 <vscale x 1 x i32> %0,432 <vscale x 1 x double> %1,433 <vscale x 1 x i1> %2,434 iXLen 0, iXLen %3, iXLen 1)435 436 ret <vscale x 1 x i32> %a437}438 439define <vscale x 2 x i32> @intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {440; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64:441; CHECK: # %bb.0: # %entry442; CHECK-NEXT: fsrmi a1, 0443; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma444; CHECK-NEXT: vfncvt.x.f.w v10, v8445; CHECK-NEXT: fsrm a1446; CHECK-NEXT: vmv.v.v v8, v10447; CHECK-NEXT: ret448entry:449 %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64(450 <vscale x 2 x i32> poison,451 <vscale x 2 x double> %0,452 iXLen 0, iXLen %1)453 454 ret <vscale x 2 x i32> %a455}456 457define <vscale x 2 x i32> @intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64(<vscale x 2 x i32> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {458; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64:459; CHECK: # %bb.0: # %entry460; CHECK-NEXT: fsrmi a1, 0461; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu462; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t463; CHECK-NEXT: fsrm a1464; CHECK-NEXT: ret465entry:466 %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64(467 <vscale x 2 x i32> %0,468 <vscale x 2 x double> %1,469 <vscale x 2 x i1> %2,470 iXLen 0, iXLen %3, iXLen 1)471 472 ret <vscale x 2 x i32> %a473}474 475define <vscale x 4 x i32> @intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {476; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64:477; CHECK: # %bb.0: # %entry478; CHECK-NEXT: fsrmi a1, 0479; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma480; CHECK-NEXT: vfncvt.x.f.w v12, v8481; CHECK-NEXT: fsrm a1482; CHECK-NEXT: vmv.v.v v8, v12483; CHECK-NEXT: ret484entry:485 %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64(486 <vscale x 4 x i32> poison,487 <vscale x 4 x double> %0,488 iXLen 0, iXLen %1)489 490 ret <vscale x 4 x i32> %a491}492 493define <vscale x 4 x i32> @intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64(<vscale x 4 x i32> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {494; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64:495; CHECK: # %bb.0: # %entry496; CHECK-NEXT: fsrmi a1, 0497; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu498; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t499; CHECK-NEXT: fsrm a1500; CHECK-NEXT: ret501entry:502 %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64(503 <vscale x 4 x i32> %0,504 <vscale x 4 x double> %1,505 <vscale x 4 x i1> %2,506 iXLen 0, iXLen %3, iXLen 1)507 508 ret <vscale x 4 x i32> %a509}510 511define <vscale x 8 x i32> @intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {512; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64:513; CHECK: # %bb.0: # %entry514; CHECK-NEXT: fsrmi a1, 0515; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma516; CHECK-NEXT: vfncvt.x.f.w v16, v8517; CHECK-NEXT: fsrm a1518; CHECK-NEXT: vmv.v.v v8, v16519; CHECK-NEXT: ret520entry:521 %a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64(522 <vscale x 8 x i32> poison,523 <vscale x 8 x double> %0,524 iXLen 0, iXLen %1)525 526 ret <vscale x 8 x i32> %a527}528 529define <vscale x 8 x i32> @intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64(<vscale x 8 x i32> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {530; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64:531; CHECK: # %bb.0: # %entry532; CHECK-NEXT: fsrmi a1, 0533; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu534; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t535; CHECK-NEXT: fsrm a1536; CHECK-NEXT: ret537entry:538 %a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64(539 <vscale x 8 x i32> %0,540 <vscale x 8 x double> %1,541 <vscale x 8 x i1> %2,542 iXLen 0, iXLen %3, iXLen 1)543 544 ret <vscale x 8 x i32> %a545}546 547define <vscale x 8 x i32> @intrinsic_vfncvt_mask_x.f.w_rtz_nxv8i32_nxv8f64(<vscale x 8 x i32> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {548; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_rtz_nxv8i32_nxv8f64:549; CHECK: # %bb.0: # %entry550; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu551; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t552; CHECK-NEXT: ret553entry:554 %a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64(555 <vscale x 8 x i32> %0,556 <vscale x 8 x double> %1,557 <vscale x 8 x i1> %2,558 iXLen 1, iXLen %3, iXLen 1)559 560 ret <vscale x 8 x i32> %a561}562 563