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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfbfmin \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfbfmin \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x bfloat> @intrinsic_vfncvtbf16_f.f.w_nxv1bf16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfncvtbf16_f.f.w_nxv1bf16_nxv1f32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vfncvtbf16.f.f.w v9, v812; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32(16 <vscale x 1 x bfloat> poison,17 <vscale x 1 x float> %0,18 iXLen 7, iXLen %1)19 20 ret <vscale x 1 x bfloat> %a21}22 23define <vscale x 1 x bfloat> @intrinsic_vfncvtbf16_mask_f.f.w_nxv1bf16_nxv1f32(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {24; CHECK-LABEL: intrinsic_vfncvtbf16_mask_f.f.w_nxv1bf16_nxv1f32:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu27; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32(31 <vscale x 1 x bfloat> %0,32 <vscale x 1 x float> %1,33 <vscale x 1 x i1> %2,34 iXLen 7, iXLen %3, iXLen 1)35 36 ret <vscale x 1 x bfloat> %a37}38 39define <vscale x 2 x bfloat> @intrinsic_vfncvtbf16_f.f.w_nxv2bf16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {40; CHECK-LABEL: intrinsic_vfncvtbf16_f.f.w_nxv2bf16_nxv2f32:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma43; CHECK-NEXT: vfncvtbf16.f.f.w v9, v844; CHECK-NEXT: vmv1r.v v8, v945; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32(48 <vscale x 2 x bfloat> poison,49 <vscale x 2 x float> %0,50 iXLen 7, iXLen %1)51 52 ret <vscale x 2 x bfloat> %a53}54 55define <vscale x 2 x bfloat> @intrinsic_vfncvtbf16_mask_f.f.w_nxv2bf16_nxv2f32(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {56; CHECK-LABEL: intrinsic_vfncvtbf16_mask_f.f.w_nxv2bf16_nxv2f32:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu59; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t60; CHECK-NEXT: ret61entry:62 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32(63 <vscale x 2 x bfloat> %0,64 <vscale x 2 x float> %1,65 <vscale x 2 x i1> %2,66 iXLen 7, iXLen %3, iXLen 1)67 68 ret <vscale x 2 x bfloat> %a69}70 71define <vscale x 4 x bfloat> @intrinsic_vfncvtbf16_f.f.w_nxv4bf16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {72; CHECK-LABEL: intrinsic_vfncvtbf16_f.f.w_nxv4bf16_nxv4f32:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma75; CHECK-NEXT: vfncvtbf16.f.f.w v10, v876; CHECK-NEXT: vmv.v.v v8, v1077; CHECK-NEXT: ret78entry:79 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32(80 <vscale x 4 x bfloat> poison,81 <vscale x 4 x float> %0,82 iXLen 7, iXLen %1)83 84 ret <vscale x 4 x bfloat> %a85}86 87define <vscale x 4 x bfloat> @intrinsic_vfncvtbf16_mask_f.f.w_nxv4bf16_nxv4f32(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {88; CHECK-LABEL: intrinsic_vfncvtbf16_mask_f.f.w_nxv4bf16_nxv4f32:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu91; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t92; CHECK-NEXT: ret93entry:94 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32(95 <vscale x 4 x bfloat> %0,96 <vscale x 4 x float> %1,97 <vscale x 4 x i1> %2,98 iXLen 7, iXLen %3, iXLen 1)99 100 ret <vscale x 4 x bfloat> %a101}102 103define <vscale x 8 x bfloat> @intrinsic_vfncvtbf16_f.f.w_nxv8bf16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {104; CHECK-LABEL: intrinsic_vfncvtbf16_f.f.w_nxv8bf16_nxv8f32:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma107; CHECK-NEXT: vfncvtbf16.f.f.w v12, v8108; CHECK-NEXT: vmv.v.v v8, v12109; CHECK-NEXT: ret110entry:111 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32(112 <vscale x 8 x bfloat> poison,113 <vscale x 8 x float> %0,114 iXLen 7, iXLen %1)115 116 ret <vscale x 8 x bfloat> %a117}118 119define <vscale x 8 x bfloat> @intrinsic_vfncvtbf16_mask_f.f.w_nxv8bf16_nxv8f32(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {120; CHECK-LABEL: intrinsic_vfncvtbf16_mask_f.f.w_nxv8bf16_nxv8f32:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu123; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t124; CHECK-NEXT: ret125entry:126 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32(127 <vscale x 8 x bfloat> %0,128 <vscale x 8 x float> %1,129 <vscale x 8 x i1> %2,130 iXLen 7, iXLen %3, iXLen 1)131 132 ret <vscale x 8 x bfloat> %a133}134 135define <vscale x 16 x bfloat> @intrinsic_vfncvtbf16_f.f.w_nxv16bf16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {136; CHECK-LABEL: intrinsic_vfncvtbf16_f.f.w_nxv16bf16_nxv16f32:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma139; CHECK-NEXT: vfncvtbf16.f.f.w v16, v8140; CHECK-NEXT: vmv.v.v v8, v16141; CHECK-NEXT: ret142entry:143 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32(144 <vscale x 16 x bfloat> poison,145 <vscale x 16 x float> %0,146 iXLen 7, iXLen %1)147 148 ret <vscale x 16 x bfloat> %a149}150 151define <vscale x 16 x bfloat> @intrinsic_vfncvtbf16_mask_f.f.w_nxv16bf16_nxv16f32(<vscale x 16 x bfloat> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {152; CHECK-LABEL: intrinsic_vfncvtbf16_mask_f.f.w_nxv16bf16_nxv16f32:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu155; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t156; CHECK-NEXT: ret157entry:158 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32(159 <vscale x 16 x bfloat> %0,160 <vscale x 16 x float> %1,161 <vscale x 16 x i1> %2,162 iXLen 7, iXLen %3, iXLen 1)163 164 ret <vscale x 16 x bfloat> %a165}166