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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN14; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v \15; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \16; RUN: --check-prefixes=CHECK,ZVFBFA17; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v \18; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \19; RUN: --check-prefixes=CHECK,ZVFBFA20 21define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %va) {22; ZVFH-LABEL: nxv1bf16:23; ZVFH: # %bb.0:24; ZVFH-NEXT: lui a0, 825; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma26; ZVFH-NEXT: vxor.vx v8, v8, a027; ZVFH-NEXT: ret28;29; ZVFHMIN-LABEL: nxv1bf16:30; ZVFHMIN: # %bb.0:31; ZVFHMIN-NEXT: lui a0, 832; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma33; ZVFHMIN-NEXT: vxor.vx v8, v8, a034; ZVFHMIN-NEXT: ret35;36; ZVFBFA-LABEL: nxv1bf16:37; ZVFBFA: # %bb.0:38; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma39; ZVFBFA-NEXT: vfneg.v v8, v840; ZVFBFA-NEXT: ret41 %vb = fneg <vscale x 1 x bfloat> %va42 ret <vscale x 1 x bfloat> %vb43}44 45define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %va) {46; ZVFH-LABEL: nxv2bf16:47; ZVFH: # %bb.0:48; ZVFH-NEXT: lui a0, 849; ZVFH-NEXT: vsetvli a1, zero, e16, mf2, ta, ma50; ZVFH-NEXT: vxor.vx v8, v8, a051; ZVFH-NEXT: ret52;53; ZVFHMIN-LABEL: nxv2bf16:54; ZVFHMIN: # %bb.0:55; ZVFHMIN-NEXT: lui a0, 856; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma57; ZVFHMIN-NEXT: vxor.vx v8, v8, a058; ZVFHMIN-NEXT: ret59;60; ZVFBFA-LABEL: nxv2bf16:61; ZVFBFA: # %bb.0:62; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf2, ta, ma63; ZVFBFA-NEXT: vfneg.v v8, v864; ZVFBFA-NEXT: ret65 %vb = fneg <vscale x 2 x bfloat> %va66 ret <vscale x 2 x bfloat> %vb67}68 69define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %va) {70; ZVFH-LABEL: nxv4bf16:71; ZVFH: # %bb.0:72; ZVFH-NEXT: lui a0, 873; ZVFH-NEXT: vsetvli a1, zero, e16, m1, ta, ma74; ZVFH-NEXT: vxor.vx v8, v8, a075; ZVFH-NEXT: ret76;77; ZVFHMIN-LABEL: nxv4bf16:78; ZVFHMIN: # %bb.0:79; ZVFHMIN-NEXT: lui a0, 880; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma81; ZVFHMIN-NEXT: vxor.vx v8, v8, a082; ZVFHMIN-NEXT: ret83;84; ZVFBFA-LABEL: nxv4bf16:85; ZVFBFA: # %bb.0:86; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m1, ta, ma87; ZVFBFA-NEXT: vfneg.v v8, v888; ZVFBFA-NEXT: ret89 %vb = fneg <vscale x 4 x bfloat> %va90 ret <vscale x 4 x bfloat> %vb91}92 93define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %va) {94; ZVFH-LABEL: nxv8bf16:95; ZVFH: # %bb.0:96; ZVFH-NEXT: lui a0, 897; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma98; ZVFH-NEXT: vxor.vx v8, v8, a099; ZVFH-NEXT: ret100;101; ZVFHMIN-LABEL: nxv8bf16:102; ZVFHMIN: # %bb.0:103; ZVFHMIN-NEXT: lui a0, 8104; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma105; ZVFHMIN-NEXT: vxor.vx v8, v8, a0106; ZVFHMIN-NEXT: ret107;108; ZVFBFA-LABEL: nxv8bf16:109; ZVFBFA: # %bb.0:110; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m2, ta, ma111; ZVFBFA-NEXT: vfneg.v v8, v8112; ZVFBFA-NEXT: ret113 %vb = fneg <vscale x 8 x bfloat> %va114 ret <vscale x 8 x bfloat> %vb115}116 117define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %va) {118; ZVFH-LABEL: nxv16bf16:119; ZVFH: # %bb.0:120; ZVFH-NEXT: lui a0, 8121; ZVFH-NEXT: vsetvli a1, zero, e16, m4, ta, ma122; ZVFH-NEXT: vxor.vx v8, v8, a0123; ZVFH-NEXT: ret124;125; ZVFHMIN-LABEL: nxv16bf16:126; ZVFHMIN: # %bb.0:127; ZVFHMIN-NEXT: lui a0, 8128; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma129; ZVFHMIN-NEXT: vxor.vx v8, v8, a0130; ZVFHMIN-NEXT: ret131;132; ZVFBFA-LABEL: nxv16bf16:133; ZVFBFA: # %bb.0:134; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m4, ta, ma135; ZVFBFA-NEXT: vfneg.v v8, v8136; ZVFBFA-NEXT: ret137 %vb = fneg <vscale x 16 x bfloat> %va138 ret <vscale x 16 x bfloat> %vb139}140 141define <vscale x 32 x bfloat> @nxv32bf16(<vscale x 32 x bfloat> %va) {142; ZVFH-LABEL: nxv32bf16:143; ZVFH: # %bb.0:144; ZVFH-NEXT: lui a0, 8145; ZVFH-NEXT: vsetvli a1, zero, e16, m8, ta, ma146; ZVFH-NEXT: vxor.vx v8, v8, a0147; ZVFH-NEXT: ret148;149; ZVFHMIN-LABEL: nxv32bf16:150; ZVFHMIN: # %bb.0:151; ZVFHMIN-NEXT: lui a0, 8152; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma153; ZVFHMIN-NEXT: vxor.vx v8, v8, a0154; ZVFHMIN-NEXT: ret155;156; ZVFBFA-LABEL: nxv32bf16:157; ZVFBFA: # %bb.0:158; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m8, ta, ma159; ZVFBFA-NEXT: vfneg.v v8, v8160; ZVFBFA-NEXT: ret161 %vb = fneg <vscale x 32 x bfloat> %va162 ret <vscale x 32 x bfloat> %vb163}164 165define <vscale x 1 x half> @vfneg_vv_nxv1f16(<vscale x 1 x half> %va) {166; ZVFH-LABEL: vfneg_vv_nxv1f16:167; ZVFH: # %bb.0:168; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma169; ZVFH-NEXT: vfneg.v v8, v8170; ZVFH-NEXT: ret171;172; ZVFHMIN-LABEL: vfneg_vv_nxv1f16:173; ZVFHMIN: # %bb.0:174; ZVFHMIN-NEXT: lui a0, 8175; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma176; ZVFHMIN-NEXT: vxor.vx v8, v8, a0177; ZVFHMIN-NEXT: ret178;179; ZVFBFA-LABEL: vfneg_vv_nxv1f16:180; ZVFBFA: # %bb.0:181; ZVFBFA-NEXT: lui a0, 8182; ZVFBFA-NEXT: vsetvli a1, zero, e16, mf4, ta, ma183; ZVFBFA-NEXT: vxor.vx v8, v8, a0184; ZVFBFA-NEXT: ret185 %vb = fneg <vscale x 1 x half> %va186 ret <vscale x 1 x half> %vb187}188 189define <vscale x 2 x half> @vfneg_vv_nxv2f16(<vscale x 2 x half> %va) {190; ZVFH-LABEL: vfneg_vv_nxv2f16:191; ZVFH: # %bb.0:192; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma193; ZVFH-NEXT: vfneg.v v8, v8194; ZVFH-NEXT: ret195;196; ZVFHMIN-LABEL: vfneg_vv_nxv2f16:197; ZVFHMIN: # %bb.0:198; ZVFHMIN-NEXT: lui a0, 8199; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma200; ZVFHMIN-NEXT: vxor.vx v8, v8, a0201; ZVFHMIN-NEXT: ret202;203; ZVFBFA-LABEL: vfneg_vv_nxv2f16:204; ZVFBFA: # %bb.0:205; ZVFBFA-NEXT: lui a0, 8206; ZVFBFA-NEXT: vsetvli a1, zero, e16, mf2, ta, ma207; ZVFBFA-NEXT: vxor.vx v8, v8, a0208; ZVFBFA-NEXT: ret209 %vb = fneg <vscale x 2 x half> %va210 ret <vscale x 2 x half> %vb211}212 213define <vscale x 4 x half> @vfneg_vv_nxv4f16(<vscale x 4 x half> %va) {214; ZVFH-LABEL: vfneg_vv_nxv4f16:215; ZVFH: # %bb.0:216; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma217; ZVFH-NEXT: vfneg.v v8, v8218; ZVFH-NEXT: ret219;220; ZVFHMIN-LABEL: vfneg_vv_nxv4f16:221; ZVFHMIN: # %bb.0:222; ZVFHMIN-NEXT: lui a0, 8223; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma224; ZVFHMIN-NEXT: vxor.vx v8, v8, a0225; ZVFHMIN-NEXT: ret226;227; ZVFBFA-LABEL: vfneg_vv_nxv4f16:228; ZVFBFA: # %bb.0:229; ZVFBFA-NEXT: lui a0, 8230; ZVFBFA-NEXT: vsetvli a1, zero, e16, m1, ta, ma231; ZVFBFA-NEXT: vxor.vx v8, v8, a0232; ZVFBFA-NEXT: ret233 %vb = fneg <vscale x 4 x half> %va234 ret <vscale x 4 x half> %vb235}236 237define <vscale x 8 x half> @vfneg_vv_nxv8f16(<vscale x 8 x half> %va) {238; ZVFH-LABEL: vfneg_vv_nxv8f16:239; ZVFH: # %bb.0:240; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma241; ZVFH-NEXT: vfneg.v v8, v8242; ZVFH-NEXT: ret243;244; ZVFHMIN-LABEL: vfneg_vv_nxv8f16:245; ZVFHMIN: # %bb.0:246; ZVFHMIN-NEXT: lui a0, 8247; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma248; ZVFHMIN-NEXT: vxor.vx v8, v8, a0249; ZVFHMIN-NEXT: ret250;251; ZVFBFA-LABEL: vfneg_vv_nxv8f16:252; ZVFBFA: # %bb.0:253; ZVFBFA-NEXT: lui a0, 8254; ZVFBFA-NEXT: vsetvli a1, zero, e16, m2, ta, ma255; ZVFBFA-NEXT: vxor.vx v8, v8, a0256; ZVFBFA-NEXT: ret257 %vb = fneg <vscale x 8 x half> %va258 ret <vscale x 8 x half> %vb259}260 261define <vscale x 16 x half> @vfneg_vv_nxv16f16(<vscale x 16 x half> %va) {262; ZVFH-LABEL: vfneg_vv_nxv16f16:263; ZVFH: # %bb.0:264; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma265; ZVFH-NEXT: vfneg.v v8, v8266; ZVFH-NEXT: ret267;268; ZVFHMIN-LABEL: vfneg_vv_nxv16f16:269; ZVFHMIN: # %bb.0:270; ZVFHMIN-NEXT: lui a0, 8271; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma272; ZVFHMIN-NEXT: vxor.vx v8, v8, a0273; ZVFHMIN-NEXT: ret274;275; ZVFBFA-LABEL: vfneg_vv_nxv16f16:276; ZVFBFA: # %bb.0:277; ZVFBFA-NEXT: lui a0, 8278; ZVFBFA-NEXT: vsetvli a1, zero, e16, m4, ta, ma279; ZVFBFA-NEXT: vxor.vx v8, v8, a0280; ZVFBFA-NEXT: ret281 %vb = fneg <vscale x 16 x half> %va282 ret <vscale x 16 x half> %vb283}284 285define <vscale x 32 x half> @vfneg_vv_nxv32f16(<vscale x 32 x half> %va) {286; ZVFH-LABEL: vfneg_vv_nxv32f16:287; ZVFH: # %bb.0:288; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma289; ZVFH-NEXT: vfneg.v v8, v8290; ZVFH-NEXT: ret291;292; ZVFHMIN-LABEL: vfneg_vv_nxv32f16:293; ZVFHMIN: # %bb.0:294; ZVFHMIN-NEXT: lui a0, 8295; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma296; ZVFHMIN-NEXT: vxor.vx v8, v8, a0297; ZVFHMIN-NEXT: ret298;299; ZVFBFA-LABEL: vfneg_vv_nxv32f16:300; ZVFBFA: # %bb.0:301; ZVFBFA-NEXT: lui a0, 8302; ZVFBFA-NEXT: vsetvli a1, zero, e16, m8, ta, ma303; ZVFBFA-NEXT: vxor.vx v8, v8, a0304; ZVFBFA-NEXT: ret305 %vb = fneg <vscale x 32 x half> %va306 ret <vscale x 32 x half> %vb307}308 309define <vscale x 1 x float> @vfneg_vv_nxv1f32(<vscale x 1 x float> %va) {310; CHECK-LABEL: vfneg_vv_nxv1f32:311; CHECK: # %bb.0:312; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma313; CHECK-NEXT: vfneg.v v8, v8314; CHECK-NEXT: ret315 %vb = fneg <vscale x 1 x float> %va316 ret <vscale x 1 x float> %vb317}318 319define <vscale x 2 x float> @vfneg_vv_nxv2f32(<vscale x 2 x float> %va) {320; CHECK-LABEL: vfneg_vv_nxv2f32:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma323; CHECK-NEXT: vfneg.v v8, v8324; CHECK-NEXT: ret325 %vb = fneg <vscale x 2 x float> %va326 ret <vscale x 2 x float> %vb327}328 329define <vscale x 4 x float> @vfneg_vv_nxv4f32(<vscale x 4 x float> %va) {330; CHECK-LABEL: vfneg_vv_nxv4f32:331; CHECK: # %bb.0:332; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma333; CHECK-NEXT: vfneg.v v8, v8334; CHECK-NEXT: ret335 %vb = fneg <vscale x 4 x float> %va336 ret <vscale x 4 x float> %vb337}338 339define <vscale x 8 x float> @vfneg_vv_nxv8f32(<vscale x 8 x float> %va) {340; CHECK-LABEL: vfneg_vv_nxv8f32:341; CHECK: # %bb.0:342; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma343; CHECK-NEXT: vfneg.v v8, v8344; CHECK-NEXT: ret345 %vb = fneg <vscale x 8 x float> %va346 ret <vscale x 8 x float> %vb347}348 349define <vscale x 16 x float> @vfneg_vv_nxv16f32(<vscale x 16 x float> %va) {350; CHECK-LABEL: vfneg_vv_nxv16f32:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma353; CHECK-NEXT: vfneg.v v8, v8354; CHECK-NEXT: ret355 %vb = fneg <vscale x 16 x float> %va356 ret <vscale x 16 x float> %vb357}358 359define <vscale x 1 x double> @vfneg_vv_nxv1f64(<vscale x 1 x double> %va) {360; CHECK-LABEL: vfneg_vv_nxv1f64:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma363; CHECK-NEXT: vfneg.v v8, v8364; CHECK-NEXT: ret365 %vb = fneg <vscale x 1 x double> %va366 ret <vscale x 1 x double> %vb367}368 369define <vscale x 2 x double> @vfneg_vv_nxv2f64(<vscale x 2 x double> %va) {370; CHECK-LABEL: vfneg_vv_nxv2f64:371; CHECK: # %bb.0:372; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma373; CHECK-NEXT: vfneg.v v8, v8374; CHECK-NEXT: ret375 %vb = fneg <vscale x 2 x double> %va376 ret <vscale x 2 x double> %vb377}378 379define <vscale x 4 x double> @vfneg_vv_nxv4f64(<vscale x 4 x double> %va) {380; CHECK-LABEL: vfneg_vv_nxv4f64:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma383; CHECK-NEXT: vfneg.v v8, v8384; CHECK-NEXT: ret385 %vb = fneg <vscale x 4 x double> %va386 ret <vscale x 4 x double> %vb387}388 389define <vscale x 8 x double> @vfneg_vv_nxv8f64(<vscale x 8 x double> %va) {390; CHECK-LABEL: vfneg_vv_nxv8f64:391; CHECK: # %bb.0:392; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma393; CHECK-NEXT: vfneg.v v8, v8394; CHECK-NEXT: ret395 %vb = fneg <vscale x 8 x double> %va396 ret <vscale x 8 x double> %vb397}398