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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN10; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v -target-abi=ilp32d \11; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA12; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v -target-abi=lp64d \13; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA14 15define <vscale x 1 x bfloat> @vfneg_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {16; ZVFH-LABEL: vfneg_vv_nxv1bf16:17; ZVFH: # %bb.0:18; ZVFH-NEXT: lui a1, 819; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma20; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t21; ZVFH-NEXT: ret22;23; ZVFHMIN-LABEL: vfneg_vv_nxv1bf16:24; ZVFHMIN: # %bb.0:25; ZVFHMIN-NEXT: lui a1, 826; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma27; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t28; ZVFHMIN-NEXT: ret29;30; ZVFBFA-LABEL: vfneg_vv_nxv1bf16:31; ZVFBFA: # %bb.0:32; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma33; ZVFBFA-NEXT: vfneg.v v8, v8, v0.t34; ZVFBFA-NEXT: ret35 %v = call <vscale x 1 x bfloat> @llvm.vp.fneg.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)36 ret <vscale x 1 x bfloat> %v37}38 39define <vscale x 1 x bfloat> @vfneg_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, i32 zeroext %evl) {40; ZVFH-LABEL: vfneg_vv_nxv1bf16_unmasked:41; ZVFH: # %bb.0:42; ZVFH-NEXT: lui a1, 843; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma44; ZVFH-NEXT: vxor.vx v8, v8, a145; ZVFH-NEXT: ret46;47; ZVFHMIN-LABEL: vfneg_vv_nxv1bf16_unmasked:48; ZVFHMIN: # %bb.0:49; ZVFHMIN-NEXT: lui a1, 850; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma51; ZVFHMIN-NEXT: vxor.vx v8, v8, a152; ZVFHMIN-NEXT: ret53;54; ZVFBFA-LABEL: vfneg_vv_nxv1bf16_unmasked:55; ZVFBFA: # %bb.0:56; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma57; ZVFBFA-NEXT: vfneg.v v8, v858; ZVFBFA-NEXT: ret59 %v = call <vscale x 1 x bfloat> @llvm.vp.fneg.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)60 ret <vscale x 1 x bfloat> %v61}62 63define <vscale x 2 x bfloat> @vfneg_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {64; ZVFH-LABEL: vfneg_vv_nxv2bf16:65; ZVFH: # %bb.0:66; ZVFH-NEXT: lui a1, 867; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma68; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t69; ZVFH-NEXT: ret70;71; ZVFHMIN-LABEL: vfneg_vv_nxv2bf16:72; ZVFHMIN: # %bb.0:73; ZVFHMIN-NEXT: lui a1, 874; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma75; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t76; ZVFHMIN-NEXT: ret77;78; ZVFBFA-LABEL: vfneg_vv_nxv2bf16:79; ZVFBFA: # %bb.0:80; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma81; ZVFBFA-NEXT: vfneg.v v8, v8, v0.t82; ZVFBFA-NEXT: ret83 %v = call <vscale x 2 x bfloat> @llvm.vp.fneg.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)84 ret <vscale x 2 x bfloat> %v85}86 87define <vscale x 2 x bfloat> @vfneg_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, i32 zeroext %evl) {88; ZVFH-LABEL: vfneg_vv_nxv2bf16_unmasked:89; ZVFH: # %bb.0:90; ZVFH-NEXT: lui a1, 891; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma92; ZVFH-NEXT: vxor.vx v8, v8, a193; ZVFH-NEXT: ret94;95; ZVFHMIN-LABEL: vfneg_vv_nxv2bf16_unmasked:96; ZVFHMIN: # %bb.0:97; ZVFHMIN-NEXT: lui a1, 898; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma99; ZVFHMIN-NEXT: vxor.vx v8, v8, a1100; ZVFHMIN-NEXT: ret101;102; ZVFBFA-LABEL: vfneg_vv_nxv2bf16_unmasked:103; ZVFBFA: # %bb.0:104; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma105; ZVFBFA-NEXT: vfneg.v v8, v8106; ZVFBFA-NEXT: ret107 %v = call <vscale x 2 x bfloat> @llvm.vp.fneg.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)108 ret <vscale x 2 x bfloat> %v109}110 111define <vscale x 4 x bfloat> @vfneg_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {112; ZVFH-LABEL: vfneg_vv_nxv4bf16:113; ZVFH: # %bb.0:114; ZVFH-NEXT: lui a1, 8115; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma116; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t117; ZVFH-NEXT: ret118;119; ZVFHMIN-LABEL: vfneg_vv_nxv4bf16:120; ZVFHMIN: # %bb.0:121; ZVFHMIN-NEXT: lui a1, 8122; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma123; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t124; ZVFHMIN-NEXT: ret125;126; ZVFBFA-LABEL: vfneg_vv_nxv4bf16:127; ZVFBFA: # %bb.0:128; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma129; ZVFBFA-NEXT: vfneg.v v8, v8, v0.t130; ZVFBFA-NEXT: ret131 %v = call <vscale x 4 x bfloat> @llvm.vp.fneg.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 %evl)132 ret <vscale x 4 x bfloat> %v133}134 135define <vscale x 4 x bfloat> @vfneg_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, i32 zeroext %evl) {136; ZVFH-LABEL: vfneg_vv_nxv4bf16_unmasked:137; ZVFH: # %bb.0:138; ZVFH-NEXT: lui a1, 8139; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma140; ZVFH-NEXT: vxor.vx v8, v8, a1141; ZVFH-NEXT: ret142;143; ZVFHMIN-LABEL: vfneg_vv_nxv4bf16_unmasked:144; ZVFHMIN: # %bb.0:145; ZVFHMIN-NEXT: lui a1, 8146; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma147; ZVFHMIN-NEXT: vxor.vx v8, v8, a1148; ZVFHMIN-NEXT: ret149;150; ZVFBFA-LABEL: vfneg_vv_nxv4bf16_unmasked:151; ZVFBFA: # %bb.0:152; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma153; ZVFBFA-NEXT: vfneg.v v8, v8154; ZVFBFA-NEXT: ret155 %v = call <vscale x 4 x bfloat> @llvm.vp.fneg.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)156 ret <vscale x 4 x bfloat> %v157}158 159define <vscale x 8 x bfloat> @vfneg_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {160; ZVFH-LABEL: vfneg_vv_nxv8bf16:161; ZVFH: # %bb.0:162; ZVFH-NEXT: lui a1, 8163; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma164; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t165; ZVFH-NEXT: ret166;167; ZVFHMIN-LABEL: vfneg_vv_nxv8bf16:168; ZVFHMIN: # %bb.0:169; ZVFHMIN-NEXT: lui a1, 8170; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma171; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t172; ZVFHMIN-NEXT: ret173;174; ZVFBFA-LABEL: vfneg_vv_nxv8bf16:175; ZVFBFA: # %bb.0:176; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma177; ZVFBFA-NEXT: vfneg.v v8, v8, v0.t178; ZVFBFA-NEXT: ret179 %v = call <vscale x 8 x bfloat> @llvm.vp.fneg.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 %evl)180 ret <vscale x 8 x bfloat> %v181}182 183define <vscale x 8 x bfloat> @vfneg_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, i32 zeroext %evl) {184; ZVFH-LABEL: vfneg_vv_nxv8bf16_unmasked:185; ZVFH: # %bb.0:186; ZVFH-NEXT: lui a1, 8187; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma188; ZVFH-NEXT: vxor.vx v8, v8, a1189; ZVFH-NEXT: ret190;191; ZVFHMIN-LABEL: vfneg_vv_nxv8bf16_unmasked:192; ZVFHMIN: # %bb.0:193; ZVFHMIN-NEXT: lui a1, 8194; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma195; ZVFHMIN-NEXT: vxor.vx v8, v8, a1196; ZVFHMIN-NEXT: ret197;198; ZVFBFA-LABEL: vfneg_vv_nxv8bf16_unmasked:199; ZVFBFA: # %bb.0:200; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma201; ZVFBFA-NEXT: vfneg.v v8, v8202; ZVFBFA-NEXT: ret203 %v = call <vscale x 8 x bfloat> @llvm.vp.fneg.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)204 ret <vscale x 8 x bfloat> %v205}206 207define <vscale x 16 x bfloat> @vfneg_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {208; ZVFH-LABEL: vfneg_vv_nxv16bf16:209; ZVFH: # %bb.0:210; ZVFH-NEXT: lui a1, 8211; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma212; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t213; ZVFH-NEXT: ret214;215; ZVFHMIN-LABEL: vfneg_vv_nxv16bf16:216; ZVFHMIN: # %bb.0:217; ZVFHMIN-NEXT: lui a1, 8218; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma219; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t220; ZVFHMIN-NEXT: ret221;222; ZVFBFA-LABEL: vfneg_vv_nxv16bf16:223; ZVFBFA: # %bb.0:224; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma225; ZVFBFA-NEXT: vfneg.v v8, v8, v0.t226; ZVFBFA-NEXT: ret227 %v = call <vscale x 16 x bfloat> @llvm.vp.fneg.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 %evl)228 ret <vscale x 16 x bfloat> %v229}230 231define <vscale x 16 x bfloat> @vfneg_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, i32 zeroext %evl) {232; ZVFH-LABEL: vfneg_vv_nxv16bf16_unmasked:233; ZVFH: # %bb.0:234; ZVFH-NEXT: lui a1, 8235; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma236; ZVFH-NEXT: vxor.vx v8, v8, a1237; ZVFH-NEXT: ret238;239; ZVFHMIN-LABEL: vfneg_vv_nxv16bf16_unmasked:240; ZVFHMIN: # %bb.0:241; ZVFHMIN-NEXT: lui a1, 8242; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma243; ZVFHMIN-NEXT: vxor.vx v8, v8, a1244; ZVFHMIN-NEXT: ret245;246; ZVFBFA-LABEL: vfneg_vv_nxv16bf16_unmasked:247; ZVFBFA: # %bb.0:248; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma249; ZVFBFA-NEXT: vfneg.v v8, v8250; ZVFBFA-NEXT: ret251 %v = call <vscale x 16 x bfloat> @llvm.vp.fneg.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)252 ret <vscale x 16 x bfloat> %v253}254 255define <vscale x 32 x bfloat> @vfneg_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {256; ZVFH-LABEL: vfneg_vv_nxv32bf16:257; ZVFH: # %bb.0:258; ZVFH-NEXT: lui a1, 8259; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma260; ZVFH-NEXT: vxor.vx v8, v8, a1, v0.t261; ZVFH-NEXT: ret262;263; ZVFHMIN-LABEL: vfneg_vv_nxv32bf16:264; ZVFHMIN: # %bb.0:265; ZVFHMIN-NEXT: lui a1, 8266; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma267; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t268; ZVFHMIN-NEXT: ret269;270; ZVFBFA-LABEL: vfneg_vv_nxv32bf16:271; ZVFBFA: # %bb.0:272; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma273; ZVFBFA-NEXT: vfneg.v v8, v8, v0.t274; ZVFBFA-NEXT: ret275 %v = call <vscale x 32 x bfloat> @llvm.vp.fneg.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)276 ret <vscale x 32 x bfloat> %v277}278 279define <vscale x 32 x bfloat> @vfneg_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, i32 zeroext %evl) {280; ZVFH-LABEL: vfneg_vv_nxv32bf16_unmasked:281; ZVFH: # %bb.0:282; ZVFH-NEXT: lui a1, 8283; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma284; ZVFH-NEXT: vxor.vx v8, v8, a1285; ZVFH-NEXT: ret286;287; ZVFHMIN-LABEL: vfneg_vv_nxv32bf16_unmasked:288; ZVFHMIN: # %bb.0:289; ZVFHMIN-NEXT: lui a1, 8290; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma291; ZVFHMIN-NEXT: vxor.vx v8, v8, a1292; ZVFHMIN-NEXT: ret293;294; ZVFBFA-LABEL: vfneg_vv_nxv32bf16_unmasked:295; ZVFBFA: # %bb.0:296; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma297; ZVFBFA-NEXT: vfneg.v v8, v8298; ZVFBFA-NEXT: ret299 %v = call <vscale x 32 x bfloat> @llvm.vp.fneg.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)300 ret <vscale x 32 x bfloat> %v301}302 303define <vscale x 1 x half> @vfneg_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {304; ZVFH-LABEL: vfneg_vv_nxv1f16:305; ZVFH: # %bb.0:306; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma307; ZVFH-NEXT: vfneg.v v8, v8, v0.t308; ZVFH-NEXT: ret309;310; ZVFHMIN-LABEL: vfneg_vv_nxv1f16:311; ZVFHMIN: # %bb.0:312; ZVFHMIN-NEXT: lui a1, 8313; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma314; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t315; ZVFHMIN-NEXT: ret316;317; ZVFBFA-LABEL: vfneg_vv_nxv1f16:318; ZVFBFA: # %bb.0:319; ZVFBFA-NEXT: lui a1, 8320; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf4, ta, ma321; ZVFBFA-NEXT: vxor.vx v8, v8, a1, v0.t322; ZVFBFA-NEXT: ret323 %v = call <vscale x 1 x half> @llvm.vp.fneg.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)324 ret <vscale x 1 x half> %v325}326 327define <vscale x 1 x half> @vfneg_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, i32 zeroext %evl) {328; ZVFH-LABEL: vfneg_vv_nxv1f16_unmasked:329; ZVFH: # %bb.0:330; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma331; ZVFH-NEXT: vfneg.v v8, v8332; ZVFH-NEXT: ret333;334; ZVFHMIN-LABEL: vfneg_vv_nxv1f16_unmasked:335; ZVFHMIN: # %bb.0:336; ZVFHMIN-NEXT: lui a1, 8337; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma338; ZVFHMIN-NEXT: vxor.vx v8, v8, a1339; ZVFHMIN-NEXT: ret340;341; ZVFBFA-LABEL: vfneg_vv_nxv1f16_unmasked:342; ZVFBFA: # %bb.0:343; ZVFBFA-NEXT: lui a1, 8344; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf4, ta, ma345; ZVFBFA-NEXT: vxor.vx v8, v8, a1346; ZVFBFA-NEXT: ret347 %v = call <vscale x 1 x half> @llvm.vp.fneg.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)348 ret <vscale x 1 x half> %v349}350 351define <vscale x 2 x half> @vfneg_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {352; ZVFH-LABEL: vfneg_vv_nxv2f16:353; ZVFH: # %bb.0:354; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma355; ZVFH-NEXT: vfneg.v v8, v8, v0.t356; ZVFH-NEXT: ret357;358; ZVFHMIN-LABEL: vfneg_vv_nxv2f16:359; ZVFHMIN: # %bb.0:360; ZVFHMIN-NEXT: lui a1, 8361; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma362; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t363; ZVFHMIN-NEXT: ret364;365; ZVFBFA-LABEL: vfneg_vv_nxv2f16:366; ZVFBFA: # %bb.0:367; ZVFBFA-NEXT: lui a1, 8368; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf2, ta, ma369; ZVFBFA-NEXT: vxor.vx v8, v8, a1, v0.t370; ZVFBFA-NEXT: ret371 %v = call <vscale x 2 x half> @llvm.vp.fneg.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)372 ret <vscale x 2 x half> %v373}374 375define <vscale x 2 x half> @vfneg_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {376; ZVFH-LABEL: vfneg_vv_nxv2f16_unmasked:377; ZVFH: # %bb.0:378; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma379; ZVFH-NEXT: vfneg.v v8, v8380; ZVFH-NEXT: ret381;382; ZVFHMIN-LABEL: vfneg_vv_nxv2f16_unmasked:383; ZVFHMIN: # %bb.0:384; ZVFHMIN-NEXT: lui a1, 8385; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma386; ZVFHMIN-NEXT: vxor.vx v8, v8, a1387; ZVFHMIN-NEXT: ret388;389; ZVFBFA-LABEL: vfneg_vv_nxv2f16_unmasked:390; ZVFBFA: # %bb.0:391; ZVFBFA-NEXT: lui a1, 8392; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf2, ta, ma393; ZVFBFA-NEXT: vxor.vx v8, v8, a1394; ZVFBFA-NEXT: ret395 %v = call <vscale x 2 x half> @llvm.vp.fneg.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)396 ret <vscale x 2 x half> %v397}398 399define <vscale x 4 x half> @vfneg_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {400; ZVFH-LABEL: vfneg_vv_nxv4f16:401; ZVFH: # %bb.0:402; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma403; ZVFH-NEXT: vfneg.v v8, v8, v0.t404; ZVFH-NEXT: ret405;406; ZVFHMIN-LABEL: vfneg_vv_nxv4f16:407; ZVFHMIN: # %bb.0:408; ZVFHMIN-NEXT: lui a1, 8409; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma410; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t411; ZVFHMIN-NEXT: ret412;413; ZVFBFA-LABEL: vfneg_vv_nxv4f16:414; ZVFBFA: # %bb.0:415; ZVFBFA-NEXT: lui a1, 8416; ZVFBFA-NEXT: vsetvli zero, a0, e16, m1, ta, ma417; ZVFBFA-NEXT: vxor.vx v8, v8, a1, v0.t418; ZVFBFA-NEXT: ret419 %v = call <vscale x 4 x half> @llvm.vp.fneg.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 %evl)420 ret <vscale x 4 x half> %v421}422 423define <vscale x 4 x half> @vfneg_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, i32 zeroext %evl) {424; ZVFH-LABEL: vfneg_vv_nxv4f16_unmasked:425; ZVFH: # %bb.0:426; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma427; ZVFH-NEXT: vfneg.v v8, v8428; ZVFH-NEXT: ret429;430; ZVFHMIN-LABEL: vfneg_vv_nxv4f16_unmasked:431; ZVFHMIN: # %bb.0:432; ZVFHMIN-NEXT: lui a1, 8433; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma434; ZVFHMIN-NEXT: vxor.vx v8, v8, a1435; ZVFHMIN-NEXT: ret436;437; ZVFBFA-LABEL: vfneg_vv_nxv4f16_unmasked:438; ZVFBFA: # %bb.0:439; ZVFBFA-NEXT: lui a1, 8440; ZVFBFA-NEXT: vsetvli zero, a0, e16, m1, ta, ma441; ZVFBFA-NEXT: vxor.vx v8, v8, a1442; ZVFBFA-NEXT: ret443 %v = call <vscale x 4 x half> @llvm.vp.fneg.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)444 ret <vscale x 4 x half> %v445}446 447define <vscale x 8 x half> @vfneg_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {448; ZVFH-LABEL: vfneg_vv_nxv8f16:449; ZVFH: # %bb.0:450; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma451; ZVFH-NEXT: vfneg.v v8, v8, v0.t452; ZVFH-NEXT: ret453;454; ZVFHMIN-LABEL: vfneg_vv_nxv8f16:455; ZVFHMIN: # %bb.0:456; ZVFHMIN-NEXT: lui a1, 8457; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma458; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t459; ZVFHMIN-NEXT: ret460;461; ZVFBFA-LABEL: vfneg_vv_nxv8f16:462; ZVFBFA: # %bb.0:463; ZVFBFA-NEXT: lui a1, 8464; ZVFBFA-NEXT: vsetvli zero, a0, e16, m2, ta, ma465; ZVFBFA-NEXT: vxor.vx v8, v8, a1, v0.t466; ZVFBFA-NEXT: ret467 %v = call <vscale x 8 x half> @llvm.vp.fneg.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 %evl)468 ret <vscale x 8 x half> %v469}470 471define <vscale x 8 x half> @vfneg_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, i32 zeroext %evl) {472; ZVFH-LABEL: vfneg_vv_nxv8f16_unmasked:473; ZVFH: # %bb.0:474; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma475; ZVFH-NEXT: vfneg.v v8, v8476; ZVFH-NEXT: ret477;478; ZVFHMIN-LABEL: vfneg_vv_nxv8f16_unmasked:479; ZVFHMIN: # %bb.0:480; ZVFHMIN-NEXT: lui a1, 8481; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma482; ZVFHMIN-NEXT: vxor.vx v8, v8, a1483; ZVFHMIN-NEXT: ret484;485; ZVFBFA-LABEL: vfneg_vv_nxv8f16_unmasked:486; ZVFBFA: # %bb.0:487; ZVFBFA-NEXT: lui a1, 8488; ZVFBFA-NEXT: vsetvli zero, a0, e16, m2, ta, ma489; ZVFBFA-NEXT: vxor.vx v8, v8, a1490; ZVFBFA-NEXT: ret491 %v = call <vscale x 8 x half> @llvm.vp.fneg.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)492 ret <vscale x 8 x half> %v493}494 495define <vscale x 16 x half> @vfneg_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {496; ZVFH-LABEL: vfneg_vv_nxv16f16:497; ZVFH: # %bb.0:498; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma499; ZVFH-NEXT: vfneg.v v8, v8, v0.t500; ZVFH-NEXT: ret501;502; ZVFHMIN-LABEL: vfneg_vv_nxv16f16:503; ZVFHMIN: # %bb.0:504; ZVFHMIN-NEXT: lui a1, 8505; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma506; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t507; ZVFHMIN-NEXT: ret508;509; ZVFBFA-LABEL: vfneg_vv_nxv16f16:510; ZVFBFA: # %bb.0:511; ZVFBFA-NEXT: lui a1, 8512; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma513; ZVFBFA-NEXT: vxor.vx v8, v8, a1, v0.t514; ZVFBFA-NEXT: ret515 %v = call <vscale x 16 x half> @llvm.vp.fneg.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 %evl)516 ret <vscale x 16 x half> %v517}518 519define <vscale x 16 x half> @vfneg_vv_nxv16f16_unmasked(<vscale x 16 x half> %va, i32 zeroext %evl) {520; ZVFH-LABEL: vfneg_vv_nxv16f16_unmasked:521; ZVFH: # %bb.0:522; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma523; ZVFH-NEXT: vfneg.v v8, v8524; ZVFH-NEXT: ret525;526; ZVFHMIN-LABEL: vfneg_vv_nxv16f16_unmasked:527; ZVFHMIN: # %bb.0:528; ZVFHMIN-NEXT: lui a1, 8529; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma530; ZVFHMIN-NEXT: vxor.vx v8, v8, a1531; ZVFHMIN-NEXT: ret532;533; ZVFBFA-LABEL: vfneg_vv_nxv16f16_unmasked:534; ZVFBFA: # %bb.0:535; ZVFBFA-NEXT: lui a1, 8536; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma537; ZVFBFA-NEXT: vxor.vx v8, v8, a1538; ZVFBFA-NEXT: ret539 %v = call <vscale x 16 x half> @llvm.vp.fneg.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)540 ret <vscale x 16 x half> %v541}542 543define <vscale x 32 x half> @vfneg_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {544; ZVFH-LABEL: vfneg_vv_nxv32f16:545; ZVFH: # %bb.0:546; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma547; ZVFH-NEXT: vfneg.v v8, v8, v0.t548; ZVFH-NEXT: ret549;550; ZVFHMIN-LABEL: vfneg_vv_nxv32f16:551; ZVFHMIN: # %bb.0:552; ZVFHMIN-NEXT: lui a1, 8553; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma554; ZVFHMIN-NEXT: vxor.vx v8, v8, a1, v0.t555; ZVFHMIN-NEXT: ret556;557; ZVFBFA-LABEL: vfneg_vv_nxv32f16:558; ZVFBFA: # %bb.0:559; ZVFBFA-NEXT: lui a1, 8560; ZVFBFA-NEXT: vsetvli zero, a0, e16, m8, ta, ma561; ZVFBFA-NEXT: vxor.vx v8, v8, a1, v0.t562; ZVFBFA-NEXT: ret563 %v = call <vscale x 32 x half> @llvm.vp.fneg.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)564 ret <vscale x 32 x half> %v565}566 567define <vscale x 32 x half> @vfneg_vv_nxv32f16_unmasked(<vscale x 32 x half> %va, i32 zeroext %evl) {568; ZVFH-LABEL: vfneg_vv_nxv32f16_unmasked:569; ZVFH: # %bb.0:570; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma571; ZVFH-NEXT: vfneg.v v8, v8572; ZVFH-NEXT: ret573;574; ZVFHMIN-LABEL: vfneg_vv_nxv32f16_unmasked:575; ZVFHMIN: # %bb.0:576; ZVFHMIN-NEXT: lui a1, 8577; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma578; ZVFHMIN-NEXT: vxor.vx v8, v8, a1579; ZVFHMIN-NEXT: ret580;581; ZVFBFA-LABEL: vfneg_vv_nxv32f16_unmasked:582; ZVFBFA: # %bb.0:583; ZVFBFA-NEXT: lui a1, 8584; ZVFBFA-NEXT: vsetvli zero, a0, e16, m8, ta, ma585; ZVFBFA-NEXT: vxor.vx v8, v8, a1586; ZVFBFA-NEXT: ret587 %v = call <vscale x 32 x half> @llvm.vp.fneg.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)588 ret <vscale x 32 x half> %v589}590 591define <vscale x 1 x float> @vfneg_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {592; CHECK-LABEL: vfneg_vv_nxv1f32:593; CHECK: # %bb.0:594; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma595; CHECK-NEXT: vfneg.v v8, v8, v0.t596; CHECK-NEXT: ret597 %v = call <vscale x 1 x float> @llvm.vp.fneg.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 %evl)598 ret <vscale x 1 x float> %v599}600 601define <vscale x 1 x float> @vfneg_vv_nxv1f32_unmasked(<vscale x 1 x float> %va, i32 zeroext %evl) {602; CHECK-LABEL: vfneg_vv_nxv1f32_unmasked:603; CHECK: # %bb.0:604; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma605; CHECK-NEXT: vfneg.v v8, v8606; CHECK-NEXT: ret607 %v = call <vscale x 1 x float> @llvm.vp.fneg.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)608 ret <vscale x 1 x float> %v609}610 611define <vscale x 2 x float> @vfneg_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {612; CHECK-LABEL: vfneg_vv_nxv2f32:613; CHECK: # %bb.0:614; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma615; CHECK-NEXT: vfneg.v v8, v8, v0.t616; CHECK-NEXT: ret617 %v = call <vscale x 2 x float> @llvm.vp.fneg.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)618 ret <vscale x 2 x float> %v619}620 621define <vscale x 2 x float> @vfneg_vv_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {622; CHECK-LABEL: vfneg_vv_nxv2f32_unmasked:623; CHECK: # %bb.0:624; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma625; CHECK-NEXT: vfneg.v v8, v8626; CHECK-NEXT: ret627 %v = call <vscale x 2 x float> @llvm.vp.fneg.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)628 ret <vscale x 2 x float> %v629}630 631define <vscale x 4 x float> @vfneg_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {632; CHECK-LABEL: vfneg_vv_nxv4f32:633; CHECK: # %bb.0:634; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma635; CHECK-NEXT: vfneg.v v8, v8, v0.t636; CHECK-NEXT: ret637 %v = call <vscale x 4 x float> @llvm.vp.fneg.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 %evl)638 ret <vscale x 4 x float> %v639}640 641define <vscale x 4 x float> @vfneg_vv_nxv4f32_unmasked(<vscale x 4 x float> %va, i32 zeroext %evl) {642; CHECK-LABEL: vfneg_vv_nxv4f32_unmasked:643; CHECK: # %bb.0:644; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma645; CHECK-NEXT: vfneg.v v8, v8646; CHECK-NEXT: ret647 %v = call <vscale x 4 x float> @llvm.vp.fneg.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)648 ret <vscale x 4 x float> %v649}650 651define <vscale x 8 x float> @vfneg_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {652; CHECK-LABEL: vfneg_vv_nxv8f32:653; CHECK: # %bb.0:654; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma655; CHECK-NEXT: vfneg.v v8, v8, v0.t656; CHECK-NEXT: ret657 %v = call <vscale x 8 x float> @llvm.vp.fneg.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 %evl)658 ret <vscale x 8 x float> %v659}660 661define <vscale x 8 x float> @vfneg_vv_nxv8f32_unmasked(<vscale x 8 x float> %va, i32 zeroext %evl) {662; CHECK-LABEL: vfneg_vv_nxv8f32_unmasked:663; CHECK: # %bb.0:664; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma665; CHECK-NEXT: vfneg.v v8, v8666; CHECK-NEXT: ret667 %v = call <vscale x 8 x float> @llvm.vp.fneg.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)668 ret <vscale x 8 x float> %v669}670 671define <vscale x 16 x float> @vfneg_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {672; CHECK-LABEL: vfneg_vv_nxv16f32:673; CHECK: # %bb.0:674; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma675; CHECK-NEXT: vfneg.v v8, v8, v0.t676; CHECK-NEXT: ret677 %v = call <vscale x 16 x float> @llvm.vp.fneg.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 %evl)678 ret <vscale x 16 x float> %v679}680 681define <vscale x 16 x float> @vfneg_vv_nxv16f32_unmasked(<vscale x 16 x float> %va, i32 zeroext %evl) {682; CHECK-LABEL: vfneg_vv_nxv16f32_unmasked:683; CHECK: # %bb.0:684; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma685; CHECK-NEXT: vfneg.v v8, v8686; CHECK-NEXT: ret687 %v = call <vscale x 16 x float> @llvm.vp.fneg.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)688 ret <vscale x 16 x float> %v689}690 691define <vscale x 1 x double> @vfneg_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {692; CHECK-LABEL: vfneg_vv_nxv1f64:693; CHECK: # %bb.0:694; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma695; CHECK-NEXT: vfneg.v v8, v8, v0.t696; CHECK-NEXT: ret697 %v = call <vscale x 1 x double> @llvm.vp.fneg.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 %evl)698 ret <vscale x 1 x double> %v699}700 701define <vscale x 1 x double> @vfneg_vv_nxv1f64_unmasked(<vscale x 1 x double> %va, i32 zeroext %evl) {702; CHECK-LABEL: vfneg_vv_nxv1f64_unmasked:703; CHECK: # %bb.0:704; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma705; CHECK-NEXT: vfneg.v v8, v8706; CHECK-NEXT: ret707 %v = call <vscale x 1 x double> @llvm.vp.fneg.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)708 ret <vscale x 1 x double> %v709}710 711define <vscale x 2 x double> @vfneg_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {712; CHECK-LABEL: vfneg_vv_nxv2f64:713; CHECK: # %bb.0:714; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma715; CHECK-NEXT: vfneg.v v8, v8, v0.t716; CHECK-NEXT: ret717 %v = call <vscale x 2 x double> @llvm.vp.fneg.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)718 ret <vscale x 2 x double> %v719}720 721define <vscale x 2 x double> @vfneg_vv_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {722; CHECK-LABEL: vfneg_vv_nxv2f64_unmasked:723; CHECK: # %bb.0:724; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma725; CHECK-NEXT: vfneg.v v8, v8726; CHECK-NEXT: ret727 %v = call <vscale x 2 x double> @llvm.vp.fneg.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)728 ret <vscale x 2 x double> %v729}730 731define <vscale x 4 x double> @vfneg_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {732; CHECK-LABEL: vfneg_vv_nxv4f64:733; CHECK: # %bb.0:734; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma735; CHECK-NEXT: vfneg.v v8, v8, v0.t736; CHECK-NEXT: ret737 %v = call <vscale x 4 x double> @llvm.vp.fneg.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 %evl)738 ret <vscale x 4 x double> %v739}740 741define <vscale x 4 x double> @vfneg_vv_nxv4f64_unmasked(<vscale x 4 x double> %va, i32 zeroext %evl) {742; CHECK-LABEL: vfneg_vv_nxv4f64_unmasked:743; CHECK: # %bb.0:744; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma745; CHECK-NEXT: vfneg.v v8, v8746; CHECK-NEXT: ret747 %v = call <vscale x 4 x double> @llvm.vp.fneg.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)748 ret <vscale x 4 x double> %v749}750 751define <vscale x 7 x double> @vfneg_vv_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {752; CHECK-LABEL: vfneg_vv_nxv7f64:753; CHECK: # %bb.0:754; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma755; CHECK-NEXT: vfneg.v v8, v8, v0.t756; CHECK-NEXT: ret757 %v = call <vscale x 7 x double> @llvm.vp.fneg.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)758 ret <vscale x 7 x double> %v759}760 761define <vscale x 7 x double> @vfneg_vv_nxv7f64_unmasked(<vscale x 7 x double> %va, i32 zeroext %evl) {762; CHECK-LABEL: vfneg_vv_nxv7f64_unmasked:763; CHECK: # %bb.0:764; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma765; CHECK-NEXT: vfneg.v v8, v8766; CHECK-NEXT: ret767 %v = call <vscale x 7 x double> @llvm.vp.fneg.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)768 ret <vscale x 7 x double> %v769}770 771define <vscale x 8 x double> @vfneg_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {772; CHECK-LABEL: vfneg_vv_nxv8f64:773; CHECK: # %bb.0:774; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma775; CHECK-NEXT: vfneg.v v8, v8, v0.t776; CHECK-NEXT: ret777 %v = call <vscale x 8 x double> @llvm.vp.fneg.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 %evl)778 ret <vscale x 8 x double> %v779}780 781define <vscale x 8 x double> @vfneg_vv_nxv8f64_unmasked(<vscale x 8 x double> %va, i32 zeroext %evl) {782; CHECK-LABEL: vfneg_vv_nxv8f64_unmasked:783; CHECK: # %bb.0:784; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma785; CHECK-NEXT: vfneg.v v8, v8786; CHECK-NEXT: ret787 %v = call <vscale x 8 x double> @llvm.vp.fneg.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)788 ret <vscale x 8 x double> %v789}790 791; Test splitting.792 793define <vscale x 16 x double> @vfneg_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {794; CHECK-LABEL: vfneg_vv_nxv16f64:795; CHECK: # %bb.0:796; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma797; CHECK-NEXT: vmv1r.v v24, v0798; CHECK-NEXT: csrr a1, vlenb799; CHECK-NEXT: srli a2, a1, 3800; CHECK-NEXT: sub a3, a0, a1801; CHECK-NEXT: vslidedown.vx v0, v0, a2802; CHECK-NEXT: sltu a2, a0, a3803; CHECK-NEXT: addi a2, a2, -1804; CHECK-NEXT: and a2, a2, a3805; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma806; CHECK-NEXT: vfneg.v v16, v16, v0.t807; CHECK-NEXT: bltu a0, a1, .LBB44_2808; CHECK-NEXT: # %bb.1:809; CHECK-NEXT: mv a0, a1810; CHECK-NEXT: .LBB44_2:811; CHECK-NEXT: vmv1r.v v0, v24812; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma813; CHECK-NEXT: vfneg.v v8, v8, v0.t814; CHECK-NEXT: ret815 %v = call <vscale x 16 x double> @llvm.vp.fneg.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)816 ret <vscale x 16 x double> %v817}818 819define <vscale x 16 x double> @vfneg_vv_nxv16f64_unmasked(<vscale x 16 x double> %va, i32 zeroext %evl) {820; CHECK-LABEL: vfneg_vv_nxv16f64_unmasked:821; CHECK: # %bb.0:822; CHECK-NEXT: csrr a1, vlenb823; CHECK-NEXT: sub a2, a0, a1824; CHECK-NEXT: sltu a3, a0, a2825; CHECK-NEXT: addi a3, a3, -1826; CHECK-NEXT: and a2, a3, a2827; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma828; CHECK-NEXT: vfneg.v v16, v16829; CHECK-NEXT: bltu a0, a1, .LBB45_2830; CHECK-NEXT: # %bb.1:831; CHECK-NEXT: mv a0, a1832; CHECK-NEXT: .LBB45_2:833; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma834; CHECK-NEXT: vfneg.v v8, v8835; CHECK-NEXT: ret836 %v = call <vscale x 16 x double> @llvm.vp.fneg.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)837 ret <vscale x 16 x double> %v838}839