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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s10 11define <vscale x 1 x float> @vfpext_nxv1f16_nxv1f32(<vscale x 1 x half> %va) {12;13; CHECK-LABEL: vfpext_nxv1f16_nxv1f32:14; CHECK: # %bb.0:15; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma16; CHECK-NEXT: vfwcvt.f.f.v v9, v817; CHECK-NEXT: vmv1r.v v8, v918; CHECK-NEXT: ret19 %evec = fpext <vscale x 1 x half> %va to <vscale x 1 x float>20 ret <vscale x 1 x float> %evec21}22 23define <vscale x 1 x double> @vfpext_nxv1f16_nxv1f64(<vscale x 1 x half> %va) {24;25; CHECK-LABEL: vfpext_nxv1f16_nxv1f64:26; CHECK: # %bb.0:27; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma28; CHECK-NEXT: vfwcvt.f.f.v v9, v829; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma30; CHECK-NEXT: vfwcvt.f.f.v v8, v931; CHECK-NEXT: ret32 %evec = fpext <vscale x 1 x half> %va to <vscale x 1 x double>33 ret <vscale x 1 x double> %evec34}35 36define <vscale x 2 x float> @vfpext_nxv2f16_nxv2f32(<vscale x 2 x half> %va) {37;38; CHECK-LABEL: vfpext_nxv2f16_nxv2f32:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma41; CHECK-NEXT: vfwcvt.f.f.v v9, v842; CHECK-NEXT: vmv1r.v v8, v943; CHECK-NEXT: ret44 %evec = fpext <vscale x 2 x half> %va to <vscale x 2 x float>45 ret <vscale x 2 x float> %evec46}47 48define <vscale x 2 x double> @vfpext_nxv2f16_nxv2f64(<vscale x 2 x half> %va) {49;50; CHECK-LABEL: vfpext_nxv2f16_nxv2f64:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma53; CHECK-NEXT: vfwcvt.f.f.v v10, v854; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma55; CHECK-NEXT: vfwcvt.f.f.v v8, v1056; CHECK-NEXT: ret57 %evec = fpext <vscale x 2 x half> %va to <vscale x 2 x double>58 ret <vscale x 2 x double> %evec59}60 61define <vscale x 4 x float> @vfpext_nxv4f16_nxv4f32(<vscale x 4 x half> %va) {62;63; CHECK-LABEL: vfpext_nxv4f16_nxv4f32:64; CHECK: # %bb.0:65; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma66; CHECK-NEXT: vmv1r.v v10, v867; CHECK-NEXT: vfwcvt.f.f.v v8, v1068; CHECK-NEXT: ret69 %evec = fpext <vscale x 4 x half> %va to <vscale x 4 x float>70 ret <vscale x 4 x float> %evec71}72 73define <vscale x 4 x double> @vfpext_nxv4f16_nxv4f64(<vscale x 4 x half> %va) {74;75; CHECK-LABEL: vfpext_nxv4f16_nxv4f64:76; CHECK: # %bb.0:77; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma78; CHECK-NEXT: vfwcvt.f.f.v v12, v879; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma80; CHECK-NEXT: vfwcvt.f.f.v v8, v1281; CHECK-NEXT: ret82 %evec = fpext <vscale x 4 x half> %va to <vscale x 4 x double>83 ret <vscale x 4 x double> %evec84}85 86define <vscale x 8 x float> @vfpext_nxv8f16_nxv8f32(<vscale x 8 x half> %va) {87;88; CHECK-LABEL: vfpext_nxv8f16_nxv8f32:89; CHECK: # %bb.0:90; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma91; CHECK-NEXT: vmv2r.v v12, v892; CHECK-NEXT: vfwcvt.f.f.v v8, v1293; CHECK-NEXT: ret94 %evec = fpext <vscale x 8 x half> %va to <vscale x 8 x float>95 ret <vscale x 8 x float> %evec96}97 98define <vscale x 8 x double> @vfpext_nxv8f16_nxv8f64(<vscale x 8 x half> %va) {99;100; CHECK-LABEL: vfpext_nxv8f16_nxv8f64:101; CHECK: # %bb.0:102; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma103; CHECK-NEXT: vfwcvt.f.f.v v16, v8104; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma105; CHECK-NEXT: vfwcvt.f.f.v v8, v16106; CHECK-NEXT: ret107 %evec = fpext <vscale x 8 x half> %va to <vscale x 8 x double>108 ret <vscale x 8 x double> %evec109}110 111define <vscale x 16 x float> @vfpext_nxv16f16_nxv16f32(<vscale x 16 x half> %va) {112;113; CHECK-LABEL: vfpext_nxv16f16_nxv16f32:114; CHECK: # %bb.0:115; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma116; CHECK-NEXT: vmv4r.v v16, v8117; CHECK-NEXT: vfwcvt.f.f.v v8, v16118; CHECK-NEXT: ret119 %evec = fpext <vscale x 16 x half> %va to <vscale x 16 x float>120 ret <vscale x 16 x float> %evec121}122 123define <vscale x 1 x double> @vfpext_nxv1f32_nxv1f64(<vscale x 1 x float> %va) {124;125; CHECK-LABEL: vfpext_nxv1f32_nxv1f64:126; CHECK: # %bb.0:127; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma128; CHECK-NEXT: vfwcvt.f.f.v v9, v8129; CHECK-NEXT: vmv1r.v v8, v9130; CHECK-NEXT: ret131 %evec = fpext <vscale x 1 x float> %va to <vscale x 1 x double>132 ret <vscale x 1 x double> %evec133}134 135define <vscale x 2 x double> @vfpext_nxv2f32_nxv2f64(<vscale x 2 x float> %va) {136;137; CHECK-LABEL: vfpext_nxv2f32_nxv2f64:138; CHECK: # %bb.0:139; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma140; CHECK-NEXT: vmv1r.v v10, v8141; CHECK-NEXT: vfwcvt.f.f.v v8, v10142; CHECK-NEXT: ret143 %evec = fpext <vscale x 2 x float> %va to <vscale x 2 x double>144 ret <vscale x 2 x double> %evec145}146 147define <vscale x 4 x double> @vfpext_nxv4f32_nxv4f64(<vscale x 4 x float> %va) {148;149; CHECK-LABEL: vfpext_nxv4f32_nxv4f64:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma152; CHECK-NEXT: vmv2r.v v12, v8153; CHECK-NEXT: vfwcvt.f.f.v v8, v12154; CHECK-NEXT: ret155 %evec = fpext <vscale x 4 x float> %va to <vscale x 4 x double>156 ret <vscale x 4 x double> %evec157}158 159define <vscale x 8 x double> @vfpext_nxv8f32_nxv8f64(<vscale x 8 x float> %va) {160;161; CHECK-LABEL: vfpext_nxv8f32_nxv8f64:162; CHECK: # %bb.0:163; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma164; CHECK-NEXT: vmv4r.v v16, v8165; CHECK-NEXT: vfwcvt.f.f.v v8, v16166; CHECK-NEXT: ret167 %evec = fpext <vscale x 8 x float> %va to <vscale x 8 x double>168 ret <vscale x 8 x double> %evec169}170 171define <vscale x 1 x float> @vfpext_nxv1bf16_nxv1f32(<vscale x 1 x bfloat> %va) {172;173; CHECK-LABEL: vfpext_nxv1bf16_nxv1f32:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma176; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8177; CHECK-NEXT: vmv1r.v v8, v9178; CHECK-NEXT: ret179 %evec = fpext <vscale x 1 x bfloat> %va to <vscale x 1 x float>180 ret <vscale x 1 x float> %evec181}182 183define <vscale x 1 x double> @vfpext_nxv1bf16_nxv1f64(<vscale x 1 x bfloat> %va) {184;185; CHECK-LABEL: vfpext_nxv1bf16_nxv1f64:186; CHECK: # %bb.0:187; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma188; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8189; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma190; CHECK-NEXT: vfwcvt.f.f.v v8, v9191; CHECK-NEXT: ret192 %evec = fpext <vscale x 1 x bfloat> %va to <vscale x 1 x double>193 ret <vscale x 1 x double> %evec194}195 196define <vscale x 2 x float> @vfpext_nxv2bf16_nxv2f32(<vscale x 2 x bfloat> %va) {197;198; CHECK-LABEL: vfpext_nxv2bf16_nxv2f32:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma201; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8202; CHECK-NEXT: vmv1r.v v8, v9203; CHECK-NEXT: ret204 %evec = fpext <vscale x 2 x bfloat> %va to <vscale x 2 x float>205 ret <vscale x 2 x float> %evec206}207 208define <vscale x 2 x double> @vfpext_nxv2bf16_nxv2f64(<vscale x 2 x bfloat> %va) {209;210; CHECK-LABEL: vfpext_nxv2bf16_nxv2f64:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma213; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8214; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma215; CHECK-NEXT: vfwcvt.f.f.v v8, v10216; CHECK-NEXT: ret217 %evec = fpext <vscale x 2 x bfloat> %va to <vscale x 2 x double>218 ret <vscale x 2 x double> %evec219}220 221define <vscale x 4 x float> @vfpext_nxv4bf16_nxv4f32(<vscale x 4 x bfloat> %va) {222;223; CHECK-LABEL: vfpext_nxv4bf16_nxv4f32:224; CHECK: # %bb.0:225; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma226; CHECK-NEXT: vmv1r.v v10, v8227; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10228; CHECK-NEXT: ret229 %evec = fpext <vscale x 4 x bfloat> %va to <vscale x 4 x float>230 ret <vscale x 4 x float> %evec231}232 233define <vscale x 4 x double> @vfpext_nxv4bf16_nxv4f64(<vscale x 4 x bfloat> %va) {234;235; CHECK-LABEL: vfpext_nxv4bf16_nxv4f64:236; CHECK: # %bb.0:237; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma238; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8239; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma240; CHECK-NEXT: vfwcvt.f.f.v v8, v12241; CHECK-NEXT: ret242 %evec = fpext <vscale x 4 x bfloat> %va to <vscale x 4 x double>243 ret <vscale x 4 x double> %evec244}245 246define <vscale x 8 x float> @vfpext_nxv8bf16_nxv8f32(<vscale x 8 x bfloat> %va) {247;248; CHECK-LABEL: vfpext_nxv8bf16_nxv8f32:249; CHECK: # %bb.0:250; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma251; CHECK-NEXT: vmv2r.v v12, v8252; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v12253; CHECK-NEXT: ret254 %evec = fpext <vscale x 8 x bfloat> %va to <vscale x 8 x float>255 ret <vscale x 8 x float> %evec256}257 258define <vscale x 8 x double> @vfpext_nxv8bf16_nxv8f64(<vscale x 8 x bfloat> %va) {259;260; CHECK-LABEL: vfpext_nxv8bf16_nxv8f64:261; CHECK: # %bb.0:262; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma263; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8264; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma265; CHECK-NEXT: vfwcvt.f.f.v v8, v16266; CHECK-NEXT: ret267 %evec = fpext <vscale x 8 x bfloat> %va to <vscale x 8 x double>268 ret <vscale x 8 x double> %evec269}270 271define <vscale x 16 x float> @vfpext_nxv16bf16_nxv16f32(<vscale x 16 x bfloat> %va) {272;273; CHECK-LABEL: vfpext_nxv16bf16_nxv16f32:274; CHECK: # %bb.0:275; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma276; CHECK-NEXT: vmv4r.v v16, v8277; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v16278; CHECK-NEXT: ret279 %evec = fpext <vscale x 16 x bfloat> %va to <vscale x 16 x float>280 ret <vscale x 16 x float> %evec281}282