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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s6 7define <vscale x 2 x half> @vfptrunc_nxv2f16_nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {8; CHECK-LABEL: vfptrunc_nxv2f16_nxv2f32:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma11; CHECK-NEXT: vfncvt.f.f.w v9, v8, v0.t12; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14 %v = call <vscale x 2 x half> @llvm.vp.fptrunc.nxv2f16.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x i1> %m, i32 %vl)15 ret <vscale x 2 x half> %v16}17 18define <vscale x 2 x half> @vfptrunc_nxv2f16_nxv2f32_unmasked(<vscale x 2 x float> %a, i32 zeroext %vl) {19; CHECK-LABEL: vfptrunc_nxv2f16_nxv2f32_unmasked:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma22; CHECK-NEXT: vfncvt.f.f.w v9, v823; CHECK-NEXT: vmv1r.v v8, v924; CHECK-NEXT: ret25 %v = call <vscale x 2 x half> @llvm.vp.fptrunc.nxv2f16.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)26 ret <vscale x 2 x half> %v27}28 29define <vscale x 2 x half> @vfptrunc_nxv2f16_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {30; CHECK-LABEL: vfptrunc_nxv2f16_nxv2f64:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma33; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8, v0.t34; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma35; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t36; CHECK-NEXT: ret37 %v = call <vscale x 2 x half> @llvm.vp.fptrunc.nxv2f16.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %m, i32 %vl)38 ret <vscale x 2 x half> %v39}40 41define <vscale x 2 x half> @vfptrunc_nxv2f16_nxv2f64_unmasked(<vscale x 2 x double> %a, i32 zeroext %vl) {42; CHECK-LABEL: vfptrunc_nxv2f16_nxv2f64_unmasked:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma45; CHECK-NEXT: vfncvt.rod.f.f.w v10, v846; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma47; CHECK-NEXT: vfncvt.f.f.w v8, v1048; CHECK-NEXT: ret49 %v = call <vscale x 2 x half> @llvm.vp.fptrunc.nxv2f16.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)50 ret <vscale x 2 x half> %v51}52 53define <vscale x 2 x float> @vfptrunc_nxv2f32_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {54; CHECK-LABEL: vfptrunc_nxv2f32_nxv2f64:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma57; CHECK-NEXT: vfncvt.f.f.w v10, v8, v0.t58; CHECK-NEXT: vmv.v.v v8, v1059; CHECK-NEXT: ret60 %v = call <vscale x 2 x float> @llvm.vp.fptrunc.nxv2f64.nxv2f32(<vscale x 2 x double> %a, <vscale x 2 x i1> %m, i32 %vl)61 ret <vscale x 2 x float> %v62}63 64define <vscale x 2 x float> @vfptrunc_nxv2f32_nxv2f64_unmasked(<vscale x 2 x double> %a, i32 zeroext %vl) {65; CHECK-LABEL: vfptrunc_nxv2f32_nxv2f64_unmasked:66; CHECK: # %bb.0:67; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma68; CHECK-NEXT: vfncvt.f.f.w v10, v869; CHECK-NEXT: vmv.v.v v8, v1070; CHECK-NEXT: ret71 %v = call <vscale x 2 x float> @llvm.vp.fptrunc.nxv2f64.nxv2f32(<vscale x 2 x double> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)72 ret <vscale x 2 x float> %v73}74 75define <vscale x 7 x float> @vfptrunc_nxv7f32_nxv7f64(<vscale x 7 x double> %a, <vscale x 7 x i1> %m, i32 zeroext %vl) {76; CHECK-LABEL: vfptrunc_nxv7f32_nxv7f64:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma79; CHECK-NEXT: vfncvt.f.f.w v16, v8, v0.t80; CHECK-NEXT: vmv.v.v v8, v1681; CHECK-NEXT: ret82 %v = call <vscale x 7 x float> @llvm.vp.fptrunc.nxv7f64.nxv7f32(<vscale x 7 x double> %a, <vscale x 7 x i1> %m, i32 %vl)83 ret <vscale x 7 x float> %v84}85 86define <vscale x 16 x float> @vfptrunc_nxv16f32_nxv16f64(<vscale x 16 x double> %a, <vscale x 16 x i1> %m, i32 zeroext %vl) {87; CHECK-LABEL: vfptrunc_nxv16f32_nxv16f64:88; CHECK: # %bb.0:89; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma90; CHECK-NEXT: vmv1r.v v24, v091; CHECK-NEXT: csrr a1, vlenb92; CHECK-NEXT: srli a2, a1, 393; CHECK-NEXT: sub a3, a0, a194; CHECK-NEXT: vslidedown.vx v0, v0, a295; CHECK-NEXT: sltu a2, a0, a396; CHECK-NEXT: addi a2, a2, -197; CHECK-NEXT: and a2, a2, a398; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma99; CHECK-NEXT: vfncvt.f.f.w v28, v16, v0.t100; CHECK-NEXT: bltu a0, a1, .LBB7_2101; CHECK-NEXT: # %bb.1:102; CHECK-NEXT: mv a0, a1103; CHECK-NEXT: .LBB7_2:104; CHECK-NEXT: vmv1r.v v0, v24105; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma106; CHECK-NEXT: vfncvt.f.f.w v24, v8, v0.t107; CHECK-NEXT: vmv8r.v v8, v24108; CHECK-NEXT: ret109 %v = call <vscale x 16 x float> @llvm.vp.fptrunc.nxv16f64.nxv16f32(<vscale x 16 x double> %a, <vscale x 16 x i1> %m, i32 %vl)110 ret <vscale x 16 x float> %v111}112 113define <vscale x 32 x float> @vfptrunc_nxv32f32_nxv32f64(<vscale x 32 x double> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {114; CHECK-LABEL: vfptrunc_nxv32f32_nxv32f64:115; CHECK: # %bb.0:116; CHECK-NEXT: addi sp, sp, -16117; CHECK-NEXT: .cfi_def_cfa_offset 16118; CHECK-NEXT: csrr a1, vlenb119; CHECK-NEXT: slli a1, a1, 4120; CHECK-NEXT: sub sp, sp, a1121; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb122; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma123; CHECK-NEXT: vmv1r.v v7, v0124; CHECK-NEXT: addi a1, sp, 16125; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill126; CHECK-NEXT: csrr a1, vlenb127; CHECK-NEXT: slli a1, a1, 3128; CHECK-NEXT: add a1, sp, a1129; CHECK-NEXT: addi a1, a1, 16130; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill131; CHECK-NEXT: csrr a1, vlenb132; CHECK-NEXT: vl8re64.v v16, (a0)133; CHECK-NEXT: srli a5, a1, 3134; CHECK-NEXT: slli a4, a1, 3135; CHECK-NEXT: slli a3, a1, 1136; CHECK-NEXT: add a6, a0, a4137; CHECK-NEXT: sub a0, a2, a3138; CHECK-NEXT: sltu a4, a2, a0139; CHECK-NEXT: addi a4, a4, -1140; CHECK-NEXT: and a0, a4, a0141; CHECK-NEXT: sub a4, a0, a1142; CHECK-NEXT: sltu a7, a0, a4143; CHECK-NEXT: addi a7, a7, -1144; CHECK-NEXT: and a4, a7, a4145; CHECK-NEXT: srli a7, a1, 2146; CHECK-NEXT: vl8re64.v v8, (a6)147; CHECK-NEXT: vslidedown.vx v24, v0, a7148; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma149; CHECK-NEXT: vslidedown.vx v6, v0, a5150; CHECK-NEXT: vslidedown.vx v0, v24, a5151; CHECK-NEXT: bltu a0, a1, .LBB8_2152; CHECK-NEXT: # %bb.1:153; CHECK-NEXT: mv a0, a1154; CHECK-NEXT: .LBB8_2:155; CHECK-NEXT: vsetvli zero, a4, e32, m4, ta, ma156; CHECK-NEXT: vfncvt.f.f.w v28, v8, v0.t157; CHECK-NEXT: vmv1r.v v0, v24158; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma159; CHECK-NEXT: vfncvt.f.f.w v24, v16, v0.t160; CHECK-NEXT: bltu a2, a3, .LBB8_4161; CHECK-NEXT: # %bb.3:162; CHECK-NEXT: mv a2, a3163; CHECK-NEXT: .LBB8_4:164; CHECK-NEXT: sub a0, a2, a1165; CHECK-NEXT: sltu a3, a2, a0166; CHECK-NEXT: addi a3, a3, -1167; CHECK-NEXT: and a0, a3, a0168; CHECK-NEXT: vmv1r.v v0, v6169; CHECK-NEXT: addi a3, sp, 16170; CHECK-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload171; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma172; CHECK-NEXT: vfncvt.f.f.w v12, v16, v0.t173; CHECK-NEXT: bltu a2, a1, .LBB8_6174; CHECK-NEXT: # %bb.5:175; CHECK-NEXT: mv a2, a1176; CHECK-NEXT: .LBB8_6:177; CHECK-NEXT: vmv1r.v v0, v7178; CHECK-NEXT: csrr a0, vlenb179; CHECK-NEXT: slli a0, a0, 3180; CHECK-NEXT: add a0, sp, a0181; CHECK-NEXT: addi a0, a0, 16182; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload183; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma184; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t185; CHECK-NEXT: vmv8r.v v16, v24186; CHECK-NEXT: csrr a0, vlenb187; CHECK-NEXT: slli a0, a0, 4188; CHECK-NEXT: add sp, sp, a0189; CHECK-NEXT: .cfi_def_cfa sp, 16190; CHECK-NEXT: addi sp, sp, 16191; CHECK-NEXT: .cfi_def_cfa_offset 0192; CHECK-NEXT: ret193 %v = call <vscale x 32 x float> @llvm.vp.fptrunc.nxv32f64.nxv32f32(<vscale x 32 x double> %a, <vscale x 32 x i1> %m, i32 %vl)194 ret <vscale x 32 x float> %v195}196 197define <vscale x 2 x bfloat> @vfptrunc_nxv2bf16_nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {198; CHECK-LABEL: vfptrunc_nxv2bf16_nxv2f32:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma201; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8, v0.t202; CHECK-NEXT: vmv1r.v v8, v9203; CHECK-NEXT: ret204 %v = call <vscale x 2 x bfloat> @llvm.vp.fptrunc.nxv2bf16.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x i1> %m, i32 %vl)205 ret <vscale x 2 x bfloat> %v206}207 208define <vscale x 2 x bfloat> @vfptrunc_nxv2bf16_nxv2f32_unmasked(<vscale x 2 x float> %a, i32 zeroext %vl) {209; CHECK-LABEL: vfptrunc_nxv2bf16_nxv2f32_unmasked:210; CHECK: # %bb.0:211; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma212; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8213; CHECK-NEXT: vmv1r.v v8, v9214; CHECK-NEXT: ret215 %v = call <vscale x 2 x bfloat> @llvm.vp.fptrunc.nxv2bf16.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)216 ret <vscale x 2 x bfloat> %v217}218 219define <vscale x 2 x bfloat> @vfptrunc_nxv2bf16_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {220; CHECK-LABEL: vfptrunc_nxv2bf16_nxv2f64:221; CHECK: # %bb.0:222; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma223; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8, v0.t224; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma225; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t226; CHECK-NEXT: ret227 %v = call <vscale x 2 x bfloat> @llvm.vp.fptrunc.nxv2bf16.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %m, i32 %vl)228 ret <vscale x 2 x bfloat> %v229}230 231define <vscale x 2 x bfloat> @vfptrunc_nxv2bf16_nxv2f64_unmasked(<vscale x 2 x double> %a, i32 zeroext %vl) {232; CHECK-LABEL: vfptrunc_nxv2bf16_nxv2f64_unmasked:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma235; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8236; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma237; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10238; CHECK-NEXT: ret239 %v = call <vscale x 2 x bfloat> @llvm.vp.fptrunc.nxv2bf16.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)240 ret <vscale x 2 x bfloat> %v241}242