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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x bfloat> @intrinsic_vfrec7_v_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfrec7_v_nxv1bf16_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma12; CHECK-NEXT: vfrec7.v v8, v813; CHECK-NEXT: fsrm a114; CHECK-NEXT: ret15entry:16 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.nxv1bf16(17 <vscale x 1 x bfloat> poison,18 <vscale x 1 x bfloat> %0,19 iXLen 0, iXLen %1)20 21 ret <vscale x 1 x bfloat> %a22}23 24define <vscale x 1 x bfloat> @intrinsic_vfrec7_mask_v_nxv1bf16_nxv1bf16(<vscale x 1 x i1> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {25; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1bf16_nxv1bf16:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: fsrmi a1, 028; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu29; CHECK-NEXT: vfrec7.v v8, v9, v0.t30; CHECK-NEXT: fsrm a131; CHECK-NEXT: ret32entry:33 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfrec7.mask.nxv1bf16(34 <vscale x 1 x bfloat> %1,35 <vscale x 1 x bfloat> %2,36 <vscale x 1 x i1> %0,37 iXLen 0, iXLen %3, iXLen 1)38 39 ret <vscale x 1 x bfloat> %a40}41 42define <vscale x 2 x bfloat> @intrinsic_vfrec7_v_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1) nounwind {43; CHECK-LABEL: intrinsic_vfrec7_v_nxv2bf16_nxv2bf16:44; CHECK: # %bb.0: # %entry45; CHECK-NEXT: fsrmi a1, 046; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma47; CHECK-NEXT: vfrec7.v v8, v848; CHECK-NEXT: fsrm a149; CHECK-NEXT: ret50entry:51 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.nxv2bf16(52 <vscale x 2 x bfloat> poison,53 <vscale x 2 x bfloat> %0,54 iXLen 0, iXLen %1)55 56 ret <vscale x 2 x bfloat> %a57}58 59define <vscale x 2 x bfloat> @intrinsic_vfrec7_mask_v_nxv2bf16_nxv2bf16(<vscale x 2 x i1> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {60; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv2bf16_nxv2bf16:61; CHECK: # %bb.0: # %entry62; CHECK-NEXT: fsrmi a1, 063; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu64; CHECK-NEXT: vfrec7.v v8, v9, v0.t65; CHECK-NEXT: fsrm a166; CHECK-NEXT: ret67entry:68 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfrec7.mask.nxv2bf16(69 <vscale x 2 x bfloat> %1,70 <vscale x 2 x bfloat> %2,71 <vscale x 2 x i1> %0,72 iXLen 0, iXLen %3, iXLen 1)73 74 ret <vscale x 2 x bfloat> %a75}76 77define <vscale x 4 x bfloat> @intrinsic_vfrec7_v_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1) nounwind {78; CHECK-LABEL: intrinsic_vfrec7_v_nxv4bf16_nxv4bf16:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: fsrmi a1, 081; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma82; CHECK-NEXT: vfrec7.v v8, v883; CHECK-NEXT: fsrm a184; CHECK-NEXT: ret85entry:86 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.nxv4bf16(87 <vscale x 4 x bfloat> poison,88 <vscale x 4 x bfloat> %0,89 iXLen 0, iXLen %1)90 91 ret <vscale x 4 x bfloat> %a92}93 94define <vscale x 4 x bfloat> @intrinsic_vfrec7_mask_v_nxv4bf16_nxv4bf16(<vscale x 4 x i1> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, iXLen %3) nounwind {95; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv4bf16_nxv4bf16:96; CHECK: # %bb.0: # %entry97; CHECK-NEXT: fsrmi a1, 098; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu99; CHECK-NEXT: vfrec7.v v8, v9, v0.t100; CHECK-NEXT: fsrm a1101; CHECK-NEXT: ret102entry:103 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfrec7.mask.nxv4bf16(104 <vscale x 4 x bfloat> %1,105 <vscale x 4 x bfloat> %2,106 <vscale x 4 x i1> %0,107 iXLen 0, iXLen %3, iXLen 1)108 109 ret <vscale x 4 x bfloat> %a110}111 112define <vscale x 8 x bfloat> @intrinsic_vfrec7_v_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1) nounwind {113; CHECK-LABEL: intrinsic_vfrec7_v_nxv8bf16_nxv8bf16:114; CHECK: # %bb.0: # %entry115; CHECK-NEXT: fsrmi a1, 0116; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma117; CHECK-NEXT: vfrec7.v v8, v8118; CHECK-NEXT: fsrm a1119; CHECK-NEXT: ret120entry:121 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.nxv8bf16(122 <vscale x 8 x bfloat> poison,123 <vscale x 8 x bfloat> %0,124 iXLen 0, iXLen %1)125 126 ret <vscale x 8 x bfloat> %a127}128 129define <vscale x 8 x bfloat> @intrinsic_vfrec7_mask_v_nxv8bf16_nxv8bf16(<vscale x 8 x i1> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {130; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv8bf16_nxv8bf16:131; CHECK: # %bb.0: # %entry132; CHECK-NEXT: fsrmi a1, 0133; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu134; CHECK-NEXT: vfrec7.v v8, v10, v0.t135; CHECK-NEXT: fsrm a1136; CHECK-NEXT: ret137entry:138 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfrec7.mask.nxv8bf16(139 <vscale x 8 x bfloat> %1,140 <vscale x 8 x bfloat> %2,141 <vscale x 8 x i1> %0,142 iXLen 0, iXLen %3, iXLen 1)143 144 ret <vscale x 8 x bfloat> %a145}146 147define <vscale x 16 x bfloat> @intrinsic_vfrec7_v_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1) nounwind {148; CHECK-LABEL: intrinsic_vfrec7_v_nxv16bf16_nxv16bf16:149; CHECK: # %bb.0: # %entry150; CHECK-NEXT: fsrmi a1, 0151; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma152; CHECK-NEXT: vfrec7.v v8, v8153; CHECK-NEXT: fsrm a1154; CHECK-NEXT: ret155entry:156 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.nxv16bf16(157 <vscale x 16 x bfloat> poison,158 <vscale x 16 x bfloat> %0,159 iXLen 0, iXLen %1)160 161 ret <vscale x 16 x bfloat> %a162}163 164define <vscale x 16 x bfloat> @intrinsic_vfrec7_mask_v_nxv16bf16_nxv16bf16(<vscale x 16 x i1> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {165; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv16bf16_nxv16bf16:166; CHECK: # %bb.0: # %entry167; CHECK-NEXT: fsrmi a1, 0168; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu169; CHECK-NEXT: vfrec7.v v8, v12, v0.t170; CHECK-NEXT: fsrm a1171; CHECK-NEXT: ret172entry:173 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfrec7.mask.nxv16bf16(174 <vscale x 16 x bfloat> %1,175 <vscale x 16 x bfloat> %2,176 <vscale x 16 x i1> %0,177 iXLen 0, iXLen %3, iXLen 1)178 179 ret <vscale x 16 x bfloat> %a180}181 182define <vscale x 32 x bfloat> @intrinsic_vfrec7_v_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, iXLen %1) nounwind {183; CHECK-LABEL: intrinsic_vfrec7_v_nxv32bf16_nxv32bf16:184; CHECK: # %bb.0: # %entry185; CHECK-NEXT: fsrmi a1, 0186; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma187; CHECK-NEXT: vfrec7.v v8, v8188; CHECK-NEXT: fsrm a1189; CHECK-NEXT: ret190entry:191 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.nxv32bf16(192 <vscale x 32 x bfloat> poison,193 <vscale x 32 x bfloat> %0,194 iXLen 0, iXLen %1)195 196 ret <vscale x 32 x bfloat> %a197}198 199define <vscale x 32 x bfloat> @intrinsic_vfrec7_mask_v_nxv32bf16_nxv32bf16(<vscale x 32 x i1> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, iXLen %3) nounwind {200; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv32bf16_nxv32bf16:201; CHECK: # %bb.0: # %entry202; CHECK-NEXT: fsrmi a1, 0203; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, mu204; CHECK-NEXT: vfrec7.v v8, v16, v0.t205; CHECK-NEXT: fsrm a1206; CHECK-NEXT: ret207entry:208 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfrec7.mask.nxv32bf16(209 <vscale x 32 x bfloat> %1,210 <vscale x 32 x bfloat> %2,211 <vscale x 32 x i1> %0,212 iXLen 0, iXLen %3, iXLen 1)213 214 ret <vscale x 32 x bfloat> %a215}216 217