531 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x half> @intrinsic_vfrec7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f16_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma12; CHECK-NEXT: vfrec7.v v8, v813; CHECK-NEXT: fsrm a114; CHECK-NEXT: ret15entry:16 %a = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16(17 <vscale x 1 x half> poison,18 <vscale x 1 x half> %0,19 iXLen 0, iXLen %1)20 21 ret <vscale x 1 x half> %a22}23 24define <vscale x 1 x half> @intrinsic_vfrec7_mask_v_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {25; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1f16_nxv1f16:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: fsrmi a1, 028; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu29; CHECK-NEXT: vfrec7.v v8, v9, v0.t30; CHECK-NEXT: fsrm a131; CHECK-NEXT: ret32entry:33 %a = call <vscale x 1 x half> @llvm.riscv.vfrec7.mask.nxv1f16(34 <vscale x 1 x half> %1,35 <vscale x 1 x half> %2,36 <vscale x 1 x i1> %0,37 iXLen 0, iXLen %3, iXLen 1)38 39 ret <vscale x 1 x half> %a40}41 42define <vscale x 2 x half> @intrinsic_vfrec7_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {43; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f16_nxv2f16:44; CHECK: # %bb.0: # %entry45; CHECK-NEXT: fsrmi a1, 046; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma47; CHECK-NEXT: vfrec7.v v8, v848; CHECK-NEXT: fsrm a149; CHECK-NEXT: ret50entry:51 %a = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16(52 <vscale x 2 x half> poison,53 <vscale x 2 x half> %0,54 iXLen 0, iXLen %1)55 56 ret <vscale x 2 x half> %a57}58 59define <vscale x 2 x half> @intrinsic_vfrec7_mask_v_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind {60; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv2f16_nxv2f16:61; CHECK: # %bb.0: # %entry62; CHECK-NEXT: fsrmi a1, 063; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu64; CHECK-NEXT: vfrec7.v v8, v9, v0.t65; CHECK-NEXT: fsrm a166; CHECK-NEXT: ret67entry:68 %a = call <vscale x 2 x half> @llvm.riscv.vfrec7.mask.nxv2f16(69 <vscale x 2 x half> %1,70 <vscale x 2 x half> %2,71 <vscale x 2 x i1> %0,72 iXLen 0, iXLen %3, iXLen 1)73 74 ret <vscale x 2 x half> %a75}76 77define <vscale x 4 x half> @intrinsic_vfrec7_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {78; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f16_nxv4f16:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: fsrmi a1, 081; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma82; CHECK-NEXT: vfrec7.v v8, v883; CHECK-NEXT: fsrm a184; CHECK-NEXT: ret85entry:86 %a = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16(87 <vscale x 4 x half> poison,88 <vscale x 4 x half> %0,89 iXLen 0, iXLen %1)90 91 ret <vscale x 4 x half> %a92}93 94define <vscale x 4 x half> @intrinsic_vfrec7_mask_v_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {95; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv4f16_nxv4f16:96; CHECK: # %bb.0: # %entry97; CHECK-NEXT: fsrmi a1, 098; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu99; CHECK-NEXT: vfrec7.v v8, v9, v0.t100; CHECK-NEXT: fsrm a1101; CHECK-NEXT: ret102entry:103 %a = call <vscale x 4 x half> @llvm.riscv.vfrec7.mask.nxv4f16(104 <vscale x 4 x half> %1,105 <vscale x 4 x half> %2,106 <vscale x 4 x i1> %0,107 iXLen 0, iXLen %3, iXLen 1)108 109 ret <vscale x 4 x half> %a110}111 112define <vscale x 8 x half> @intrinsic_vfrec7_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {113; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f16_nxv8f16:114; CHECK: # %bb.0: # %entry115; CHECK-NEXT: fsrmi a1, 0116; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma117; CHECK-NEXT: vfrec7.v v8, v8118; CHECK-NEXT: fsrm a1119; CHECK-NEXT: ret120entry:121 %a = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16(122 <vscale x 8 x half> poison,123 <vscale x 8 x half> %0,124 iXLen 0, iXLen %1)125 126 ret <vscale x 8 x half> %a127}128 129define <vscale x 8 x half> @intrinsic_vfrec7_mask_v_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind {130; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv8f16_nxv8f16:131; CHECK: # %bb.0: # %entry132; CHECK-NEXT: fsrmi a1, 0133; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu134; CHECK-NEXT: vfrec7.v v8, v10, v0.t135; CHECK-NEXT: fsrm a1136; CHECK-NEXT: ret137entry:138 %a = call <vscale x 8 x half> @llvm.riscv.vfrec7.mask.nxv8f16(139 <vscale x 8 x half> %1,140 <vscale x 8 x half> %2,141 <vscale x 8 x i1> %0,142 iXLen 0, iXLen %3, iXLen 1)143 144 ret <vscale x 8 x half> %a145}146 147define <vscale x 16 x half> @intrinsic_vfrec7_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {148; CHECK-LABEL: intrinsic_vfrec7_v_nxv16f16_nxv16f16:149; CHECK: # %bb.0: # %entry150; CHECK-NEXT: fsrmi a1, 0151; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma152; CHECK-NEXT: vfrec7.v v8, v8153; CHECK-NEXT: fsrm a1154; CHECK-NEXT: ret155entry:156 %a = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16(157 <vscale x 16 x half> poison,158 <vscale x 16 x half> %0,159 iXLen 0, iXLen %1)160 161 ret <vscale x 16 x half> %a162}163 164define <vscale x 16 x half> @intrinsic_vfrec7_mask_v_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {165; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv16f16_nxv16f16:166; CHECK: # %bb.0: # %entry167; CHECK-NEXT: fsrmi a1, 0168; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu169; CHECK-NEXT: vfrec7.v v8, v12, v0.t170; CHECK-NEXT: fsrm a1171; CHECK-NEXT: ret172entry:173 %a = call <vscale x 16 x half> @llvm.riscv.vfrec7.mask.nxv16f16(174 <vscale x 16 x half> %1,175 <vscale x 16 x half> %2,176 <vscale x 16 x i1> %0,177 iXLen 0, iXLen %3, iXLen 1)178 179 ret <vscale x 16 x half> %a180}181 182define <vscale x 32 x half> @intrinsic_vfrec7_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {183; CHECK-LABEL: intrinsic_vfrec7_v_nxv32f16_nxv32f16:184; CHECK: # %bb.0: # %entry185; CHECK-NEXT: fsrmi a1, 0186; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma187; CHECK-NEXT: vfrec7.v v8, v8188; CHECK-NEXT: fsrm a1189; CHECK-NEXT: ret190entry:191 %a = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16(192 <vscale x 32 x half> poison,193 <vscale x 32 x half> %0,194 iXLen 0, iXLen %1)195 196 ret <vscale x 32 x half> %a197}198 199define <vscale x 32 x half> @intrinsic_vfrec7_mask_v_nxv32f16_nxv32f16(<vscale x 32 x i1> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, iXLen %3) nounwind {200; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv32f16_nxv32f16:201; CHECK: # %bb.0: # %entry202; CHECK-NEXT: fsrmi a1, 0203; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu204; CHECK-NEXT: vfrec7.v v8, v16, v0.t205; CHECK-NEXT: fsrm a1206; CHECK-NEXT: ret207entry:208 %a = call <vscale x 32 x half> @llvm.riscv.vfrec7.mask.nxv32f16(209 <vscale x 32 x half> %1,210 <vscale x 32 x half> %2,211 <vscale x 32 x i1> %0,212 iXLen 0, iXLen %3, iXLen 1)213 214 ret <vscale x 32 x half> %a215}216 217define <vscale x 1 x float> @intrinsic_vfrec7_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {218; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f32_nxv1f32:219; CHECK: # %bb.0: # %entry220; CHECK-NEXT: fsrmi a1, 0221; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma222; CHECK-NEXT: vfrec7.v v8, v8223; CHECK-NEXT: fsrm a1224; CHECK-NEXT: ret225entry:226 %a = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32(227 <vscale x 1 x float> poison,228 <vscale x 1 x float> %0,229 iXLen 0, iXLen %1)230 231 ret <vscale x 1 x float> %a232}233 234define <vscale x 1 x float> @intrinsic_vfrec7_mask_v_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {235; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1f32_nxv1f32:236; CHECK: # %bb.0: # %entry237; CHECK-NEXT: fsrmi a1, 0238; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu239; CHECK-NEXT: vfrec7.v v8, v9, v0.t240; CHECK-NEXT: fsrm a1241; CHECK-NEXT: ret242entry:243 %a = call <vscale x 1 x float> @llvm.riscv.vfrec7.mask.nxv1f32(244 <vscale x 1 x float> %1,245 <vscale x 1 x float> %2,246 <vscale x 1 x i1> %0,247 iXLen 0, iXLen %3, iXLen 1)248 249 ret <vscale x 1 x float> %a250}251 252define <vscale x 2 x float> @intrinsic_vfrec7_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {253; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f32_nxv2f32:254; CHECK: # %bb.0: # %entry255; CHECK-NEXT: fsrmi a1, 0256; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma257; CHECK-NEXT: vfrec7.v v8, v8258; CHECK-NEXT: fsrm a1259; CHECK-NEXT: ret260entry:261 %a = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32(262 <vscale x 2 x float> poison,263 <vscale x 2 x float> %0,264 iXLen 0, iXLen %1)265 266 ret <vscale x 2 x float> %a267}268 269define <vscale x 2 x float> @intrinsic_vfrec7_mask_v_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {270; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv2f32_nxv2f32:271; CHECK: # %bb.0: # %entry272; CHECK-NEXT: fsrmi a1, 0273; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu274; CHECK-NEXT: vfrec7.v v8, v9, v0.t275; CHECK-NEXT: fsrm a1276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 2 x float> @llvm.riscv.vfrec7.mask.nxv2f32(279 <vscale x 2 x float> %1,280 <vscale x 2 x float> %2,281 <vscale x 2 x i1> %0,282 iXLen 0, iXLen %3, iXLen 1)283 284 ret <vscale x 2 x float> %a285}286 287define <vscale x 4 x float> @intrinsic_vfrec7_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {288; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f32_nxv4f32:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: fsrmi a1, 0291; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma292; CHECK-NEXT: vfrec7.v v8, v8293; CHECK-NEXT: fsrm a1294; CHECK-NEXT: ret295entry:296 %a = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32(297 <vscale x 4 x float> poison,298 <vscale x 4 x float> %0,299 iXLen 0, iXLen %1)300 301 ret <vscale x 4 x float> %a302}303 304define <vscale x 4 x float> @intrinsic_vfrec7_mask_v_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind {305; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv4f32_nxv4f32:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: fsrmi a1, 0308; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu309; CHECK-NEXT: vfrec7.v v8, v10, v0.t310; CHECK-NEXT: fsrm a1311; CHECK-NEXT: ret312entry:313 %a = call <vscale x 4 x float> @llvm.riscv.vfrec7.mask.nxv4f32(314 <vscale x 4 x float> %1,315 <vscale x 4 x float> %2,316 <vscale x 4 x i1> %0,317 iXLen 0, iXLen %3, iXLen 1)318 319 ret <vscale x 4 x float> %a320}321 322define <vscale x 8 x float> @intrinsic_vfrec7_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {323; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f32_nxv8f32:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: fsrmi a1, 0326; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma327; CHECK-NEXT: vfrec7.v v8, v8328; CHECK-NEXT: fsrm a1329; CHECK-NEXT: ret330entry:331 %a = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32(332 <vscale x 8 x float> poison,333 <vscale x 8 x float> %0,334 iXLen 0, iXLen %1)335 336 ret <vscale x 8 x float> %a337}338 339define <vscale x 8 x float> @intrinsic_vfrec7_mask_v_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind {340; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv8f32_nxv8f32:341; CHECK: # %bb.0: # %entry342; CHECK-NEXT: fsrmi a1, 0343; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu344; CHECK-NEXT: vfrec7.v v8, v12, v0.t345; CHECK-NEXT: fsrm a1346; CHECK-NEXT: ret347entry:348 %a = call <vscale x 8 x float> @llvm.riscv.vfrec7.mask.nxv8f32(349 <vscale x 8 x float> %1,350 <vscale x 8 x float> %2,351 <vscale x 8 x i1> %0,352 iXLen 0, iXLen %3, iXLen 1)353 354 ret <vscale x 8 x float> %a355}356 357define <vscale x 16 x float> @intrinsic_vfrec7_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {358; CHECK-LABEL: intrinsic_vfrec7_v_nxv16f32_nxv16f32:359; CHECK: # %bb.0: # %entry360; CHECK-NEXT: fsrmi a1, 0361; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma362; CHECK-NEXT: vfrec7.v v8, v8363; CHECK-NEXT: fsrm a1364; CHECK-NEXT: ret365entry:366 %a = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32(367 <vscale x 16 x float> poison,368 <vscale x 16 x float> %0,369 iXLen 0, iXLen %1)370 371 ret <vscale x 16 x float> %a372}373 374define <vscale x 16 x float> @intrinsic_vfrec7_mask_v_nxv16f32_nxv16f32(<vscale x 16 x i1> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, iXLen %3) nounwind {375; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv16f32_nxv16f32:376; CHECK: # %bb.0: # %entry377; CHECK-NEXT: fsrmi a1, 0378; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu379; CHECK-NEXT: vfrec7.v v8, v16, v0.t380; CHECK-NEXT: fsrm a1381; CHECK-NEXT: ret382entry:383 %a = call <vscale x 16 x float> @llvm.riscv.vfrec7.mask.nxv16f32(384 <vscale x 16 x float> %1,385 <vscale x 16 x float> %2,386 <vscale x 16 x i1> %0,387 iXLen 0, iXLen %3, iXLen 1)388 389 ret <vscale x 16 x float> %a390}391 392define <vscale x 1 x double> @intrinsic_vfrec7_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {393; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f64_nxv1f64:394; CHECK: # %bb.0: # %entry395; CHECK-NEXT: fsrmi a1, 0396; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma397; CHECK-NEXT: vfrec7.v v8, v8398; CHECK-NEXT: fsrm a1399; CHECK-NEXT: ret400entry:401 %a = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64(402 <vscale x 1 x double> poison,403 <vscale x 1 x double> %0,404 iXLen 0, iXLen %1)405 406 ret <vscale x 1 x double> %a407}408 409define <vscale x 1 x double> @intrinsic_vfrec7_mask_v_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {410; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1f64_nxv1f64:411; CHECK: # %bb.0: # %entry412; CHECK-NEXT: fsrmi a1, 0413; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu414; CHECK-NEXT: vfrec7.v v8, v9, v0.t415; CHECK-NEXT: fsrm a1416; CHECK-NEXT: ret417entry:418 %a = call <vscale x 1 x double> @llvm.riscv.vfrec7.mask.nxv1f64(419 <vscale x 1 x double> %1,420 <vscale x 1 x double> %2,421 <vscale x 1 x i1> %0,422 iXLen 0, iXLen %3, iXLen 1)423 424 ret <vscale x 1 x double> %a425}426 427define <vscale x 2 x double> @intrinsic_vfrec7_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {428; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f64_nxv2f64:429; CHECK: # %bb.0: # %entry430; CHECK-NEXT: fsrmi a1, 0431; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma432; CHECK-NEXT: vfrec7.v v8, v8433; CHECK-NEXT: fsrm a1434; CHECK-NEXT: ret435entry:436 %a = call <vscale x 2 x double> @llvm.riscv.vfrec7.nxv2f64(437 <vscale x 2 x double> poison,438 <vscale x 2 x double> %0,439 iXLen 0, iXLen %1)440 441 ret <vscale x 2 x double> %a442}443 444define <vscale x 2 x double> @intrinsic_vfrec7_mask_v_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind {445; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv2f64_nxv2f64:446; CHECK: # %bb.0: # %entry447; CHECK-NEXT: fsrmi a1, 0448; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu449; CHECK-NEXT: vfrec7.v v8, v10, v0.t450; CHECK-NEXT: fsrm a1451; CHECK-NEXT: ret452entry:453 %a = call <vscale x 2 x double> @llvm.riscv.vfrec7.mask.nxv2f64(454 <vscale x 2 x double> %1,455 <vscale x 2 x double> %2,456 <vscale x 2 x i1> %0,457 iXLen 0, iXLen %3, iXLen 1)458 459 ret <vscale x 2 x double> %a460}461 462define <vscale x 4 x double> @intrinsic_vfrec7_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {463; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f64_nxv4f64:464; CHECK: # %bb.0: # %entry465; CHECK-NEXT: fsrmi a1, 0466; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma467; CHECK-NEXT: vfrec7.v v8, v8468; CHECK-NEXT: fsrm a1469; CHECK-NEXT: ret470entry:471 %a = call <vscale x 4 x double> @llvm.riscv.vfrec7.nxv4f64(472 <vscale x 4 x double> poison,473 <vscale x 4 x double> %0,474 iXLen 0, iXLen %1)475 476 ret <vscale x 4 x double> %a477}478 479define <vscale x 4 x double> @intrinsic_vfrec7_mask_v_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind {480; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv4f64_nxv4f64:481; CHECK: # %bb.0: # %entry482; CHECK-NEXT: fsrmi a1, 0483; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu484; CHECK-NEXT: vfrec7.v v8, v12, v0.t485; CHECK-NEXT: fsrm a1486; CHECK-NEXT: ret487entry:488 %a = call <vscale x 4 x double> @llvm.riscv.vfrec7.mask.nxv4f64(489 <vscale x 4 x double> %1,490 <vscale x 4 x double> %2,491 <vscale x 4 x i1> %0,492 iXLen 0, iXLen %3, iXLen 1)493 494 ret <vscale x 4 x double> %a495}496 497define <vscale x 8 x double> @intrinsic_vfrec7_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {498; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f64_nxv8f64:499; CHECK: # %bb.0: # %entry500; CHECK-NEXT: fsrmi a1, 0501; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma502; CHECK-NEXT: vfrec7.v v8, v8503; CHECK-NEXT: fsrm a1504; CHECK-NEXT: ret505entry:506 %a = call <vscale x 8 x double> @llvm.riscv.vfrec7.nxv8f64(507 <vscale x 8 x double> poison,508 <vscale x 8 x double> %0,509 iXLen 0, iXLen %1)510 511 ret <vscale x 8 x double> %a512}513 514define <vscale x 8 x double> @intrinsic_vfrec7_mask_v_nxv8f64_nxv8f64(<vscale x 8 x i1> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, iXLen %3) nounwind {515; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv8f64_nxv8f64:516; CHECK: # %bb.0: # %entry517; CHECK-NEXT: fsrmi a1, 0518; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu519; CHECK-NEXT: vfrec7.v v8, v16, v0.t520; CHECK-NEXT: fsrm a1521; CHECK-NEXT: ret522entry:523 %a = call <vscale x 8 x double> @llvm.riscv.vfrec7.mask.nxv8f64(524 <vscale x 8 x double> %1,525 <vscale x 8 x double> %2,526 <vscale x 8 x i1> %0,527 iXLen 0, iXLen %3, iXLen 1)528 529 ret <vscale x 8 x double> %a530}531