561 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma12; CHECK-NEXT: vfredusum.vs v8, v9, v1013; CHECK-NEXT: fsrm a114; CHECK-NEXT: ret15entry:16 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16(17 <vscale x 4 x half> %0,18 <vscale x 1 x half> %1,19 <vscale x 4 x half> %2,20 iXLen 0, iXLen %3)21 22 ret <vscale x 4 x half> %a23}24 25define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {26; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv1f16_nxv4f16:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: fsrmi a1, 029; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma30; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t31; CHECK-NEXT: fsrm a132; CHECK-NEXT: ret33entry:34 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.nxv1i1(35 <vscale x 4 x half> %0,36 <vscale x 1 x half> %1,37 <vscale x 4 x half> %2,38 <vscale x 1 x i1> %3,39 iXLen 0, iXLen %4)40 41 ret <vscale x 4 x half> %a42}43 44define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {45; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv2f16_nxv4f16:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: fsrmi a1, 048; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma49; CHECK-NEXT: vfredusum.vs v8, v9, v1050; CHECK-NEXT: fsrm a151; CHECK-NEXT: ret52entry:53 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16(54 <vscale x 4 x half> %0,55 <vscale x 2 x half> %1,56 <vscale x 4 x half> %2,57 iXLen 0, iXLen %3)58 59 ret <vscale x 4 x half> %a60}61 62define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {63; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv2f16_nxv4f16:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: fsrmi a1, 066; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma67; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t68; CHECK-NEXT: fsrm a169; CHECK-NEXT: ret70entry:71 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.nxv2i1(72 <vscale x 4 x half> %0,73 <vscale x 2 x half> %1,74 <vscale x 4 x half> %2,75 <vscale x 2 x i1> %3,76 iXLen 0, iXLen %4)77 78 ret <vscale x 4 x half> %a79}80 81define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {82; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv4f16_nxv4f16:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: fsrmi a1, 085; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma86; CHECK-NEXT: vfredusum.vs v8, v9, v1087; CHECK-NEXT: fsrm a188; CHECK-NEXT: ret89entry:90 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16(91 <vscale x 4 x half> %0,92 <vscale x 4 x half> %1,93 <vscale x 4 x half> %2,94 iXLen 0, iXLen %3)95 96 ret <vscale x 4 x half> %a97}98 99define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {100; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv4f16_nxv4f16:101; CHECK: # %bb.0: # %entry102; CHECK-NEXT: fsrmi a1, 0103; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma104; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t105; CHECK-NEXT: fsrm a1106; CHECK-NEXT: ret107entry:108 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.nxv4i1(109 <vscale x 4 x half> %0,110 <vscale x 4 x half> %1,111 <vscale x 4 x half> %2,112 <vscale x 4 x i1> %3,113 iXLen 0, iXLen %4)114 115 ret <vscale x 4 x half> %a116}117 118define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {119; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv8f16_nxv4f16:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: fsrmi a1, 0122; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma123; CHECK-NEXT: vfredusum.vs v8, v10, v9124; CHECK-NEXT: fsrm a1125; CHECK-NEXT: ret126entry:127 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16(128 <vscale x 4 x half> %0,129 <vscale x 8 x half> %1,130 <vscale x 4 x half> %2,131 iXLen 0, iXLen %3)132 133 ret <vscale x 4 x half> %a134}135 136define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {137; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv8f16_nxv4f16:138; CHECK: # %bb.0: # %entry139; CHECK-NEXT: fsrmi a1, 0140; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma141; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t142; CHECK-NEXT: fsrm a1143; CHECK-NEXT: ret144entry:145 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.nxv8i1(146 <vscale x 4 x half> %0,147 <vscale x 8 x half> %1,148 <vscale x 4 x half> %2,149 <vscale x 8 x i1> %3,150 iXLen 0, iXLen %4)151 152 ret <vscale x 4 x half> %a153}154 155define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {156; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv16f16_nxv4f16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: fsrmi a1, 0159; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma160; CHECK-NEXT: vfredusum.vs v8, v12, v9161; CHECK-NEXT: fsrm a1162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16(165 <vscale x 4 x half> %0,166 <vscale x 16 x half> %1,167 <vscale x 4 x half> %2,168 iXLen 0, iXLen %3)169 170 ret <vscale x 4 x half> %a171}172 173define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {174; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv16f16_nxv4f16:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: fsrmi a1, 0177; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma178; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t179; CHECK-NEXT: fsrm a1180; CHECK-NEXT: ret181entry:182 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.nxv16i1(183 <vscale x 4 x half> %0,184 <vscale x 16 x half> %1,185 <vscale x 4 x half> %2,186 <vscale x 16 x i1> %3,187 iXLen 0, iXLen %4)188 189 ret <vscale x 4 x half> %a190}191 192define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {193; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv32f16_nxv4f16:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: fsrmi a1, 0196; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma197; CHECK-NEXT: vfredusum.vs v8, v16, v9198; CHECK-NEXT: fsrm a1199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16(202 <vscale x 4 x half> %0,203 <vscale x 32 x half> %1,204 <vscale x 4 x half> %2,205 iXLen 0, iXLen %3)206 207 ret <vscale x 4 x half> %a208}209 210define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {211; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv32f16_nxv4f16:212; CHECK: # %bb.0: # %entry213; CHECK-NEXT: fsrmi a1, 0214; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma215; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t216; CHECK-NEXT: fsrm a1217; CHECK-NEXT: ret218entry:219 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.nxv32i1(220 <vscale x 4 x half> %0,221 <vscale x 32 x half> %1,222 <vscale x 4 x half> %2,223 <vscale x 32 x i1> %3,224 iXLen 0, iXLen %4)225 226 ret <vscale x 4 x half> %a227}228 229define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {230; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv1f32_nxv2f32:231; CHECK: # %bb.0: # %entry232; CHECK-NEXT: fsrmi a1, 0233; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma234; CHECK-NEXT: vfredusum.vs v8, v9, v10235; CHECK-NEXT: fsrm a1236; CHECK-NEXT: ret237entry:238 %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32(239 <vscale x 2 x float> %0,240 <vscale x 1 x float> %1,241 <vscale x 2 x float> %2,242 iXLen 0, iXLen %3)243 244 ret <vscale x 2 x float> %a245}246 247define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {248; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv1f32_nxv2f32:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: fsrmi a1, 0251; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma252; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t253; CHECK-NEXT: fsrm a1254; CHECK-NEXT: ret255entry:256 %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.nxv1i1(257 <vscale x 2 x float> %0,258 <vscale x 1 x float> %1,259 <vscale x 2 x float> %2,260 <vscale x 1 x i1> %3,261 iXLen 0, iXLen %4)262 263 ret <vscale x 2 x float> %a264}265 266define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {267; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv2f32_nxv2f32:268; CHECK: # %bb.0: # %entry269; CHECK-NEXT: fsrmi a1, 0270; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma271; CHECK-NEXT: vfredusum.vs v8, v9, v10272; CHECK-NEXT: fsrm a1273; CHECK-NEXT: ret274entry:275 %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32(276 <vscale x 2 x float> %0,277 <vscale x 2 x float> %1,278 <vscale x 2 x float> %2,279 iXLen 0, iXLen %3)280 281 ret <vscale x 2 x float> %a282}283 284define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {285; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv2f32_nxv2f32:286; CHECK: # %bb.0: # %entry287; CHECK-NEXT: fsrmi a1, 0288; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma289; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t290; CHECK-NEXT: fsrm a1291; CHECK-NEXT: ret292entry:293 %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.nxv2i1(294 <vscale x 2 x float> %0,295 <vscale x 2 x float> %1,296 <vscale x 2 x float> %2,297 <vscale x 2 x i1> %3,298 iXLen 0, iXLen %4)299 300 ret <vscale x 2 x float> %a301}302 303define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {304; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv4f32_nxv2f32:305; CHECK: # %bb.0: # %entry306; CHECK-NEXT: fsrmi a1, 0307; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma308; CHECK-NEXT: vfredusum.vs v8, v10, v9309; CHECK-NEXT: fsrm a1310; CHECK-NEXT: ret311entry:312 %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32(313 <vscale x 2 x float> %0,314 <vscale x 4 x float> %1,315 <vscale x 2 x float> %2,316 iXLen 0, iXLen %3)317 318 ret <vscale x 2 x float> %a319}320 321define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {322; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv4f32_nxv2f32:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: fsrmi a1, 0325; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma326; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t327; CHECK-NEXT: fsrm a1328; CHECK-NEXT: ret329entry:330 %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.nxv4i1(331 <vscale x 2 x float> %0,332 <vscale x 4 x float> %1,333 <vscale x 2 x float> %2,334 <vscale x 4 x i1> %3,335 iXLen 0, iXLen %4)336 337 ret <vscale x 2 x float> %a338}339 340define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {341; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv8f32_nxv2f32:342; CHECK: # %bb.0: # %entry343; CHECK-NEXT: fsrmi a1, 0344; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma345; CHECK-NEXT: vfredusum.vs v8, v12, v9346; CHECK-NEXT: fsrm a1347; CHECK-NEXT: ret348entry:349 %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32(350 <vscale x 2 x float> %0,351 <vscale x 8 x float> %1,352 <vscale x 2 x float> %2,353 iXLen 0, iXLen %3)354 355 ret <vscale x 2 x float> %a356}357 358define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {359; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv8f32_nxv2f32:360; CHECK: # %bb.0: # %entry361; CHECK-NEXT: fsrmi a1, 0362; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma363; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t364; CHECK-NEXT: fsrm a1365; CHECK-NEXT: ret366entry:367 %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.nxv8i1(368 <vscale x 2 x float> %0,369 <vscale x 8 x float> %1,370 <vscale x 2 x float> %2,371 <vscale x 8 x i1> %3,372 iXLen 0, iXLen %4)373 374 ret <vscale x 2 x float> %a375}376 377define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {378; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv16f32_nxv2f32:379; CHECK: # %bb.0: # %entry380; CHECK-NEXT: fsrmi a1, 0381; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma382; CHECK-NEXT: vfredusum.vs v8, v16, v9383; CHECK-NEXT: fsrm a1384; CHECK-NEXT: ret385entry:386 %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32(387 <vscale x 2 x float> %0,388 <vscale x 16 x float> %1,389 <vscale x 2 x float> %2,390 iXLen 0, iXLen %3)391 392 ret <vscale x 2 x float> %a393}394 395define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {396; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv16f32_nxv2f32:397; CHECK: # %bb.0: # %entry398; CHECK-NEXT: fsrmi a1, 0399; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma400; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t401; CHECK-NEXT: fsrm a1402; CHECK-NEXT: ret403entry:404 %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.nxv16i1(405 <vscale x 2 x float> %0,406 <vscale x 16 x float> %1,407 <vscale x 2 x float> %2,408 <vscale x 16 x i1> %3,409 iXLen 0, iXLen %4)410 411 ret <vscale x 2 x float> %a412}413 414define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {415; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv1f64_nxv1f64:416; CHECK: # %bb.0: # %entry417; CHECK-NEXT: fsrmi a1, 0418; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma419; CHECK-NEXT: vfredusum.vs v8, v9, v10420; CHECK-NEXT: fsrm a1421; CHECK-NEXT: ret422entry:423 %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64(424 <vscale x 1 x double> %0,425 <vscale x 1 x double> %1,426 <vscale x 1 x double> %2,427 iXLen 0, iXLen %3)428 429 ret <vscale x 1 x double> %a430}431 432define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {433; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv1f64_nxv1f64:434; CHECK: # %bb.0: # %entry435; CHECK-NEXT: fsrmi a1, 0436; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma437; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t438; CHECK-NEXT: fsrm a1439; CHECK-NEXT: ret440entry:441 %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.nxv1i1(442 <vscale x 1 x double> %0,443 <vscale x 1 x double> %1,444 <vscale x 1 x double> %2,445 <vscale x 1 x i1> %3,446 iXLen 0, iXLen %4)447 448 ret <vscale x 1 x double> %a449}450 451define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {452; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv2f64_nxv1f64:453; CHECK: # %bb.0: # %entry454; CHECK-NEXT: fsrmi a1, 0455; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma456; CHECK-NEXT: vfredusum.vs v8, v10, v9457; CHECK-NEXT: fsrm a1458; CHECK-NEXT: ret459entry:460 %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64(461 <vscale x 1 x double> %0,462 <vscale x 2 x double> %1,463 <vscale x 1 x double> %2,464 iXLen 0, iXLen %3)465 466 ret <vscale x 1 x double> %a467}468 469define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {470; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv2f64_nxv1f64:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: fsrmi a1, 0473; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma474; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t475; CHECK-NEXT: fsrm a1476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.nxv2i1(479 <vscale x 1 x double> %0,480 <vscale x 2 x double> %1,481 <vscale x 1 x double> %2,482 <vscale x 2 x i1> %3,483 iXLen 0, iXLen %4)484 485 ret <vscale x 1 x double> %a486}487 488define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {489; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv4f64_nxv1f64:490; CHECK: # %bb.0: # %entry491; CHECK-NEXT: fsrmi a1, 0492; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma493; CHECK-NEXT: vfredusum.vs v8, v12, v9494; CHECK-NEXT: fsrm a1495; CHECK-NEXT: ret496entry:497 %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64(498 <vscale x 1 x double> %0,499 <vscale x 4 x double> %1,500 <vscale x 1 x double> %2,501 iXLen 0, iXLen %3)502 503 ret <vscale x 1 x double> %a504}505 506define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {507; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv4f64_nxv1f64:508; CHECK: # %bb.0: # %entry509; CHECK-NEXT: fsrmi a1, 0510; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma511; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t512; CHECK-NEXT: fsrm a1513; CHECK-NEXT: ret514entry:515 %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.nxv4i1(516 <vscale x 1 x double> %0,517 <vscale x 4 x double> %1,518 <vscale x 1 x double> %2,519 <vscale x 4 x i1> %3,520 iXLen 0, iXLen %4)521 522 ret <vscale x 1 x double> %a523}524 525define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {526; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv8f64_nxv1f64:527; CHECK: # %bb.0: # %entry528; CHECK-NEXT: fsrmi a1, 0529; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma530; CHECK-NEXT: vfredusum.vs v8, v16, v9531; CHECK-NEXT: fsrm a1532; CHECK-NEXT: ret533entry:534 %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64(535 <vscale x 1 x double> %0,536 <vscale x 8 x double> %1,537 <vscale x 1 x double> %2,538 iXLen 0, iXLen %3)539 540 ret <vscale x 1 x double> %a541}542 543define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {544; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv8f64_nxv1f64:545; CHECK: # %bb.0: # %entry546; CHECK-NEXT: fsrmi a1, 0547; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma548; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t549; CHECK-NEXT: fsrm a1550; CHECK-NEXT: ret551entry:552 %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.nxv8i1(553 <vscale x 1 x double> %0,554 <vscale x 8 x double> %1,555 <vscale x 1 x double> %2,556 <vscale x 8 x i1> %3,557 iXLen 0, iXLen %4)558 559 ret <vscale x 1 x double> %a560}561