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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x bfloat> @intrinsic_vfrsqrt7_v_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv1bf16_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma11; CHECK-NEXT: vfrsqrt7.v v8, v812; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.nxv1bf16(15 <vscale x 1 x bfloat> poison,16 <vscale x 1 x bfloat> %0,17 iXLen %1)18 19 ret <vscale x 1 x bfloat> %a20}21 22define <vscale x 1 x bfloat> @intrinsic_vfrsqrt7_mask_v_nxv1bf16_nxv1bf16(<vscale x 1 x i1> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {23; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv1bf16_nxv1bf16:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu26; CHECK-NEXT: vfrsqrt7.v v8, v9, v0.t27; CHECK-NEXT: ret28entry:29 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv1bf16(30 <vscale x 1 x bfloat> %1,31 <vscale x 1 x bfloat> %2,32 <vscale x 1 x i1> %0,33 iXLen %3, iXLen 1)34 35 ret <vscale x 1 x bfloat> %a36}37 38define <vscale x 2 x bfloat> @intrinsic_vfrsqrt7_v_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1) nounwind {39; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv2bf16_nxv2bf16:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma42; CHECK-NEXT: vfrsqrt7.v v8, v843; CHECK-NEXT: ret44entry:45 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.nxv2bf16(46 <vscale x 2 x bfloat> poison,47 <vscale x 2 x bfloat> %0,48 iXLen %1)49 50 ret <vscale x 2 x bfloat> %a51}52 53define <vscale x 2 x bfloat> @intrinsic_vfrsqrt7_mask_v_nxv2bf16_nxv2bf16(<vscale x 2 x i1> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {54; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv2bf16_nxv2bf16:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu57; CHECK-NEXT: vfrsqrt7.v v8, v9, v0.t58; CHECK-NEXT: ret59entry:60 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv2bf16(61 <vscale x 2 x bfloat> %1,62 <vscale x 2 x bfloat> %2,63 <vscale x 2 x i1> %0,64 iXLen %3, iXLen 1)65 66 ret <vscale x 2 x bfloat> %a67}68 69define <vscale x 4 x bfloat> @intrinsic_vfrsqrt7_v_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1) nounwind {70; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv4bf16_nxv4bf16:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma73; CHECK-NEXT: vfrsqrt7.v v8, v874; CHECK-NEXT: ret75entry:76 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.nxv4bf16(77 <vscale x 4 x bfloat> poison,78 <vscale x 4 x bfloat> %0,79 iXLen %1)80 81 ret <vscale x 4 x bfloat> %a82}83 84define <vscale x 4 x bfloat> @intrinsic_vfrsqrt7_mask_v_nxv4bf16_nxv4bf16(<vscale x 4 x i1> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, iXLen %3) nounwind {85; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv4bf16_nxv4bf16:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu88; CHECK-NEXT: vfrsqrt7.v v8, v9, v0.t89; CHECK-NEXT: ret90entry:91 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv4bf16(92 <vscale x 4 x bfloat> %1,93 <vscale x 4 x bfloat> %2,94 <vscale x 4 x i1> %0,95 iXLen %3, iXLen 1)96 97 ret <vscale x 4 x bfloat> %a98}99 100define <vscale x 8 x bfloat> @intrinsic_vfrsqrt7_v_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1) nounwind {101; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv8bf16_nxv8bf16:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma104; CHECK-NEXT: vfrsqrt7.v v8, v8105; CHECK-NEXT: ret106entry:107 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.nxv8bf16(108 <vscale x 8 x bfloat> poison,109 <vscale x 8 x bfloat> %0,110 iXLen %1)111 112 ret <vscale x 8 x bfloat> %a113}114 115define <vscale x 8 x bfloat> @intrinsic_vfrsqrt7_mask_v_nxv8bf16_nxv8bf16(<vscale x 8 x i1> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {116; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv8bf16_nxv8bf16:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu119; CHECK-NEXT: vfrsqrt7.v v8, v10, v0.t120; CHECK-NEXT: ret121entry:122 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv8bf16(123 <vscale x 8 x bfloat> %1,124 <vscale x 8 x bfloat> %2,125 <vscale x 8 x i1> %0,126 iXLen %3, iXLen 1)127 128 ret <vscale x 8 x bfloat> %a129}130 131define <vscale x 16 x bfloat> @intrinsic_vfrsqrt7_v_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1) nounwind {132; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv16bf16_nxv16bf16:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma135; CHECK-NEXT: vfrsqrt7.v v8, v8136; CHECK-NEXT: ret137entry:138 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.nxv16bf16(139 <vscale x 16 x bfloat> poison,140 <vscale x 16 x bfloat> %0,141 iXLen %1)142 143 ret <vscale x 16 x bfloat> %a144}145 146define <vscale x 16 x bfloat> @intrinsic_vfrsqrt7_mask_v_nxv16bf16_nxv16bf16(<vscale x 16 x i1> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {147; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv16bf16_nxv16bf16:148; CHECK: # %bb.0: # %entry149; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu150; CHECK-NEXT: vfrsqrt7.v v8, v12, v0.t151; CHECK-NEXT: ret152entry:153 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv16bf16(154 <vscale x 16 x bfloat> %1,155 <vscale x 16 x bfloat> %2,156 <vscale x 16 x i1> %0,157 iXLen %3, iXLen 1)158 159 ret <vscale x 16 x bfloat> %a160}161 162define <vscale x 32 x bfloat> @intrinsic_vfrsqrt7_v_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, iXLen %1) nounwind {163; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv32bf16_nxv32bf16:164; CHECK: # %bb.0: # %entry165; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma166; CHECK-NEXT: vfrsqrt7.v v8, v8167; CHECK-NEXT: ret168entry:169 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.nxv32bf16(170 <vscale x 32 x bfloat> poison,171 <vscale x 32 x bfloat> %0,172 iXLen %1)173 174 ret <vscale x 32 x bfloat> %a175}176 177define <vscale x 32 x bfloat> @intrinsic_vfrsqrt7_mask_v_nxv32bf16_nxv32bf16(<vscale x 32 x i1> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, iXLen %3) nounwind {178; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv32bf16_nxv32bf16:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, mu181; CHECK-NEXT: vfrsqrt7.v v8, v16, v0.t182; CHECK-NEXT: ret183entry:184 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfrsqrt7.mask.nxv32bf16(185 <vscale x 32 x bfloat> %1,186 <vscale x 32 x bfloat> %2,187 <vscale x 32 x i1> %0,188 iXLen %3, iXLen 1)189 190 ret <vscale x 32 x bfloat> %a191}192 193