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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x half> @intrinsic_vfrsqrt7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv1f16_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vfrsqrt7.v v8, v812; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16(15 <vscale x 1 x half> poison,16 <vscale x 1 x half> %0,17 iXLen %1)18 19 ret <vscale x 1 x half> %a20}21 22define <vscale x 1 x half> @intrinsic_vfrsqrt7_mask_v_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {23; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv1f16_nxv1f16:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu26; CHECK-NEXT: vfrsqrt7.v v8, v9, v0.t27; CHECK-NEXT: ret28entry:29 %a = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.mask.nxv1f16(30 <vscale x 1 x half> %1,31 <vscale x 1 x half> %2,32 <vscale x 1 x i1> %0,33 iXLen %3, iXLen 1)34 35 ret <vscale x 1 x half> %a36}37 38define <vscale x 2 x half> @intrinsic_vfrsqrt7_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {39; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv2f16_nxv2f16:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma42; CHECK-NEXT: vfrsqrt7.v v8, v843; CHECK-NEXT: ret44entry:45 %a = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16(46 <vscale x 2 x half> poison,47 <vscale x 2 x half> %0,48 iXLen %1)49 50 ret <vscale x 2 x half> %a51}52 53define <vscale x 2 x half> @intrinsic_vfrsqrt7_mask_v_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind {54; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv2f16_nxv2f16:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu57; CHECK-NEXT: vfrsqrt7.v v8, v9, v0.t58; CHECK-NEXT: ret59entry:60 %a = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.mask.nxv2f16(61 <vscale x 2 x half> %1,62 <vscale x 2 x half> %2,63 <vscale x 2 x i1> %0,64 iXLen %3, iXLen 1)65 66 ret <vscale x 2 x half> %a67}68 69define <vscale x 4 x half> @intrinsic_vfrsqrt7_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {70; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv4f16_nxv4f16:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma73; CHECK-NEXT: vfrsqrt7.v v8, v874; CHECK-NEXT: ret75entry:76 %a = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16(77 <vscale x 4 x half> poison,78 <vscale x 4 x half> %0,79 iXLen %1)80 81 ret <vscale x 4 x half> %a82}83 84define <vscale x 4 x half> @intrinsic_vfrsqrt7_mask_v_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {85; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv4f16_nxv4f16:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu88; CHECK-NEXT: vfrsqrt7.v v8, v9, v0.t89; CHECK-NEXT: ret90entry:91 %a = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.mask.nxv4f16(92 <vscale x 4 x half> %1,93 <vscale x 4 x half> %2,94 <vscale x 4 x i1> %0,95 iXLen %3, iXLen 1)96 97 ret <vscale x 4 x half> %a98}99 100define <vscale x 8 x half> @intrinsic_vfrsqrt7_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {101; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv8f16_nxv8f16:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma104; CHECK-NEXT: vfrsqrt7.v v8, v8105; CHECK-NEXT: ret106entry:107 %a = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16(108 <vscale x 8 x half> poison,109 <vscale x 8 x half> %0,110 iXLen %1)111 112 ret <vscale x 8 x half> %a113}114 115define <vscale x 8 x half> @intrinsic_vfrsqrt7_mask_v_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind {116; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv8f16_nxv8f16:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu119; CHECK-NEXT: vfrsqrt7.v v8, v10, v0.t120; CHECK-NEXT: ret121entry:122 %a = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.mask.nxv8f16(123 <vscale x 8 x half> %1,124 <vscale x 8 x half> %2,125 <vscale x 8 x i1> %0,126 iXLen %3, iXLen 1)127 128 ret <vscale x 8 x half> %a129}130 131define <vscale x 16 x half> @intrinsic_vfrsqrt7_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {132; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv16f16_nxv16f16:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma135; CHECK-NEXT: vfrsqrt7.v v8, v8136; CHECK-NEXT: ret137entry:138 %a = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16(139 <vscale x 16 x half> poison,140 <vscale x 16 x half> %0,141 iXLen %1)142 143 ret <vscale x 16 x half> %a144}145 146define <vscale x 16 x half> @intrinsic_vfrsqrt7_mask_v_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {147; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv16f16_nxv16f16:148; CHECK: # %bb.0: # %entry149; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu150; CHECK-NEXT: vfrsqrt7.v v8, v12, v0.t151; CHECK-NEXT: ret152entry:153 %a = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.mask.nxv16f16(154 <vscale x 16 x half> %1,155 <vscale x 16 x half> %2,156 <vscale x 16 x i1> %0,157 iXLen %3, iXLen 1)158 159 ret <vscale x 16 x half> %a160}161 162define <vscale x 32 x half> @intrinsic_vfrsqrt7_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {163; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv32f16_nxv32f16:164; CHECK: # %bb.0: # %entry165; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma166; CHECK-NEXT: vfrsqrt7.v v8, v8167; CHECK-NEXT: ret168entry:169 %a = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16(170 <vscale x 32 x half> poison,171 <vscale x 32 x half> %0,172 iXLen %1)173 174 ret <vscale x 32 x half> %a175}176 177define <vscale x 32 x half> @intrinsic_vfrsqrt7_mask_v_nxv32f16_nxv32f16(<vscale x 32 x i1> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, iXLen %3) nounwind {178; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv32f16_nxv32f16:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu181; CHECK-NEXT: vfrsqrt7.v v8, v16, v0.t182; CHECK-NEXT: ret183entry:184 %a = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.mask.nxv32f16(185 <vscale x 32 x half> %1,186 <vscale x 32 x half> %2,187 <vscale x 32 x i1> %0,188 iXLen %3, iXLen 1)189 190 ret <vscale x 32 x half> %a191}192 193define <vscale x 1 x float> @intrinsic_vfrsqrt7_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {194; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv1f32_nxv1f32:195; CHECK: # %bb.0: # %entry196; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma197; CHECK-NEXT: vfrsqrt7.v v8, v8198; CHECK-NEXT: ret199entry:200 %a = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32(201 <vscale x 1 x float> poison,202 <vscale x 1 x float> %0,203 iXLen %1)204 205 ret <vscale x 1 x float> %a206}207 208define <vscale x 1 x float> @intrinsic_vfrsqrt7_mask_v_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {209; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv1f32_nxv1f32:210; CHECK: # %bb.0: # %entry211; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu212; CHECK-NEXT: vfrsqrt7.v v8, v9, v0.t213; CHECK-NEXT: ret214entry:215 %a = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.mask.nxv1f32(216 <vscale x 1 x float> %1,217 <vscale x 1 x float> %2,218 <vscale x 1 x i1> %0,219 iXLen %3, iXLen 1)220 221 ret <vscale x 1 x float> %a222}223 224define <vscale x 2 x float> @intrinsic_vfrsqrt7_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {225; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv2f32_nxv2f32:226; CHECK: # %bb.0: # %entry227; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma228; CHECK-NEXT: vfrsqrt7.v v8, v8229; CHECK-NEXT: ret230entry:231 %a = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32(232 <vscale x 2 x float> poison,233 <vscale x 2 x float> %0,234 iXLen %1)235 236 ret <vscale x 2 x float> %a237}238 239define <vscale x 2 x float> @intrinsic_vfrsqrt7_mask_v_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {240; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv2f32_nxv2f32:241; CHECK: # %bb.0: # %entry242; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu243; CHECK-NEXT: vfrsqrt7.v v8, v9, v0.t244; CHECK-NEXT: ret245entry:246 %a = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.mask.nxv2f32(247 <vscale x 2 x float> %1,248 <vscale x 2 x float> %2,249 <vscale x 2 x i1> %0,250 iXLen %3, iXLen 1)251 252 ret <vscale x 2 x float> %a253}254 255define <vscale x 4 x float> @intrinsic_vfrsqrt7_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {256; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv4f32_nxv4f32:257; CHECK: # %bb.0: # %entry258; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma259; CHECK-NEXT: vfrsqrt7.v v8, v8260; CHECK-NEXT: ret261entry:262 %a = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32(263 <vscale x 4 x float> poison,264 <vscale x 4 x float> %0,265 iXLen %1)266 267 ret <vscale x 4 x float> %a268}269 270define <vscale x 4 x float> @intrinsic_vfrsqrt7_mask_v_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind {271; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv4f32_nxv4f32:272; CHECK: # %bb.0: # %entry273; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu274; CHECK-NEXT: vfrsqrt7.v v8, v10, v0.t275; CHECK-NEXT: ret276entry:277 %a = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.mask.nxv4f32(278 <vscale x 4 x float> %1,279 <vscale x 4 x float> %2,280 <vscale x 4 x i1> %0,281 iXLen %3, iXLen 1)282 283 ret <vscale x 4 x float> %a284}285 286define <vscale x 8 x float> @intrinsic_vfrsqrt7_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {287; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv8f32_nxv8f32:288; CHECK: # %bb.0: # %entry289; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma290; CHECK-NEXT: vfrsqrt7.v v8, v8291; CHECK-NEXT: ret292entry:293 %a = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32(294 <vscale x 8 x float> poison,295 <vscale x 8 x float> %0,296 iXLen %1)297 298 ret <vscale x 8 x float> %a299}300 301define <vscale x 8 x float> @intrinsic_vfrsqrt7_mask_v_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind {302; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv8f32_nxv8f32:303; CHECK: # %bb.0: # %entry304; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu305; CHECK-NEXT: vfrsqrt7.v v8, v12, v0.t306; CHECK-NEXT: ret307entry:308 %a = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.mask.nxv8f32(309 <vscale x 8 x float> %1,310 <vscale x 8 x float> %2,311 <vscale x 8 x i1> %0,312 iXLen %3, iXLen 1)313 314 ret <vscale x 8 x float> %a315}316 317define <vscale x 16 x float> @intrinsic_vfrsqrt7_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {318; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv16f32_nxv16f32:319; CHECK: # %bb.0: # %entry320; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma321; CHECK-NEXT: vfrsqrt7.v v8, v8322; CHECK-NEXT: ret323entry:324 %a = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32(325 <vscale x 16 x float> poison,326 <vscale x 16 x float> %0,327 iXLen %1)328 329 ret <vscale x 16 x float> %a330}331 332define <vscale x 16 x float> @intrinsic_vfrsqrt7_mask_v_nxv16f32_nxv16f32(<vscale x 16 x i1> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, iXLen %3) nounwind {333; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv16f32_nxv16f32:334; CHECK: # %bb.0: # %entry335; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu336; CHECK-NEXT: vfrsqrt7.v v8, v16, v0.t337; CHECK-NEXT: ret338entry:339 %a = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.mask.nxv16f32(340 <vscale x 16 x float> %1,341 <vscale x 16 x float> %2,342 <vscale x 16 x i1> %0,343 iXLen %3, iXLen 1)344 345 ret <vscale x 16 x float> %a346}347 348define <vscale x 1 x double> @intrinsic_vfrsqrt7_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {349; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv1f64_nxv1f64:350; CHECK: # %bb.0: # %entry351; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma352; CHECK-NEXT: vfrsqrt7.v v8, v8353; CHECK-NEXT: ret354entry:355 %a = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64(356 <vscale x 1 x double> poison,357 <vscale x 1 x double> %0,358 iXLen %1)359 360 ret <vscale x 1 x double> %a361}362 363define <vscale x 1 x double> @intrinsic_vfrsqrt7_mask_v_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {364; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv1f64_nxv1f64:365; CHECK: # %bb.0: # %entry366; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu367; CHECK-NEXT: vfrsqrt7.v v8, v9, v0.t368; CHECK-NEXT: ret369entry:370 %a = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.mask.nxv1f64(371 <vscale x 1 x double> %1,372 <vscale x 1 x double> %2,373 <vscale x 1 x i1> %0,374 iXLen %3, iXLen 1)375 376 ret <vscale x 1 x double> %a377}378 379define <vscale x 2 x double> @intrinsic_vfrsqrt7_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {380; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv2f64_nxv2f64:381; CHECK: # %bb.0: # %entry382; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma383; CHECK-NEXT: vfrsqrt7.v v8, v8384; CHECK-NEXT: ret385entry:386 %a = call <vscale x 2 x double> @llvm.riscv.vfrsqrt7.nxv2f64(387 <vscale x 2 x double> poison,388 <vscale x 2 x double> %0,389 iXLen %1)390 391 ret <vscale x 2 x double> %a392}393 394define <vscale x 2 x double> @intrinsic_vfrsqrt7_mask_v_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind {395; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv2f64_nxv2f64:396; CHECK: # %bb.0: # %entry397; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu398; CHECK-NEXT: vfrsqrt7.v v8, v10, v0.t399; CHECK-NEXT: ret400entry:401 %a = call <vscale x 2 x double> @llvm.riscv.vfrsqrt7.mask.nxv2f64(402 <vscale x 2 x double> %1,403 <vscale x 2 x double> %2,404 <vscale x 2 x i1> %0,405 iXLen %3, iXLen 1)406 407 ret <vscale x 2 x double> %a408}409 410define <vscale x 4 x double> @intrinsic_vfrsqrt7_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {411; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv4f64_nxv4f64:412; CHECK: # %bb.0: # %entry413; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma414; CHECK-NEXT: vfrsqrt7.v v8, v8415; CHECK-NEXT: ret416entry:417 %a = call <vscale x 4 x double> @llvm.riscv.vfrsqrt7.nxv4f64(418 <vscale x 4 x double> poison,419 <vscale x 4 x double> %0,420 iXLen %1)421 422 ret <vscale x 4 x double> %a423}424 425define <vscale x 4 x double> @intrinsic_vfrsqrt7_mask_v_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind {426; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv4f64_nxv4f64:427; CHECK: # %bb.0: # %entry428; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu429; CHECK-NEXT: vfrsqrt7.v v8, v12, v0.t430; CHECK-NEXT: ret431entry:432 %a = call <vscale x 4 x double> @llvm.riscv.vfrsqrt7.mask.nxv4f64(433 <vscale x 4 x double> %1,434 <vscale x 4 x double> %2,435 <vscale x 4 x i1> %0,436 iXLen %3, iXLen 1)437 438 ret <vscale x 4 x double> %a439}440 441define <vscale x 8 x double> @intrinsic_vfrsqrt7_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {442; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv8f64_nxv8f64:443; CHECK: # %bb.0: # %entry444; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma445; CHECK-NEXT: vfrsqrt7.v v8, v8446; CHECK-NEXT: ret447entry:448 %a = call <vscale x 8 x double> @llvm.riscv.vfrsqrt7.nxv8f64(449 <vscale x 8 x double> poison,450 <vscale x 8 x double> %0,451 iXLen %1)452 453 ret <vscale x 8 x double> %a454}455 456define <vscale x 8 x double> @intrinsic_vfrsqrt7_mask_v_nxv8f64_nxv8f64(<vscale x 8 x i1> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, iXLen %3) nounwind {457; CHECK-LABEL: intrinsic_vfrsqrt7_mask_v_nxv8f64_nxv8f64:458; CHECK: # %bb.0: # %entry459; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu460; CHECK-NEXT: vfrsqrt7.v v8, v16, v0.t461; CHECK-NEXT: ret462entry:463 %a = call <vscale x 8 x double> @llvm.riscv.vfrsqrt7.mask.nxv8f64(464 <vscale x 8 x double> %1,465 <vscale x 8 x double> %2,466 <vscale x 8 x i1> %0,467 iXLen %3, iXLen 1)468 469 ret <vscale x 8 x double> %a470}471