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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x half> @intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vfrsub.vf v8, v8, fa012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16(15 <vscale x 1 x half> poison,16 <vscale x 1 x half> %0,17 half %1,18 iXLen 7, iXLen %2)19 20 ret <vscale x 1 x half> %a21}22 23define <vscale x 1 x half> @intrinsic_vfrsub_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv1f16_nxv1f16_f16:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu27; CHECK-NEXT: vfrsub.vf v8, v9, fa0, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x half> @llvm.riscv.vfrsub.mask.nxv1f16.f16(31 <vscale x 1 x half> %0,32 <vscale x 1 x half> %1,33 half %2,34 <vscale x 1 x i1> %3,35 iXLen 7, iXLen %4, iXLen 1)36 37 ret <vscale x 1 x half> %a38}39 40define <vscale x 2 x half> @intrinsic_vfrsub_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vfrsub_vf_nxv2f16_nxv2f16_f16:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma44; CHECK-NEXT: vfrsub.vf v8, v8, fa045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x half> @llvm.riscv.vfrsub.nxv2f16.f16(48 <vscale x 2 x half> poison,49 <vscale x 2 x half> %0,50 half %1,51 iXLen 7, iXLen %2)52 53 ret <vscale x 2 x half> %a54}55 56define <vscale x 2 x half> @intrinsic_vfrsub_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv2f16_nxv2f16_f16:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu60; CHECK-NEXT: vfrsub.vf v8, v9, fa0, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x half> @llvm.riscv.vfrsub.mask.nxv2f16.f16(64 <vscale x 2 x half> %0,65 <vscale x 2 x half> %1,66 half %2,67 <vscale x 2 x i1> %3,68 iXLen 7, iXLen %4, iXLen 1)69 70 ret <vscale x 2 x half> %a71}72 73define <vscale x 4 x half> @intrinsic_vfrsub_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vfrsub_vf_nxv4f16_nxv4f16_f16:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma77; CHECK-NEXT: vfrsub.vf v8, v8, fa078; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x half> @llvm.riscv.vfrsub.nxv4f16.f16(81 <vscale x 4 x half> poison,82 <vscale x 4 x half> %0,83 half %1,84 iXLen 7, iXLen %2)85 86 ret <vscale x 4 x half> %a87}88 89define <vscale x 4 x half> @intrinsic_vfrsub_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv4f16_nxv4f16_f16:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu93; CHECK-NEXT: vfrsub.vf v8, v9, fa0, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x half> @llvm.riscv.vfrsub.mask.nxv4f16.f16(97 <vscale x 4 x half> %0,98 <vscale x 4 x half> %1,99 half %2,100 <vscale x 4 x i1> %3,101 iXLen 7, iXLen %4, iXLen 1)102 103 ret <vscale x 4 x half> %a104}105 106define <vscale x 8 x half> @intrinsic_vfrsub_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vfrsub_vf_nxv8f16_nxv8f16_f16:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma110; CHECK-NEXT: vfrsub.vf v8, v8, fa0111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x half> @llvm.riscv.vfrsub.nxv8f16.f16(114 <vscale x 8 x half> poison,115 <vscale x 8 x half> %0,116 half %1,117 iXLen 7, iXLen %2)118 119 ret <vscale x 8 x half> %a120}121 122define <vscale x 8 x half> @intrinsic_vfrsub_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv8f16_nxv8f16_f16:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu126; CHECK-NEXT: vfrsub.vf v8, v10, fa0, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x half> @llvm.riscv.vfrsub.mask.nxv8f16.f16(130 <vscale x 8 x half> %0,131 <vscale x 8 x half> %1,132 half %2,133 <vscale x 8 x i1> %3,134 iXLen 7, iXLen %4, iXLen 1)135 136 ret <vscale x 8 x half> %a137}138 139define <vscale x 16 x half> @intrinsic_vfrsub_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vfrsub_vf_nxv16f16_nxv16f16_f16:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma143; CHECK-NEXT: vfrsub.vf v8, v8, fa0144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 16 x half> @llvm.riscv.vfrsub.nxv16f16.f16(147 <vscale x 16 x half> poison,148 <vscale x 16 x half> %0,149 half %1,150 iXLen 7, iXLen %2)151 152 ret <vscale x 16 x half> %a153}154 155define <vscale x 16 x half> @intrinsic_vfrsub_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv16f16_nxv16f16_f16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu159; CHECK-NEXT: vfrsub.vf v8, v12, fa0, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x half> @llvm.riscv.vfrsub.mask.nxv16f16.f16(163 <vscale x 16 x half> %0,164 <vscale x 16 x half> %1,165 half %2,166 <vscale x 16 x i1> %3,167 iXLen 7, iXLen %4, iXLen 1)168 169 ret <vscale x 16 x half> %a170}171 172define <vscale x 32 x half> @intrinsic_vfrsub_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vfrsub_vf_nxv32f16_nxv32f16_f16:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma176; CHECK-NEXT: vfrsub.vf v8, v8, fa0177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 32 x half> @llvm.riscv.vfrsub.nxv32f16.f16(180 <vscale x 32 x half> poison,181 <vscale x 32 x half> %0,182 half %1,183 iXLen 7, iXLen %2)184 185 ret <vscale x 32 x half> %a186}187 188define <vscale x 32 x half> @intrinsic_vfrsub_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv32f16_nxv32f16_f16:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu192; CHECK-NEXT: vfrsub.vf v8, v16, fa0, v0.t193; CHECK-NEXT: ret194entry:195 %a = call <vscale x 32 x half> @llvm.riscv.vfrsub.mask.nxv32f16.f16(196 <vscale x 32 x half> %0,197 <vscale x 32 x half> %1,198 half %2,199 <vscale x 32 x i1> %3,200 iXLen 7, iXLen %4, iXLen 1)201 202 ret <vscale x 32 x half> %a203}204 205define <vscale x 1 x float> @intrinsic_vfrsub_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {206; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f32_nxv1f32_f32:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma209; CHECK-NEXT: vfrsub.vf v8, v8, fa0210; CHECK-NEXT: ret211entry:212 %a = call <vscale x 1 x float> @llvm.riscv.vfrsub.nxv1f32.f32(213 <vscale x 1 x float> poison,214 <vscale x 1 x float> %0,215 float %1,216 iXLen 7, iXLen %2)217 218 ret <vscale x 1 x float> %a219}220 221define <vscale x 1 x float> @intrinsic_vfrsub_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv1f32_nxv1f32_f32:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu225; CHECK-NEXT: vfrsub.vf v8, v9, fa0, v0.t226; CHECK-NEXT: ret227entry:228 %a = call <vscale x 1 x float> @llvm.riscv.vfrsub.mask.nxv1f32.f32(229 <vscale x 1 x float> %0,230 <vscale x 1 x float> %1,231 float %2,232 <vscale x 1 x i1> %3,233 iXLen 7, iXLen %4, iXLen 1)234 235 ret <vscale x 1 x float> %a236}237 238define <vscale x 2 x float> @intrinsic_vfrsub_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {239; CHECK-LABEL: intrinsic_vfrsub_vf_nxv2f32_nxv2f32_f32:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma242; CHECK-NEXT: vfrsub.vf v8, v8, fa0243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 2 x float> @llvm.riscv.vfrsub.nxv2f32.f32(246 <vscale x 2 x float> poison,247 <vscale x 2 x float> %0,248 float %1,249 iXLen 7, iXLen %2)250 251 ret <vscale x 2 x float> %a252}253 254define <vscale x 2 x float> @intrinsic_vfrsub_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {255; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv2f32_nxv2f32_f32:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu258; CHECK-NEXT: vfrsub.vf v8, v9, fa0, v0.t259; CHECK-NEXT: ret260entry:261 %a = call <vscale x 2 x float> @llvm.riscv.vfrsub.mask.nxv2f32.f32(262 <vscale x 2 x float> %0,263 <vscale x 2 x float> %1,264 float %2,265 <vscale x 2 x i1> %3,266 iXLen 7, iXLen %4, iXLen 1)267 268 ret <vscale x 2 x float> %a269}270 271define <vscale x 4 x float> @intrinsic_vfrsub_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {272; CHECK-LABEL: intrinsic_vfrsub_vf_nxv4f32_nxv4f32_f32:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma275; CHECK-NEXT: vfrsub.vf v8, v8, fa0276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.f32(279 <vscale x 4 x float> poison,280 <vscale x 4 x float> %0,281 float %1,282 iXLen 7, iXLen %2)283 284 ret <vscale x 4 x float> %a285}286 287define <vscale x 4 x float> @intrinsic_vfrsub_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {288; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv4f32_nxv4f32_f32:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu291; CHECK-NEXT: vfrsub.vf v8, v10, fa0, v0.t292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 4 x float> @llvm.riscv.vfrsub.mask.nxv4f32.f32(295 <vscale x 4 x float> %0,296 <vscale x 4 x float> %1,297 float %2,298 <vscale x 4 x i1> %3,299 iXLen 7, iXLen %4, iXLen 1)300 301 ret <vscale x 4 x float> %a302}303 304define <vscale x 8 x float> @intrinsic_vfrsub_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {305; CHECK-LABEL: intrinsic_vfrsub_vf_nxv8f32_nxv8f32_f32:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma308; CHECK-NEXT: vfrsub.vf v8, v8, fa0309; CHECK-NEXT: ret310entry:311 %a = call <vscale x 8 x float> @llvm.riscv.vfrsub.nxv8f32.f32(312 <vscale x 8 x float> poison,313 <vscale x 8 x float> %0,314 float %1,315 iXLen 7, iXLen %2)316 317 ret <vscale x 8 x float> %a318}319 320define <vscale x 8 x float> @intrinsic_vfrsub_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {321; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv8f32_nxv8f32_f32:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu324; CHECK-NEXT: vfrsub.vf v8, v12, fa0, v0.t325; CHECK-NEXT: ret326entry:327 %a = call <vscale x 8 x float> @llvm.riscv.vfrsub.mask.nxv8f32.f32(328 <vscale x 8 x float> %0,329 <vscale x 8 x float> %1,330 float %2,331 <vscale x 8 x i1> %3,332 iXLen 7, iXLen %4, iXLen 1)333 334 ret <vscale x 8 x float> %a335}336 337define <vscale x 16 x float> @intrinsic_vfrsub_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, iXLen %2) nounwind {338; CHECK-LABEL: intrinsic_vfrsub_vf_nxv16f32_nxv16f32_f32:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma341; CHECK-NEXT: vfrsub.vf v8, v8, fa0342; CHECK-NEXT: ret343entry:344 %a = call <vscale x 16 x float> @llvm.riscv.vfrsub.nxv16f32.f32(345 <vscale x 16 x float> poison,346 <vscale x 16 x float> %0,347 float %1,348 iXLen 7, iXLen %2)349 350 ret <vscale x 16 x float> %a351}352 353define <vscale x 16 x float> @intrinsic_vfrsub_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {354; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv16f32_nxv16f32_f32:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu357; CHECK-NEXT: vfrsub.vf v8, v16, fa0, v0.t358; CHECK-NEXT: ret359entry:360 %a = call <vscale x 16 x float> @llvm.riscv.vfrsub.mask.nxv16f32.f32(361 <vscale x 16 x float> %0,362 <vscale x 16 x float> %1,363 float %2,364 <vscale x 16 x i1> %3,365 iXLen 7, iXLen %4, iXLen 1)366 367 ret <vscale x 16 x float> %a368}369 370define <vscale x 1 x double> @intrinsic_vfrsub_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {371; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f64_nxv1f64_f64:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma374; CHECK-NEXT: vfrsub.vf v8, v8, fa0375; CHECK-NEXT: ret376entry:377 %a = call <vscale x 1 x double> @llvm.riscv.vfrsub.nxv1f64.f64(378 <vscale x 1 x double> poison,379 <vscale x 1 x double> %0,380 double %1,381 iXLen 7, iXLen %2)382 383 ret <vscale x 1 x double> %a384}385 386define <vscale x 1 x double> @intrinsic_vfrsub_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {387; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv1f64_nxv1f64_f64:388; CHECK: # %bb.0: # %entry389; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu390; CHECK-NEXT: vfrsub.vf v8, v9, fa0, v0.t391; CHECK-NEXT: ret392entry:393 %a = call <vscale x 1 x double> @llvm.riscv.vfrsub.mask.nxv1f64.f64(394 <vscale x 1 x double> %0,395 <vscale x 1 x double> %1,396 double %2,397 <vscale x 1 x i1> %3,398 iXLen 7, iXLen %4, iXLen 1)399 400 ret <vscale x 1 x double> %a401}402 403define <vscale x 2 x double> @intrinsic_vfrsub_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {404; CHECK-LABEL: intrinsic_vfrsub_vf_nxv2f64_nxv2f64_f64:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma407; CHECK-NEXT: vfrsub.vf v8, v8, fa0408; CHECK-NEXT: ret409entry:410 %a = call <vscale x 2 x double> @llvm.riscv.vfrsub.nxv2f64.f64(411 <vscale x 2 x double> poison,412 <vscale x 2 x double> %0,413 double %1,414 iXLen 7, iXLen %2)415 416 ret <vscale x 2 x double> %a417}418 419define <vscale x 2 x double> @intrinsic_vfrsub_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {420; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv2f64_nxv2f64_f64:421; CHECK: # %bb.0: # %entry422; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu423; CHECK-NEXT: vfrsub.vf v8, v10, fa0, v0.t424; CHECK-NEXT: ret425entry:426 %a = call <vscale x 2 x double> @llvm.riscv.vfrsub.mask.nxv2f64.f64(427 <vscale x 2 x double> %0,428 <vscale x 2 x double> %1,429 double %2,430 <vscale x 2 x i1> %3,431 iXLen 7, iXLen %4, iXLen 1)432 433 ret <vscale x 2 x double> %a434}435 436define <vscale x 4 x double> @intrinsic_vfrsub_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {437; CHECK-LABEL: intrinsic_vfrsub_vf_nxv4f64_nxv4f64_f64:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma440; CHECK-NEXT: vfrsub.vf v8, v8, fa0441; CHECK-NEXT: ret442entry:443 %a = call <vscale x 4 x double> @llvm.riscv.vfrsub.nxv4f64.f64(444 <vscale x 4 x double> poison,445 <vscale x 4 x double> %0,446 double %1,447 iXLen 7, iXLen %2)448 449 ret <vscale x 4 x double> %a450}451 452define <vscale x 4 x double> @intrinsic_vfrsub_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {453; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv4f64_nxv4f64_f64:454; CHECK: # %bb.0: # %entry455; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu456; CHECK-NEXT: vfrsub.vf v8, v12, fa0, v0.t457; CHECK-NEXT: ret458entry:459 %a = call <vscale x 4 x double> @llvm.riscv.vfrsub.mask.nxv4f64.f64(460 <vscale x 4 x double> %0,461 <vscale x 4 x double> %1,462 double %2,463 <vscale x 4 x i1> %3,464 iXLen 7, iXLen %4, iXLen 1)465 466 ret <vscale x 4 x double> %a467}468 469define <vscale x 8 x double> @intrinsic_vfrsub_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, iXLen %2) nounwind {470; CHECK-LABEL: intrinsic_vfrsub_vf_nxv8f64_nxv8f64_f64:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma473; CHECK-NEXT: vfrsub.vf v8, v8, fa0474; CHECK-NEXT: ret475entry:476 %a = call <vscale x 8 x double> @llvm.riscv.vfrsub.nxv8f64.f64(477 <vscale x 8 x double> poison,478 <vscale x 8 x double> %0,479 double %1,480 iXLen 7, iXLen %2)481 482 ret <vscale x 8 x double> %a483}484 485define <vscale x 8 x double> @intrinsic_vfrsub_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {486; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv8f64_nxv8f64_f64:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu489; CHECK-NEXT: vfrsub.vf v8, v16, fa0, v0.t490; CHECK-NEXT: ret491entry:492 %a = call <vscale x 8 x double> @llvm.riscv.vfrsub.mask.nxv8f64.f64(493 <vscale x 8 x double> %0,494 <vscale x 8 x double> %1,495 double %2,496 <vscale x 8 x i1> %3,497 iXLen 7, iXLen %4, iXLen 1)498 499 ret <vscale x 8 x double> %a500}501