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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x bfloat> @intrinsic_vfslide1down_vf_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, bfloat %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1bf16_nxv1bf16_bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma11; CHECK-NEXT: vfslide1down.vf v8, v8, fa012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.nxv1bf16.bf16(15 <vscale x 1 x bfloat> poison,16 <vscale x 1 x bfloat> %0,17 bfloat %1,18 iXLen %2)19 20 ret <vscale x 1 x bfloat> %a21}22 23define <vscale x 1 x bfloat> @intrinsic_vfslide1down_mask_vf_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv1bf16_nxv1bf16_bf16:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu27; CHECK-NEXT: vfslide1down.vf v8, v9, fa0, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16(31 <vscale x 1 x bfloat> %0,32 <vscale x 1 x bfloat> %1,33 bfloat %2,34 <vscale x 1 x i1> %3,35 iXLen %4, iXLen 1)36 37 ret <vscale x 1 x bfloat> %a38}39 40define <vscale x 2 x bfloat> @intrinsic_vfslide1down_vf_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, bfloat %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv2bf16_nxv2bf16_bf16:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma44; CHECK-NEXT: vfslide1down.vf v8, v8, fa045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.nxv2bf16.bf16(48 <vscale x 2 x bfloat> poison,49 <vscale x 2 x bfloat> %0,50 bfloat %1,51 iXLen %2)52 53 ret <vscale x 2 x bfloat> %a54}55 56define <vscale x 2 x bfloat> @intrinsic_vfslide1down_mask_vf_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv2bf16_nxv2bf16_bf16:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu60; CHECK-NEXT: vfslide1down.vf v8, v9, fa0, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16(64 <vscale x 2 x bfloat> %0,65 <vscale x 2 x bfloat> %1,66 bfloat %2,67 <vscale x 2 x i1> %3,68 iXLen %4, iXLen 1)69 70 ret <vscale x 2 x bfloat> %a71}72 73define <vscale x 4 x bfloat> @intrinsic_vfslide1down_vf_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, bfloat %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4bf16_nxv4bf16_bf16:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma77; CHECK-NEXT: vfslide1down.vf v8, v8, fa078; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.nxv4bf16.bf16(81 <vscale x 4 x bfloat> poison,82 <vscale x 4 x bfloat> %0,83 bfloat %1,84 iXLen %2)85 86 ret <vscale x 4 x bfloat> %a87}88 89define <vscale x 4 x bfloat> @intrinsic_vfslide1down_mask_vf_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv4bf16_nxv4bf16_bf16:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu93; CHECK-NEXT: vfslide1down.vf v8, v9, fa0, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16(97 <vscale x 4 x bfloat> %0,98 <vscale x 4 x bfloat> %1,99 bfloat %2,100 <vscale x 4 x i1> %3,101 iXLen %4, iXLen 1)102 103 ret <vscale x 4 x bfloat> %a104}105 106define <vscale x 8 x bfloat> @intrinsic_vfslide1down_vf_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, bfloat %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv8bf16_nxv8bf16_bf16:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma110; CHECK-NEXT: vfslide1down.vf v8, v8, fa0111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.nxv8bf16.bf16(114 <vscale x 8 x bfloat> poison,115 <vscale x 8 x bfloat> %0,116 bfloat %1,117 iXLen %2)118 119 ret <vscale x 8 x bfloat> %a120}121 122define <vscale x 8 x bfloat> @intrinsic_vfslide1down_mask_vf_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8bf16_nxv8bf16_bf16:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu126; CHECK-NEXT: vfslide1down.vf v8, v10, fa0, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1down.mask.nxv8bf16.bf16(130 <vscale x 8 x bfloat> %0,131 <vscale x 8 x bfloat> %1,132 bfloat %2,133 <vscale x 8 x i1> %3,134 iXLen %4, iXLen 1)135 136 ret <vscale x 8 x bfloat> %a137}138 139define <vscale x 16 x bfloat> @intrinsic_vfslide1down_vf_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, bfloat %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv16bf16_nxv16bf16_bf16:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma143; CHECK-NEXT: vfslide1down.vf v8, v8, fa0144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.nxv16bf16.bf16(147 <vscale x 16 x bfloat> poison,148 <vscale x 16 x bfloat> %0,149 bfloat %1,150 iXLen %2)151 152 ret <vscale x 16 x bfloat> %a153}154 155define <vscale x 16 x bfloat> @intrinsic_vfslide1down_mask_vf_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv16bf16_nxv16bf16_bf16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu159; CHECK-NEXT: vfslide1down.vf v8, v12, fa0, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1down.mask.nxv16bf16.bf16(163 <vscale x 16 x bfloat> %0,164 <vscale x 16 x bfloat> %1,165 bfloat %2,166 <vscale x 16 x i1> %3,167 iXLen %4, iXLen 1)168 169 ret <vscale x 16 x bfloat> %a170}171 172define <vscale x 32 x bfloat> @intrinsic_vfslide1down_vf_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, bfloat %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv32bf16_nxv32bf16_bf16:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma176; CHECK-NEXT: vfslide1down.vf v8, v8, fa0177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.nxv32bf16.bf16(180 <vscale x 32 x bfloat> poison,181 <vscale x 32 x bfloat> %0,182 bfloat %1,183 iXLen %2)184 185 ret <vscale x 32 x bfloat> %a186}187 188define <vscale x 32 x bfloat> @intrinsic_vfslide1down_mask_vf_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv32bf16_nxv32bf16_bf16:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, mu192; CHECK-NEXT: vfslide1down.vf v8, v16, fa0, v0.t193; CHECK-NEXT: ret194entry:195 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1down.mask.nxv32bf16.bf16(196 <vscale x 32 x bfloat> %0,197 <vscale x 32 x bfloat> %1,198 bfloat %2,199 <vscale x 32 x i1> %3,200 iXLen %4, iXLen 1)201 202 ret <vscale x 32 x bfloat> %a203}204 205