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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x bfloat> @intrinsic_vfslide1up_vf_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, bfloat %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1bf16_nxv1bf16_bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma11; CHECK-NEXT: vfslide1up.vf v9, v8, fa012; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.nxv1bf16.bf16(16 <vscale x 1 x bfloat> poison,17 <vscale x 1 x bfloat> %0,18 bfloat %1,19 iXLen %2)20 21 ret <vscale x 1 x bfloat> %a22}23 24define <vscale x 1 x bfloat> @intrinsic_vfslide1up_mask_vf_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1bf16_nxv1bf16_bf16:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu28; CHECK-NEXT: vfslide1up.vf v8, v9, fa0, v0.t29; CHECK-NEXT: ret30entry:31 %a = call <vscale x 1 x bfloat> @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16(32 <vscale x 1 x bfloat> %0,33 <vscale x 1 x bfloat> %1,34 bfloat %2,35 <vscale x 1 x i1> %3,36 iXLen %4, iXLen 1)37 38 ret <vscale x 1 x bfloat> %a39}40 41define <vscale x 2 x bfloat> @intrinsic_vfslide1up_vf_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, bfloat %1, iXLen %2) nounwind {42; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2bf16_nxv2bf16_bf16:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma45; CHECK-NEXT: vfslide1up.vf v9, v8, fa046; CHECK-NEXT: vmv1r.v v8, v947; CHECK-NEXT: ret48entry:49 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.nxv2bf16.bf16(50 <vscale x 2 x bfloat> poison,51 <vscale x 2 x bfloat> %0,52 bfloat %1,53 iXLen %2)54 55 ret <vscale x 2 x bfloat> %a56}57 58define <vscale x 2 x bfloat> @intrinsic_vfslide1up_mask_vf_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {59; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2bf16_nxv2bf16_bf16:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu62; CHECK-NEXT: vfslide1up.vf v8, v9, fa0, v0.t63; CHECK-NEXT: ret64entry:65 %a = call <vscale x 2 x bfloat> @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16(66 <vscale x 2 x bfloat> %0,67 <vscale x 2 x bfloat> %1,68 bfloat %2,69 <vscale x 2 x i1> %3,70 iXLen %4, iXLen 1)71 72 ret <vscale x 2 x bfloat> %a73}74 75define <vscale x 4 x bfloat> @intrinsic_vfslide1up_vf_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, bfloat %1, iXLen %2) nounwind {76; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4bf16_nxv4bf16_bf16:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma79; CHECK-NEXT: vfslide1up.vf v9, v8, fa080; CHECK-NEXT: vmv.v.v v8, v981; CHECK-NEXT: ret82entry:83 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.nxv4bf16.bf16(84 <vscale x 4 x bfloat> poison,85 <vscale x 4 x bfloat> %0,86 bfloat %1,87 iXLen %2)88 89 ret <vscale x 4 x bfloat> %a90}91 92define <vscale x 4 x bfloat> @intrinsic_vfslide1up_mask_vf_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {93; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4bf16_nxv4bf16_bf16:94; CHECK: # %bb.0: # %entry95; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu96; CHECK-NEXT: vfslide1up.vf v8, v9, fa0, v0.t97; CHECK-NEXT: ret98entry:99 %a = call <vscale x 4 x bfloat> @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16(100 <vscale x 4 x bfloat> %0,101 <vscale x 4 x bfloat> %1,102 bfloat %2,103 <vscale x 4 x i1> %3,104 iXLen %4, iXLen 1)105 106 ret <vscale x 4 x bfloat> %a107}108 109define <vscale x 8 x bfloat> @intrinsic_vfslide1up_vf_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, bfloat %1, iXLen %2) nounwind {110; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8bf16_nxv8bf16_bf16:111; CHECK: # %bb.0: # %entry112; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma113; CHECK-NEXT: vfslide1up.vf v10, v8, fa0114; CHECK-NEXT: vmv.v.v v8, v10115; CHECK-NEXT: ret116entry:117 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.nxv8bf16.bf16(118 <vscale x 8 x bfloat> poison,119 <vscale x 8 x bfloat> %0,120 bfloat %1,121 iXLen %2)122 123 ret <vscale x 8 x bfloat> %a124}125 126define <vscale x 8 x bfloat> @intrinsic_vfslide1up_mask_vf_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {127; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8bf16_nxv8bf16_bf16:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu130; CHECK-NEXT: vfslide1up.vf v8, v10, fa0, v0.t131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 8 x bfloat> @llvm.riscv.vfslide1up.mask.nxv8bf16.bf16(134 <vscale x 8 x bfloat> %0,135 <vscale x 8 x bfloat> %1,136 bfloat %2,137 <vscale x 8 x i1> %3,138 iXLen %4, iXLen 1)139 140 ret <vscale x 8 x bfloat> %a141}142 143define <vscale x 16 x bfloat> @intrinsic_vfslide1up_vf_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, bfloat %1, iXLen %2) nounwind {144; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv16bf16_nxv16bf16_bf16:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma147; CHECK-NEXT: vfslide1up.vf v12, v8, fa0148; CHECK-NEXT: vmv.v.v v8, v12149; CHECK-NEXT: ret150entry:151 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.nxv16bf16.bf16(152 <vscale x 16 x bfloat> poison,153 <vscale x 16 x bfloat> %0,154 bfloat %1,155 iXLen %2)156 157 ret <vscale x 16 x bfloat> %a158}159 160define <vscale x 16 x bfloat> @intrinsic_vfslide1up_mask_vf_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {161; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16bf16_nxv16bf16_bf16:162; CHECK: # %bb.0: # %entry163; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu164; CHECK-NEXT: vfslide1up.vf v8, v12, fa0, v0.t165; CHECK-NEXT: ret166entry:167 %a = call <vscale x 16 x bfloat> @llvm.riscv.vfslide1up.mask.nxv16bf16.bf16(168 <vscale x 16 x bfloat> %0,169 <vscale x 16 x bfloat> %1,170 bfloat %2,171 <vscale x 16 x i1> %3,172 iXLen %4, iXLen 1)173 174 ret <vscale x 16 x bfloat> %a175}176 177define <vscale x 32 x bfloat> @intrinsic_vfslide1up_vf_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, bfloat %1, iXLen %2) nounwind {178; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv32bf16_nxv32bf16_bf16:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma181; CHECK-NEXT: vfslide1up.vf v16, v8, fa0182; CHECK-NEXT: vmv.v.v v8, v16183; CHECK-NEXT: ret184entry:185 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.nxv32bf16.bf16(186 <vscale x 32 x bfloat> poison,187 <vscale x 32 x bfloat> %0,188 bfloat %1,189 iXLen %2)190 191 ret <vscale x 32 x bfloat> %a192}193 194define <vscale x 32 x bfloat> @intrinsic_vfslide1up_mask_vf_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {195; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv32bf16_nxv32bf16_bf16:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, mu198; CHECK-NEXT: vfslide1up.vf v8, v16, fa0, v0.t199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 32 x bfloat> @llvm.riscv.vfslide1up.mask.nxv32bf16.bf16(202 <vscale x 32 x bfloat> %0,203 <vscale x 32 x bfloat> %1,204 bfloat %2,205 <vscale x 32 x i1> %3,206 iXLen %4, iXLen 1)207 208 ret <vscale x 32 x bfloat> %a209}210 211