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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vfslide1up.vf v9, v8, fa012; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(16 <vscale x 1 x half> poison,17 <vscale x 1 x half> %0,18 half %1,19 iXLen %2)20 21 ret <vscale x 1 x half> %a22}23 24define <vscale x 1 x half> @intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu28; CHECK-NEXT: vfslide1up.vf v8, v9, fa0, v0.t29; CHECK-NEXT: ret30entry:31 %a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.mask.nxv1f16.f16(32 <vscale x 1 x half> %0,33 <vscale x 1 x half> %1,34 half %2,35 <vscale x 1 x i1> %3,36 iXLen %4, iXLen 1)37 38 ret <vscale x 1 x half> %a39}40 41define <vscale x 2 x half> @intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {42; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma45; CHECK-NEXT: vfslide1up.vf v9, v8, fa046; CHECK-NEXT: vmv1r.v v8, v947; CHECK-NEXT: ret48entry:49 %a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16(50 <vscale x 2 x half> poison,51 <vscale x 2 x half> %0,52 half %1,53 iXLen %2)54 55 ret <vscale x 2 x half> %a56}57 58define <vscale x 2 x half> @intrinsic_vfslide1up_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {59; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f16_nxv2f16_f16:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu62; CHECK-NEXT: vfslide1up.vf v8, v9, fa0, v0.t63; CHECK-NEXT: ret64entry:65 %a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.mask.nxv2f16.f16(66 <vscale x 2 x half> %0,67 <vscale x 2 x half> %1,68 half %2,69 <vscale x 2 x i1> %3,70 iXLen %4, iXLen 1)71 72 ret <vscale x 2 x half> %a73}74 75define <vscale x 4 x half> @intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {76; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma79; CHECK-NEXT: vfslide1up.vf v9, v8, fa080; CHECK-NEXT: vmv.v.v v8, v981; CHECK-NEXT: ret82entry:83 %a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16(84 <vscale x 4 x half> poison,85 <vscale x 4 x half> %0,86 half %1,87 iXLen %2)88 89 ret <vscale x 4 x half> %a90}91 92define <vscale x 4 x half> @intrinsic_vfslide1up_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {93; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f16_nxv4f16_f16:94; CHECK: # %bb.0: # %entry95; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu96; CHECK-NEXT: vfslide1up.vf v8, v9, fa0, v0.t97; CHECK-NEXT: ret98entry:99 %a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.mask.nxv4f16.f16(100 <vscale x 4 x half> %0,101 <vscale x 4 x half> %1,102 half %2,103 <vscale x 4 x i1> %3,104 iXLen %4, iXLen 1)105 106 ret <vscale x 4 x half> %a107}108 109define <vscale x 8 x half> @intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {110; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16:111; CHECK: # %bb.0: # %entry112; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma113; CHECK-NEXT: vfslide1up.vf v10, v8, fa0114; CHECK-NEXT: vmv.v.v v8, v10115; CHECK-NEXT: ret116entry:117 %a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16(118 <vscale x 8 x half> poison,119 <vscale x 8 x half> %0,120 half %1,121 iXLen %2)122 123 ret <vscale x 8 x half> %a124}125 126define <vscale x 8 x half> @intrinsic_vfslide1up_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {127; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f16_nxv8f16_f16:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu130; CHECK-NEXT: vfslide1up.vf v8, v10, fa0, v0.t131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.mask.nxv8f16.f16(134 <vscale x 8 x half> %0,135 <vscale x 8 x half> %1,136 half %2,137 <vscale x 8 x i1> %3,138 iXLen %4, iXLen 1)139 140 ret <vscale x 8 x half> %a141}142 143define <vscale x 16 x half> @intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {144; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma147; CHECK-NEXT: vfslide1up.vf v12, v8, fa0148; CHECK-NEXT: vmv.v.v v8, v12149; CHECK-NEXT: ret150entry:151 %a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16(152 <vscale x 16 x half> poison,153 <vscale x 16 x half> %0,154 half %1,155 iXLen %2)156 157 ret <vscale x 16 x half> %a158}159 160define <vscale x 16 x half> @intrinsic_vfslide1up_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {161; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f16_nxv16f16_f16:162; CHECK: # %bb.0: # %entry163; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu164; CHECK-NEXT: vfslide1up.vf v8, v12, fa0, v0.t165; CHECK-NEXT: ret166entry:167 %a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.mask.nxv16f16.f16(168 <vscale x 16 x half> %0,169 <vscale x 16 x half> %1,170 half %2,171 <vscale x 16 x i1> %3,172 iXLen %4, iXLen 1)173 174 ret <vscale x 16 x half> %a175}176 177define <vscale x 32 x half> @intrinsic_vfslide1up_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, iXLen %2) nounwind {178; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv32f16_nxv32f16_f16:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma181; CHECK-NEXT: vfslide1up.vf v16, v8, fa0182; CHECK-NEXT: vmv.v.v v8, v16183; CHECK-NEXT: ret184entry:185 %a = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16(186 <vscale x 32 x half> poison,187 <vscale x 32 x half> %0,188 half %1,189 iXLen %2)190 191 ret <vscale x 32 x half> %a192}193 194define <vscale x 32 x half> @intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {195; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu198; CHECK-NEXT: vfslide1up.vf v8, v16, fa0, v0.t199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 32 x half> @llvm.riscv.vfslide1up.mask.nxv32f16.f16(202 <vscale x 32 x half> %0,203 <vscale x 32 x half> %1,204 half %2,205 <vscale x 32 x i1> %3,206 iXLen %4, iXLen 1)207 208 ret <vscale x 32 x half> %a209}210 211define <vscale x 1 x float> @intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {212; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32:213; CHECK: # %bb.0: # %entry214; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma215; CHECK-NEXT: vfslide1up.vf v9, v8, fa0216; CHECK-NEXT: vmv1r.v v8, v9217; CHECK-NEXT: ret218entry:219 %a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32(220 <vscale x 1 x float> poison,221 <vscale x 1 x float> %0,222 float %1,223 iXLen %2)224 225 ret <vscale x 1 x float> %a226}227 228define <vscale x 1 x float> @intrinsic_vfslide1up_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {229; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f32_nxv1f32_f32:230; CHECK: # %bb.0: # %entry231; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu232; CHECK-NEXT: vfslide1up.vf v8, v9, fa0, v0.t233; CHECK-NEXT: ret234entry:235 %a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32(236 <vscale x 1 x float> %0,237 <vscale x 1 x float> %1,238 float %2,239 <vscale x 1 x i1> %3,240 iXLen %4, iXLen 1)241 242 ret <vscale x 1 x float> %a243}244 245define <vscale x 2 x float> @intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {246; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32:247; CHECK: # %bb.0: # %entry248; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma249; CHECK-NEXT: vfslide1up.vf v9, v8, fa0250; CHECK-NEXT: vmv.v.v v8, v9251; CHECK-NEXT: ret252entry:253 %a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32(254 <vscale x 2 x float> poison,255 <vscale x 2 x float> %0,256 float %1,257 iXLen %2)258 259 ret <vscale x 2 x float> %a260}261 262define <vscale x 2 x float> @intrinsic_vfslide1up_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {263; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f32_nxv2f32_f32:264; CHECK: # %bb.0: # %entry265; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu266; CHECK-NEXT: vfslide1up.vf v8, v9, fa0, v0.t267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32(270 <vscale x 2 x float> %0,271 <vscale x 2 x float> %1,272 float %2,273 <vscale x 2 x i1> %3,274 iXLen %4, iXLen 1)275 276 ret <vscale x 2 x float> %a277}278 279define <vscale x 4 x float> @intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {280; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma283; CHECK-NEXT: vfslide1up.vf v10, v8, fa0284; CHECK-NEXT: vmv.v.v v8, v10285; CHECK-NEXT: ret286entry:287 %a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32(288 <vscale x 4 x float> poison,289 <vscale x 4 x float> %0,290 float %1,291 iXLen %2)292 293 ret <vscale x 4 x float> %a294}295 296define <vscale x 4 x float> @intrinsic_vfslide1up_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {297; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f32_nxv4f32_f32:298; CHECK: # %bb.0: # %entry299; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu300; CHECK-NEXT: vfslide1up.vf v8, v10, fa0, v0.t301; CHECK-NEXT: ret302entry:303 %a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32(304 <vscale x 4 x float> %0,305 <vscale x 4 x float> %1,306 float %2,307 <vscale x 4 x i1> %3,308 iXLen %4, iXLen 1)309 310 ret <vscale x 4 x float> %a311}312 313define <vscale x 8 x float> @intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {314; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32:315; CHECK: # %bb.0: # %entry316; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma317; CHECK-NEXT: vfslide1up.vf v12, v8, fa0318; CHECK-NEXT: vmv.v.v v8, v12319; CHECK-NEXT: ret320entry:321 %a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32(322 <vscale x 8 x float> poison,323 <vscale x 8 x float> %0,324 float %1,325 iXLen %2)326 327 ret <vscale x 8 x float> %a328}329 330define <vscale x 8 x float> @intrinsic_vfslide1up_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {331; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f32_nxv8f32_f32:332; CHECK: # %bb.0: # %entry333; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu334; CHECK-NEXT: vfslide1up.vf v8, v12, fa0, v0.t335; CHECK-NEXT: ret336entry:337 %a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32(338 <vscale x 8 x float> %0,339 <vscale x 8 x float> %1,340 float %2,341 <vscale x 8 x i1> %3,342 iXLen %4, iXLen 1)343 344 ret <vscale x 8 x float> %a345}346 347define <vscale x 16 x float> @intrinsic_vfslide1up_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, iXLen %2) nounwind {348; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv16f32_nxv16f32_f32:349; CHECK: # %bb.0: # %entry350; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma351; CHECK-NEXT: vfslide1up.vf v16, v8, fa0352; CHECK-NEXT: vmv.v.v v8, v16353; CHECK-NEXT: ret354entry:355 %a = call <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32(356 <vscale x 16 x float> poison,357 <vscale x 16 x float> %0,358 float %1,359 iXLen %2)360 361 ret <vscale x 16 x float> %a362}363 364define <vscale x 16 x float> @intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {365; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32:366; CHECK: # %bb.0: # %entry367; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu368; CHECK-NEXT: vfslide1up.vf v8, v16, fa0, v0.t369; CHECK-NEXT: ret370entry:371 %a = call <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32(372 <vscale x 16 x float> %0,373 <vscale x 16 x float> %1,374 float %2,375 <vscale x 16 x i1> %3,376 iXLen %4, iXLen 1)377 378 ret <vscale x 16 x float> %a379}380 381define <vscale x 1 x double> @intrinsic_vfslide1up_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {382; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f64_nxv1f64_f64:383; CHECK: # %bb.0: # %entry384; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma385; CHECK-NEXT: vfslide1up.vf v9, v8, fa0386; CHECK-NEXT: vmv.v.v v8, v9387; CHECK-NEXT: ret388entry:389 %a = call <vscale x 1 x double> @llvm.riscv.vfslide1up.nxv1f64.f64(390 <vscale x 1 x double> poison,391 <vscale x 1 x double> %0,392 double %1,393 iXLen %2)394 395 ret <vscale x 1 x double> %a396}397 398define <vscale x 1 x double> @intrinsic_vfslide1up_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {399; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f64_nxv1f64_f64:400; CHECK: # %bb.0: # %entry401; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu402; CHECK-NEXT: vfslide1up.vf v8, v9, fa0, v0.t403; CHECK-NEXT: ret404entry:405 %a = call <vscale x 1 x double> @llvm.riscv.vfslide1up.mask.nxv1f64.f64(406 <vscale x 1 x double> %0,407 <vscale x 1 x double> %1,408 double %2,409 <vscale x 1 x i1> %3,410 iXLen %4, iXLen 1)411 412 ret <vscale x 1 x double> %a413}414 415define <vscale x 2 x double> @intrinsic_vfslide1up_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {416; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f64_nxv2f64_f64:417; CHECK: # %bb.0: # %entry418; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma419; CHECK-NEXT: vfslide1up.vf v10, v8, fa0420; CHECK-NEXT: vmv.v.v v8, v10421; CHECK-NEXT: ret422entry:423 %a = call <vscale x 2 x double> @llvm.riscv.vfslide1up.nxv2f64.f64(424 <vscale x 2 x double> poison,425 <vscale x 2 x double> %0,426 double %1,427 iXLen %2)428 429 ret <vscale x 2 x double> %a430}431 432define <vscale x 2 x double> @intrinsic_vfslide1up_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {433; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f64_nxv2f64_f64:434; CHECK: # %bb.0: # %entry435; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu436; CHECK-NEXT: vfslide1up.vf v8, v10, fa0, v0.t437; CHECK-NEXT: ret438entry:439 %a = call <vscale x 2 x double> @llvm.riscv.vfslide1up.mask.nxv2f64.f64(440 <vscale x 2 x double> %0,441 <vscale x 2 x double> %1,442 double %2,443 <vscale x 2 x i1> %3,444 iXLen %4, iXLen 1)445 446 ret <vscale x 2 x double> %a447}448 449define <vscale x 4 x double> @intrinsic_vfslide1up_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {450; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f64_nxv4f64_f64:451; CHECK: # %bb.0: # %entry452; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma453; CHECK-NEXT: vfslide1up.vf v12, v8, fa0454; CHECK-NEXT: vmv.v.v v8, v12455; CHECK-NEXT: ret456entry:457 %a = call <vscale x 4 x double> @llvm.riscv.vfslide1up.nxv4f64.f64(458 <vscale x 4 x double> poison,459 <vscale x 4 x double> %0,460 double %1,461 iXLen %2)462 463 ret <vscale x 4 x double> %a464}465 466define <vscale x 4 x double> @intrinsic_vfslide1up_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {467; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f64_nxv4f64_f64:468; CHECK: # %bb.0: # %entry469; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu470; CHECK-NEXT: vfslide1up.vf v8, v12, fa0, v0.t471; CHECK-NEXT: ret472entry:473 %a = call <vscale x 4 x double> @llvm.riscv.vfslide1up.mask.nxv4f64.f64(474 <vscale x 4 x double> %0,475 <vscale x 4 x double> %1,476 double %2,477 <vscale x 4 x i1> %3,478 iXLen %4, iXLen 1)479 480 ret <vscale x 4 x double> %a481}482 483define <vscale x 8 x double> @intrinsic_vfslide1up_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, iXLen %2) nounwind {484; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f64_nxv8f64_f64:485; CHECK: # %bb.0: # %entry486; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma487; CHECK-NEXT: vfslide1up.vf v16, v8, fa0488; CHECK-NEXT: vmv.v.v v8, v16489; CHECK-NEXT: ret490entry:491 %a = call <vscale x 8 x double> @llvm.riscv.vfslide1up.nxv8f64.f64(492 <vscale x 8 x double> poison,493 <vscale x 8 x double> %0,494 double %1,495 iXLen %2)496 497 ret <vscale x 8 x double> %a498}499 500define <vscale x 8 x double> @intrinsic_vfslide1up_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {501; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f64_nxv8f64_f64:502; CHECK: # %bb.0: # %entry503; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu504; CHECK-NEXT: vfslide1up.vf v8, v16, fa0, v0.t505; CHECK-NEXT: ret506entry:507 %a = call <vscale x 8 x double> @llvm.riscv.vfslide1up.mask.nxv8f64.f64(508 <vscale x 8 x double> %0,509 <vscale x 8 x double> %1,510 double %2,511 <vscale x 8 x i1> %3,512 iXLen %4, iXLen 1)513 514 ret <vscale x 8 x double> %a515}516