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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN14 15define <vscale x 1 x bfloat> @vfsqrt_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {16; CHECK-LABEL: vfsqrt_vv_nxv1bf16:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma19; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t20; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma21; CHECK-NEXT: vfsqrt.v v9, v9, v0.t22; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma23; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t24; CHECK-NEXT: ret25 %v = call <vscale x 1 x bfloat> @llvm.vp.sqrt.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)26 ret <vscale x 1 x bfloat> %v27}28 29define <vscale x 1 x bfloat> @vfsqrt_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, i32 zeroext %evl) {30; CHECK-LABEL: vfsqrt_vv_nxv1bf16_unmasked:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma33; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v834; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma35; CHECK-NEXT: vfsqrt.v v9, v936; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma37; CHECK-NEXT: vfncvtbf16.f.f.w v8, v938; CHECK-NEXT: ret39 %v = call <vscale x 1 x bfloat> @llvm.vp.sqrt.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)40 ret <vscale x 1 x bfloat> %v41}42 43define <vscale x 2 x bfloat> @vfsqrt_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {44; CHECK-LABEL: vfsqrt_vv_nxv2bf16:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma47; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t48; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma49; CHECK-NEXT: vfsqrt.v v9, v9, v0.t50; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma51; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t52; CHECK-NEXT: ret53 %v = call <vscale x 2 x bfloat> @llvm.vp.sqrt.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)54 ret <vscale x 2 x bfloat> %v55}56 57define <vscale x 2 x bfloat> @vfsqrt_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, i32 zeroext %evl) {58; CHECK-LABEL: vfsqrt_vv_nxv2bf16_unmasked:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma61; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v862; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma63; CHECK-NEXT: vfsqrt.v v9, v964; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma65; CHECK-NEXT: vfncvtbf16.f.f.w v8, v966; CHECK-NEXT: ret67 %v = call <vscale x 2 x bfloat> @llvm.vp.sqrt.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)68 ret <vscale x 2 x bfloat> %v69}70 71define <vscale x 4 x bfloat> @vfsqrt_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {72; CHECK-LABEL: vfsqrt_vv_nxv4bf16:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma75; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t76; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma77; CHECK-NEXT: vfsqrt.v v10, v10, v0.t78; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma79; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t80; CHECK-NEXT: ret81 %v = call <vscale x 4 x bfloat> @llvm.vp.sqrt.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 %evl)82 ret <vscale x 4 x bfloat> %v83}84 85define <vscale x 4 x bfloat> @vfsqrt_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, i32 zeroext %evl) {86; CHECK-LABEL: vfsqrt_vv_nxv4bf16_unmasked:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma89; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v890; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma91; CHECK-NEXT: vfsqrt.v v10, v1092; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma93; CHECK-NEXT: vfncvtbf16.f.f.w v8, v1094; CHECK-NEXT: ret95 %v = call <vscale x 4 x bfloat> @llvm.vp.sqrt.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)96 ret <vscale x 4 x bfloat> %v97}98 99define <vscale x 8 x bfloat> @vfsqrt_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {100; CHECK-LABEL: vfsqrt_vv_nxv8bf16:101; CHECK: # %bb.0:102; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma103; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t104; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma105; CHECK-NEXT: vfsqrt.v v12, v12, v0.t106; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma107; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t108; CHECK-NEXT: ret109 %v = call <vscale x 8 x bfloat> @llvm.vp.sqrt.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 %evl)110 ret <vscale x 8 x bfloat> %v111}112 113define <vscale x 8 x bfloat> @vfsqrt_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, i32 zeroext %evl) {114; CHECK-LABEL: vfsqrt_vv_nxv8bf16_unmasked:115; CHECK: # %bb.0:116; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma117; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8118; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma119; CHECK-NEXT: vfsqrt.v v12, v12120; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma121; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12122; CHECK-NEXT: ret123 %v = call <vscale x 8 x bfloat> @llvm.vp.sqrt.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)124 ret <vscale x 8 x bfloat> %v125}126 127define <vscale x 16 x bfloat> @vfsqrt_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {128; CHECK-LABEL: vfsqrt_vv_nxv16bf16:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma131; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t132; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma133; CHECK-NEXT: vfsqrt.v v16, v16, v0.t134; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma135; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t136; CHECK-NEXT: ret137 %v = call <vscale x 16 x bfloat> @llvm.vp.sqrt.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 %evl)138 ret <vscale x 16 x bfloat> %v139}140 141define <vscale x 16 x bfloat> @vfsqrt_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, i32 zeroext %evl) {142; CHECK-LABEL: vfsqrt_vv_nxv16bf16_unmasked:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma145; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8146; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma147; CHECK-NEXT: vfsqrt.v v16, v16148; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma149; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16150; CHECK-NEXT: ret151 %v = call <vscale x 16 x bfloat> @llvm.vp.sqrt.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)152 ret <vscale x 16 x bfloat> %v153}154 155define <vscale x 32 x bfloat> @vfsqrt_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {156; CHECK-LABEL: vfsqrt_vv_nxv32bf16:157; CHECK: # %bb.0:158; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma159; CHECK-NEXT: vmv1r.v v16, v0160; CHECK-NEXT: csrr a2, vlenb161; CHECK-NEXT: slli a1, a2, 1162; CHECK-NEXT: srli a2, a2, 2163; CHECK-NEXT: sub a3, a0, a1164; CHECK-NEXT: sltu a4, a0, a3165; CHECK-NEXT: addi a4, a4, -1166; CHECK-NEXT: vslidedown.vx v0, v0, a2167; CHECK-NEXT: and a3, a4, a3168; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma169; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t170; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma171; CHECK-NEXT: vfsqrt.v v24, v24, v0.t172; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma173; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t174; CHECK-NEXT: bltu a0, a1, .LBB10_2175; CHECK-NEXT: # %bb.1:176; CHECK-NEXT: mv a0, a1177; CHECK-NEXT: .LBB10_2:178; CHECK-NEXT: vmv1r.v v0, v16179; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma180; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t181; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma182; CHECK-NEXT: vfsqrt.v v24, v24, v0.t183; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma184; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t185; CHECK-NEXT: ret186 %v = call <vscale x 32 x bfloat> @llvm.vp.sqrt.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)187 ret <vscale x 32 x bfloat> %v188}189 190define <vscale x 32 x bfloat> @vfsqrt_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, i32 zeroext %evl) {191; CHECK-LABEL: vfsqrt_vv_nxv32bf16_unmasked:192; CHECK: # %bb.0:193; CHECK-NEXT: csrr a2, vlenb194; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma195; CHECK-NEXT: vmset.m v16196; CHECK-NEXT: slli a1, a2, 1197; CHECK-NEXT: srli a2, a2, 2198; CHECK-NEXT: sub a3, a0, a1199; CHECK-NEXT: sltu a4, a0, a3200; CHECK-NEXT: addi a4, a4, -1201; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma202; CHECK-NEXT: vslidedown.vx v0, v16, a2203; CHECK-NEXT: and a3, a4, a3204; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma205; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t206; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma207; CHECK-NEXT: vfsqrt.v v16, v16, v0.t208; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma209; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t210; CHECK-NEXT: bltu a0, a1, .LBB11_2211; CHECK-NEXT: # %bb.1:212; CHECK-NEXT: mv a0, a1213; CHECK-NEXT: .LBB11_2:214; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma215; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8216; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma217; CHECK-NEXT: vfsqrt.v v16, v16218; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma219; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16220; CHECK-NEXT: ret221 %v = call <vscale x 32 x bfloat> @llvm.vp.sqrt.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)222 ret <vscale x 32 x bfloat> %v223}224 225define <vscale x 1 x half> @vfsqrt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {226; ZVFH-LABEL: vfsqrt_vv_nxv1f16:227; ZVFH: # %bb.0:228; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma229; ZVFH-NEXT: vfsqrt.v v8, v8, v0.t230; ZVFH-NEXT: ret231;232; ZVFHMIN-LABEL: vfsqrt_vv_nxv1f16:233; ZVFHMIN: # %bb.0:234; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma235; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t236; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma237; ZVFHMIN-NEXT: vfsqrt.v v9, v9, v0.t238; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma239; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t240; ZVFHMIN-NEXT: ret241 %v = call <vscale x 1 x half> @llvm.vp.sqrt.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)242 ret <vscale x 1 x half> %v243}244 245define <vscale x 1 x half> @vfsqrt_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, i32 zeroext %evl) {246; ZVFH-LABEL: vfsqrt_vv_nxv1f16_unmasked:247; ZVFH: # %bb.0:248; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma249; ZVFH-NEXT: vfsqrt.v v8, v8250; ZVFH-NEXT: ret251;252; ZVFHMIN-LABEL: vfsqrt_vv_nxv1f16_unmasked:253; ZVFHMIN: # %bb.0:254; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma255; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8256; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma257; ZVFHMIN-NEXT: vfsqrt.v v9, v9258; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma259; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9260; ZVFHMIN-NEXT: ret261 %v = call <vscale x 1 x half> @llvm.vp.sqrt.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)262 ret <vscale x 1 x half> %v263}264 265define <vscale x 2 x half> @vfsqrt_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {266; ZVFH-LABEL: vfsqrt_vv_nxv2f16:267; ZVFH: # %bb.0:268; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma269; ZVFH-NEXT: vfsqrt.v v8, v8, v0.t270; ZVFH-NEXT: ret271;272; ZVFHMIN-LABEL: vfsqrt_vv_nxv2f16:273; ZVFHMIN: # %bb.0:274; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma275; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t276; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma277; ZVFHMIN-NEXT: vfsqrt.v v9, v9, v0.t278; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma279; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t280; ZVFHMIN-NEXT: ret281 %v = call <vscale x 2 x half> @llvm.vp.sqrt.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)282 ret <vscale x 2 x half> %v283}284 285define <vscale x 2 x half> @vfsqrt_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {286; ZVFH-LABEL: vfsqrt_vv_nxv2f16_unmasked:287; ZVFH: # %bb.0:288; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma289; ZVFH-NEXT: vfsqrt.v v8, v8290; ZVFH-NEXT: ret291;292; ZVFHMIN-LABEL: vfsqrt_vv_nxv2f16_unmasked:293; ZVFHMIN: # %bb.0:294; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma295; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8296; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma297; ZVFHMIN-NEXT: vfsqrt.v v9, v9298; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma299; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9300; ZVFHMIN-NEXT: ret301 %v = call <vscale x 2 x half> @llvm.vp.sqrt.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)302 ret <vscale x 2 x half> %v303}304 305define <vscale x 4 x half> @vfsqrt_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {306; ZVFH-LABEL: vfsqrt_vv_nxv4f16:307; ZVFH: # %bb.0:308; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma309; ZVFH-NEXT: vfsqrt.v v8, v8, v0.t310; ZVFH-NEXT: ret311;312; ZVFHMIN-LABEL: vfsqrt_vv_nxv4f16:313; ZVFHMIN: # %bb.0:314; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma315; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t316; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma317; ZVFHMIN-NEXT: vfsqrt.v v10, v10, v0.t318; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma319; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t320; ZVFHMIN-NEXT: ret321 %v = call <vscale x 4 x half> @llvm.vp.sqrt.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 %evl)322 ret <vscale x 4 x half> %v323}324 325define <vscale x 4 x half> @vfsqrt_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, i32 zeroext %evl) {326; ZVFH-LABEL: vfsqrt_vv_nxv4f16_unmasked:327; ZVFH: # %bb.0:328; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma329; ZVFH-NEXT: vfsqrt.v v8, v8330; ZVFH-NEXT: ret331;332; ZVFHMIN-LABEL: vfsqrt_vv_nxv4f16_unmasked:333; ZVFHMIN: # %bb.0:334; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma335; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8336; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma337; ZVFHMIN-NEXT: vfsqrt.v v10, v10338; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma339; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10340; ZVFHMIN-NEXT: ret341 %v = call <vscale x 4 x half> @llvm.vp.sqrt.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)342 ret <vscale x 4 x half> %v343}344 345define <vscale x 8 x half> @vfsqrt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {346; ZVFH-LABEL: vfsqrt_vv_nxv8f16:347; ZVFH: # %bb.0:348; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma349; ZVFH-NEXT: vfsqrt.v v8, v8, v0.t350; ZVFH-NEXT: ret351;352; ZVFHMIN-LABEL: vfsqrt_vv_nxv8f16:353; ZVFHMIN: # %bb.0:354; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma355; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t356; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma357; ZVFHMIN-NEXT: vfsqrt.v v12, v12, v0.t358; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma359; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t360; ZVFHMIN-NEXT: ret361 %v = call <vscale x 8 x half> @llvm.vp.sqrt.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 %evl)362 ret <vscale x 8 x half> %v363}364 365define <vscale x 8 x half> @vfsqrt_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, i32 zeroext %evl) {366; ZVFH-LABEL: vfsqrt_vv_nxv8f16_unmasked:367; ZVFH: # %bb.0:368; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma369; ZVFH-NEXT: vfsqrt.v v8, v8370; ZVFH-NEXT: ret371;372; ZVFHMIN-LABEL: vfsqrt_vv_nxv8f16_unmasked:373; ZVFHMIN: # %bb.0:374; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma375; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8376; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma377; ZVFHMIN-NEXT: vfsqrt.v v12, v12378; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma379; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12380; ZVFHMIN-NEXT: ret381 %v = call <vscale x 8 x half> @llvm.vp.sqrt.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)382 ret <vscale x 8 x half> %v383}384 385define <vscale x 16 x half> @vfsqrt_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {386; ZVFH-LABEL: vfsqrt_vv_nxv16f16:387; ZVFH: # %bb.0:388; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma389; ZVFH-NEXT: vfsqrt.v v8, v8, v0.t390; ZVFH-NEXT: ret391;392; ZVFHMIN-LABEL: vfsqrt_vv_nxv16f16:393; ZVFHMIN: # %bb.0:394; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma395; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t396; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma397; ZVFHMIN-NEXT: vfsqrt.v v16, v16, v0.t398; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma399; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t400; ZVFHMIN-NEXT: ret401 %v = call <vscale x 16 x half> @llvm.vp.sqrt.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 %evl)402 ret <vscale x 16 x half> %v403}404 405define <vscale x 16 x half> @vfsqrt_vv_nxv16f16_unmasked(<vscale x 16 x half> %va, i32 zeroext %evl) {406; ZVFH-LABEL: vfsqrt_vv_nxv16f16_unmasked:407; ZVFH: # %bb.0:408; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma409; ZVFH-NEXT: vfsqrt.v v8, v8410; ZVFH-NEXT: ret411;412; ZVFHMIN-LABEL: vfsqrt_vv_nxv16f16_unmasked:413; ZVFHMIN: # %bb.0:414; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma415; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8416; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma417; ZVFHMIN-NEXT: vfsqrt.v v16, v16418; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma419; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16420; ZVFHMIN-NEXT: ret421 %v = call <vscale x 16 x half> @llvm.vp.sqrt.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)422 ret <vscale x 16 x half> %v423}424 425define <vscale x 32 x half> @vfsqrt_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {426; ZVFH-LABEL: vfsqrt_vv_nxv32f16:427; ZVFH: # %bb.0:428; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma429; ZVFH-NEXT: vfsqrt.v v8, v8, v0.t430; ZVFH-NEXT: ret431;432; ZVFHMIN-LABEL: vfsqrt_vv_nxv32f16:433; ZVFHMIN: # %bb.0:434; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma435; ZVFHMIN-NEXT: vmv1r.v v16, v0436; ZVFHMIN-NEXT: csrr a2, vlenb437; ZVFHMIN-NEXT: slli a1, a2, 1438; ZVFHMIN-NEXT: srli a2, a2, 2439; ZVFHMIN-NEXT: sub a3, a0, a1440; ZVFHMIN-NEXT: sltu a4, a0, a3441; ZVFHMIN-NEXT: addi a4, a4, -1442; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2443; ZVFHMIN-NEXT: and a3, a4, a3444; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma445; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t446; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma447; ZVFHMIN-NEXT: vfsqrt.v v24, v24, v0.t448; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma449; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t450; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2451; ZVFHMIN-NEXT: # %bb.1:452; ZVFHMIN-NEXT: mv a0, a1453; ZVFHMIN-NEXT: .LBB22_2:454; ZVFHMIN-NEXT: vmv1r.v v0, v16455; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma456; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t457; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma458; ZVFHMIN-NEXT: vfsqrt.v v24, v24, v0.t459; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma460; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t461; ZVFHMIN-NEXT: ret462 %v = call <vscale x 32 x half> @llvm.vp.sqrt.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)463 ret <vscale x 32 x half> %v464}465 466define <vscale x 32 x half> @vfsqrt_vv_nxv32f16_unmasked(<vscale x 32 x half> %va, i32 zeroext %evl) {467; ZVFH-LABEL: vfsqrt_vv_nxv32f16_unmasked:468; ZVFH: # %bb.0:469; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma470; ZVFH-NEXT: vfsqrt.v v8, v8471; ZVFH-NEXT: ret472;473; ZVFHMIN-LABEL: vfsqrt_vv_nxv32f16_unmasked:474; ZVFHMIN: # %bb.0:475; ZVFHMIN-NEXT: csrr a2, vlenb476; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma477; ZVFHMIN-NEXT: vmset.m v16478; ZVFHMIN-NEXT: slli a1, a2, 1479; ZVFHMIN-NEXT: srli a2, a2, 2480; ZVFHMIN-NEXT: sub a3, a0, a1481; ZVFHMIN-NEXT: sltu a4, a0, a3482; ZVFHMIN-NEXT: addi a4, a4, -1483; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma484; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2485; ZVFHMIN-NEXT: and a3, a4, a3486; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma487; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t488; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma489; ZVFHMIN-NEXT: vfsqrt.v v16, v16, v0.t490; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma491; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t492; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2493; ZVFHMIN-NEXT: # %bb.1:494; ZVFHMIN-NEXT: mv a0, a1495; ZVFHMIN-NEXT: .LBB23_2:496; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma497; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8498; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma499; ZVFHMIN-NEXT: vfsqrt.v v16, v16500; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma501; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16502; ZVFHMIN-NEXT: ret503 %v = call <vscale x 32 x half> @llvm.vp.sqrt.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)504 ret <vscale x 32 x half> %v505}506 507define <vscale x 1 x float> @vfsqrt_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {508; CHECK-LABEL: vfsqrt_vv_nxv1f32:509; CHECK: # %bb.0:510; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma511; CHECK-NEXT: vfsqrt.v v8, v8, v0.t512; CHECK-NEXT: ret513 %v = call <vscale x 1 x float> @llvm.vp.sqrt.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 %evl)514 ret <vscale x 1 x float> %v515}516 517define <vscale x 1 x float> @vfsqrt_vv_nxv1f32_unmasked(<vscale x 1 x float> %va, i32 zeroext %evl) {518; CHECK-LABEL: vfsqrt_vv_nxv1f32_unmasked:519; CHECK: # %bb.0:520; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma521; CHECK-NEXT: vfsqrt.v v8, v8522; CHECK-NEXT: ret523 %v = call <vscale x 1 x float> @llvm.vp.sqrt.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)524 ret <vscale x 1 x float> %v525}526 527define <vscale x 2 x float> @vfsqrt_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {528; CHECK-LABEL: vfsqrt_vv_nxv2f32:529; CHECK: # %bb.0:530; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma531; CHECK-NEXT: vfsqrt.v v8, v8, v0.t532; CHECK-NEXT: ret533 %v = call <vscale x 2 x float> @llvm.vp.sqrt.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)534 ret <vscale x 2 x float> %v535}536 537define <vscale x 2 x float> @vfsqrt_vv_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {538; CHECK-LABEL: vfsqrt_vv_nxv2f32_unmasked:539; CHECK: # %bb.0:540; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma541; CHECK-NEXT: vfsqrt.v v8, v8542; CHECK-NEXT: ret543 %v = call <vscale x 2 x float> @llvm.vp.sqrt.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)544 ret <vscale x 2 x float> %v545}546 547define <vscale x 4 x float> @vfsqrt_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {548; CHECK-LABEL: vfsqrt_vv_nxv4f32:549; CHECK: # %bb.0:550; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma551; CHECK-NEXT: vfsqrt.v v8, v8, v0.t552; CHECK-NEXT: ret553 %v = call <vscale x 4 x float> @llvm.vp.sqrt.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 %evl)554 ret <vscale x 4 x float> %v555}556 557define <vscale x 4 x float> @vfsqrt_vv_nxv4f32_unmasked(<vscale x 4 x float> %va, i32 zeroext %evl) {558; CHECK-LABEL: vfsqrt_vv_nxv4f32_unmasked:559; CHECK: # %bb.0:560; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma561; CHECK-NEXT: vfsqrt.v v8, v8562; CHECK-NEXT: ret563 %v = call <vscale x 4 x float> @llvm.vp.sqrt.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)564 ret <vscale x 4 x float> %v565}566 567define <vscale x 8 x float> @vfsqrt_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {568; CHECK-LABEL: vfsqrt_vv_nxv8f32:569; CHECK: # %bb.0:570; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma571; CHECK-NEXT: vfsqrt.v v8, v8, v0.t572; CHECK-NEXT: ret573 %v = call <vscale x 8 x float> @llvm.vp.sqrt.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 %evl)574 ret <vscale x 8 x float> %v575}576 577define <vscale x 8 x float> @vfsqrt_vv_nxv8f32_unmasked(<vscale x 8 x float> %va, i32 zeroext %evl) {578; CHECK-LABEL: vfsqrt_vv_nxv8f32_unmasked:579; CHECK: # %bb.0:580; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma581; CHECK-NEXT: vfsqrt.v v8, v8582; CHECK-NEXT: ret583 %v = call <vscale x 8 x float> @llvm.vp.sqrt.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)584 ret <vscale x 8 x float> %v585}586 587define <vscale x 16 x float> @vfsqrt_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {588; CHECK-LABEL: vfsqrt_vv_nxv16f32:589; CHECK: # %bb.0:590; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma591; CHECK-NEXT: vfsqrt.v v8, v8, v0.t592; CHECK-NEXT: ret593 %v = call <vscale x 16 x float> @llvm.vp.sqrt.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 %evl)594 ret <vscale x 16 x float> %v595}596 597define <vscale x 16 x float> @vfsqrt_vv_nxv16f32_unmasked(<vscale x 16 x float> %va, i32 zeroext %evl) {598; CHECK-LABEL: vfsqrt_vv_nxv16f32_unmasked:599; CHECK: # %bb.0:600; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma601; CHECK-NEXT: vfsqrt.v v8, v8602; CHECK-NEXT: ret603 %v = call <vscale x 16 x float> @llvm.vp.sqrt.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)604 ret <vscale x 16 x float> %v605}606 607define <vscale x 1 x double> @vfsqrt_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {608; CHECK-LABEL: vfsqrt_vv_nxv1f64:609; CHECK: # %bb.0:610; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma611; CHECK-NEXT: vfsqrt.v v8, v8, v0.t612; CHECK-NEXT: ret613 %v = call <vscale x 1 x double> @llvm.vp.sqrt.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 %evl)614 ret <vscale x 1 x double> %v615}616 617define <vscale x 1 x double> @vfsqrt_vv_nxv1f64_unmasked(<vscale x 1 x double> %va, i32 zeroext %evl) {618; CHECK-LABEL: vfsqrt_vv_nxv1f64_unmasked:619; CHECK: # %bb.0:620; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma621; CHECK-NEXT: vfsqrt.v v8, v8622; CHECK-NEXT: ret623 %v = call <vscale x 1 x double> @llvm.vp.sqrt.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)624 ret <vscale x 1 x double> %v625}626 627define <vscale x 2 x double> @vfsqrt_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {628; CHECK-LABEL: vfsqrt_vv_nxv2f64:629; CHECK: # %bb.0:630; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma631; CHECK-NEXT: vfsqrt.v v8, v8, v0.t632; CHECK-NEXT: ret633 %v = call <vscale x 2 x double> @llvm.vp.sqrt.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)634 ret <vscale x 2 x double> %v635}636 637define <vscale x 2 x double> @vfsqrt_vv_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {638; CHECK-LABEL: vfsqrt_vv_nxv2f64_unmasked:639; CHECK: # %bb.0:640; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma641; CHECK-NEXT: vfsqrt.v v8, v8642; CHECK-NEXT: ret643 %v = call <vscale x 2 x double> @llvm.vp.sqrt.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)644 ret <vscale x 2 x double> %v645}646 647define <vscale x 4 x double> @vfsqrt_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {648; CHECK-LABEL: vfsqrt_vv_nxv4f64:649; CHECK: # %bb.0:650; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma651; CHECK-NEXT: vfsqrt.v v8, v8, v0.t652; CHECK-NEXT: ret653 %v = call <vscale x 4 x double> @llvm.vp.sqrt.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 %evl)654 ret <vscale x 4 x double> %v655}656 657define <vscale x 4 x double> @vfsqrt_vv_nxv4f64_unmasked(<vscale x 4 x double> %va, i32 zeroext %evl) {658; CHECK-LABEL: vfsqrt_vv_nxv4f64_unmasked:659; CHECK: # %bb.0:660; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma661; CHECK-NEXT: vfsqrt.v v8, v8662; CHECK-NEXT: ret663 %v = call <vscale x 4 x double> @llvm.vp.sqrt.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)664 ret <vscale x 4 x double> %v665}666 667define <vscale x 7 x double> @vfsqrt_vv_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {668; CHECK-LABEL: vfsqrt_vv_nxv7f64:669; CHECK: # %bb.0:670; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma671; CHECK-NEXT: vfsqrt.v v8, v8, v0.t672; CHECK-NEXT: ret673 %v = call <vscale x 7 x double> @llvm.vp.sqrt.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)674 ret <vscale x 7 x double> %v675}676 677define <vscale x 7 x double> @vfsqrt_vv_nxv7f64_unmasked(<vscale x 7 x double> %va, i32 zeroext %evl) {678; CHECK-LABEL: vfsqrt_vv_nxv7f64_unmasked:679; CHECK: # %bb.0:680; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma681; CHECK-NEXT: vfsqrt.v v8, v8682; CHECK-NEXT: ret683 %v = call <vscale x 7 x double> @llvm.vp.sqrt.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)684 ret <vscale x 7 x double> %v685}686 687define <vscale x 8 x double> @vfsqrt_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {688; CHECK-LABEL: vfsqrt_vv_nxv8f64:689; CHECK: # %bb.0:690; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma691; CHECK-NEXT: vfsqrt.v v8, v8, v0.t692; CHECK-NEXT: ret693 %v = call <vscale x 8 x double> @llvm.vp.sqrt.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 %evl)694 ret <vscale x 8 x double> %v695}696 697define <vscale x 8 x double> @vfsqrt_vv_nxv8f64_unmasked(<vscale x 8 x double> %va, i32 zeroext %evl) {698; CHECK-LABEL: vfsqrt_vv_nxv8f64_unmasked:699; CHECK: # %bb.0:700; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma701; CHECK-NEXT: vfsqrt.v v8, v8702; CHECK-NEXT: ret703 %v = call <vscale x 8 x double> @llvm.vp.sqrt.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)704 ret <vscale x 8 x double> %v705}706 707; Test splitting.708 709define <vscale x 16 x double> @vfsqrt_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {710; CHECK-LABEL: vfsqrt_vv_nxv16f64:711; CHECK: # %bb.0:712; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma713; CHECK-NEXT: vmv1r.v v24, v0714; CHECK-NEXT: csrr a1, vlenb715; CHECK-NEXT: srli a2, a1, 3716; CHECK-NEXT: sub a3, a0, a1717; CHECK-NEXT: vslidedown.vx v0, v0, a2718; CHECK-NEXT: sltu a2, a0, a3719; CHECK-NEXT: addi a2, a2, -1720; CHECK-NEXT: and a2, a2, a3721; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma722; CHECK-NEXT: vfsqrt.v v16, v16, v0.t723; CHECK-NEXT: bltu a0, a1, .LBB44_2724; CHECK-NEXT: # %bb.1:725; CHECK-NEXT: mv a0, a1726; CHECK-NEXT: .LBB44_2:727; CHECK-NEXT: vmv1r.v v0, v24728; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma729; CHECK-NEXT: vfsqrt.v v8, v8, v0.t730; CHECK-NEXT: ret731 %v = call <vscale x 16 x double> @llvm.vp.sqrt.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)732 ret <vscale x 16 x double> %v733}734 735define <vscale x 16 x double> @vfsqrt_vv_nxv16f64_unmasked(<vscale x 16 x double> %va, i32 zeroext %evl) {736; CHECK-LABEL: vfsqrt_vv_nxv16f64_unmasked:737; CHECK: # %bb.0:738; CHECK-NEXT: csrr a1, vlenb739; CHECK-NEXT: sub a2, a0, a1740; CHECK-NEXT: sltu a3, a0, a2741; CHECK-NEXT: addi a3, a3, -1742; CHECK-NEXT: and a2, a3, a2743; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma744; CHECK-NEXT: vfsqrt.v v16, v16745; CHECK-NEXT: bltu a0, a1, .LBB45_2746; CHECK-NEXT: # %bb.1:747; CHECK-NEXT: mv a0, a1748; CHECK-NEXT: .LBB45_2:749; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma750; CHECK-NEXT: vfsqrt.v v8, v8751; CHECK-NEXT: ret752 %v = call <vscale x 16 x double> @llvm.vp.sqrt.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)753 ret <vscale x 16 x double> %v754}755