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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x half> @intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vfsub.vv v8, v8, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16(15 <vscale x 1 x half> poison,16 <vscale x 1 x half> %0,17 <vscale x 1 x half> %1,18 iXLen 7, iXLen %2)19 20 ret <vscale x 1 x half> %a21}22 23define <vscale x 1 x half> @intrinsic_vfsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f16_nxv1f16_nxv1f16:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu27; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x half> @llvm.riscv.vfsub.mask.nxv1f16.nxv1f16(31 <vscale x 1 x half> %0,32 <vscale x 1 x half> %1,33 <vscale x 1 x half> %2,34 <vscale x 1 x i1> %3,35 iXLen 7, iXLen %4, iXLen 1)36 37 ret <vscale x 1 x half> %a38}39 40define <vscale x 2 x half> @intrinsic_vfsub_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f16_nxv2f16_nxv2f16:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma44; CHECK-NEXT: vfsub.vv v8, v8, v945; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.nxv2f16(48 <vscale x 2 x half> poison,49 <vscale x 2 x half> %0,50 <vscale x 2 x half> %1,51 iXLen 7, iXLen %2)52 53 ret <vscale x 2 x half> %a54}55 56define <vscale x 2 x half> @intrinsic_vfsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f16_nxv2f16_nxv2f16:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu60; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x half> @llvm.riscv.vfsub.mask.nxv2f16.nxv2f16(64 <vscale x 2 x half> %0,65 <vscale x 2 x half> %1,66 <vscale x 2 x half> %2,67 <vscale x 2 x i1> %3,68 iXLen 7, iXLen %4, iXLen 1)69 70 ret <vscale x 2 x half> %a71}72 73define <vscale x 4 x half> @intrinsic_vfsub_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f16_nxv4f16_nxv4f16:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma77; CHECK-NEXT: vfsub.vv v8, v8, v978; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.nxv4f16(81 <vscale x 4 x half> poison,82 <vscale x 4 x half> %0,83 <vscale x 4 x half> %1,84 iXLen 7, iXLen %2)85 86 ret <vscale x 4 x half> %a87}88 89define <vscale x 4 x half> @intrinsic_vfsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f16_nxv4f16_nxv4f16:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu93; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x half> @llvm.riscv.vfsub.mask.nxv4f16.nxv4f16(97 <vscale x 4 x half> %0,98 <vscale x 4 x half> %1,99 <vscale x 4 x half> %2,100 <vscale x 4 x i1> %3,101 iXLen 7, iXLen %4, iXLen 1)102 103 ret <vscale x 4 x half> %a104}105 106define <vscale x 8 x half> @intrinsic_vfsub_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f16_nxv8f16_nxv8f16:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma110; CHECK-NEXT: vfsub.vv v8, v8, v10111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.nxv8f16(114 <vscale x 8 x half> poison,115 <vscale x 8 x half> %0,116 <vscale x 8 x half> %1,117 iXLen 7, iXLen %2)118 119 ret <vscale x 8 x half> %a120}121 122define <vscale x 8 x half> @intrinsic_vfsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f16_nxv8f16_nxv8f16:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu126; CHECK-NEXT: vfsub.vv v8, v10, v12, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x half> @llvm.riscv.vfsub.mask.nxv8f16.nxv8f16(130 <vscale x 8 x half> %0,131 <vscale x 8 x half> %1,132 <vscale x 8 x half> %2,133 <vscale x 8 x i1> %3,134 iXLen 7, iXLen %4, iXLen 1)135 136 ret <vscale x 8 x half> %a137}138 139define <vscale x 16 x half> @intrinsic_vfsub_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vfsub_vv_nxv16f16_nxv16f16_nxv16f16:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma143; CHECK-NEXT: vfsub.vv v8, v8, v12144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.nxv16f16(147 <vscale x 16 x half> poison,148 <vscale x 16 x half> %0,149 <vscale x 16 x half> %1,150 iXLen 7, iXLen %2)151 152 ret <vscale x 16 x half> %a153}154 155define <vscale x 16 x half> @intrinsic_vfsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f16_nxv16f16_nxv16f16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu159; CHECK-NEXT: vfsub.vv v8, v12, v16, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x half> @llvm.riscv.vfsub.mask.nxv16f16.nxv16f16(163 <vscale x 16 x half> %0,164 <vscale x 16 x half> %1,165 <vscale x 16 x half> %2,166 <vscale x 16 x i1> %3,167 iXLen 7, iXLen %4, iXLen 1)168 169 ret <vscale x 16 x half> %a170}171 172define <vscale x 32 x half> @intrinsic_vfsub_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vfsub_vv_nxv32f16_nxv32f16_nxv32f16:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma176; CHECK-NEXT: vfsub.vv v8, v8, v16177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 32 x half> @llvm.riscv.vfsub.nxv32f16.nxv32f16(180 <vscale x 32 x half> poison,181 <vscale x 32 x half> %0,182 <vscale x 32 x half> %1,183 iXLen 7, iXLen %2)184 185 ret <vscale x 32 x half> %a186}187 188define <vscale x 32 x half> @intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vl8re16.v v24, (a0)192; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu193; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t194; CHECK-NEXT: ret195entry:196 %a = call <vscale x 32 x half> @llvm.riscv.vfsub.mask.nxv32f16.nxv32f16(197 <vscale x 32 x half> %0,198 <vscale x 32 x half> %1,199 <vscale x 32 x half> %2,200 <vscale x 32 x i1> %3,201 iXLen 7, iXLen %4, iXLen 1)202 203 ret <vscale x 32 x half> %a204}205 206define <vscale x 1 x float> @intrinsic_vfsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {207; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f32_nxv1f32_nxv1f32:208; CHECK: # %bb.0: # %entry209; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma210; CHECK-NEXT: vfsub.vv v8, v8, v9211; CHECK-NEXT: ret212entry:213 %a = call <vscale x 1 x float> @llvm.riscv.vfsub.nxv1f32.nxv1f32(214 <vscale x 1 x float> poison,215 <vscale x 1 x float> %0,216 <vscale x 1 x float> %1,217 iXLen 7, iXLen %2)218 219 ret <vscale x 1 x float> %a220}221 222define <vscale x 1 x float> @intrinsic_vfsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {223; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f32_nxv1f32_nxv1f32:224; CHECK: # %bb.0: # %entry225; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu226; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t227; CHECK-NEXT: ret228entry:229 %a = call <vscale x 1 x float> @llvm.riscv.vfsub.mask.nxv1f32.nxv1f32(230 <vscale x 1 x float> %0,231 <vscale x 1 x float> %1,232 <vscale x 1 x float> %2,233 <vscale x 1 x i1> %3,234 iXLen 7, iXLen %4, iXLen 1)235 236 ret <vscale x 1 x float> %a237}238 239define <vscale x 2 x float> @intrinsic_vfsub_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {240; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f32_nxv2f32_nxv2f32:241; CHECK: # %bb.0: # %entry242; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma243; CHECK-NEXT: vfsub.vv v8, v8, v9244; CHECK-NEXT: ret245entry:246 %a = call <vscale x 2 x float> @llvm.riscv.vfsub.nxv2f32.nxv2f32(247 <vscale x 2 x float> poison,248 <vscale x 2 x float> %0,249 <vscale x 2 x float> %1,250 iXLen 7, iXLen %2)251 252 ret <vscale x 2 x float> %a253}254 255define <vscale x 2 x float> @intrinsic_vfsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {256; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f32_nxv2f32_nxv2f32:257; CHECK: # %bb.0: # %entry258; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu259; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t260; CHECK-NEXT: ret261entry:262 %a = call <vscale x 2 x float> @llvm.riscv.vfsub.mask.nxv2f32.nxv2f32(263 <vscale x 2 x float> %0,264 <vscale x 2 x float> %1,265 <vscale x 2 x float> %2,266 <vscale x 2 x i1> %3,267 iXLen 7, iXLen %4, iXLen 1)268 269 ret <vscale x 2 x float> %a270}271 272define <vscale x 4 x float> @intrinsic_vfsub_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {273; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f32_nxv4f32_nxv4f32:274; CHECK: # %bb.0: # %entry275; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma276; CHECK-NEXT: vfsub.vv v8, v8, v10277; CHECK-NEXT: ret278entry:279 %a = call <vscale x 4 x float> @llvm.riscv.vfsub.nxv4f32.nxv4f32(280 <vscale x 4 x float> poison,281 <vscale x 4 x float> %0,282 <vscale x 4 x float> %1,283 iXLen 7, iXLen %2)284 285 ret <vscale x 4 x float> %a286}287 288define <vscale x 4 x float> @intrinsic_vfsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {289; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f32_nxv4f32_nxv4f32:290; CHECK: # %bb.0: # %entry291; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu292; CHECK-NEXT: vfsub.vv v8, v10, v12, v0.t293; CHECK-NEXT: ret294entry:295 %a = call <vscale x 4 x float> @llvm.riscv.vfsub.mask.nxv4f32.nxv4f32(296 <vscale x 4 x float> %0,297 <vscale x 4 x float> %1,298 <vscale x 4 x float> %2,299 <vscale x 4 x i1> %3,300 iXLen 7, iXLen %4, iXLen 1)301 302 ret <vscale x 4 x float> %a303}304 305define <vscale x 8 x float> @intrinsic_vfsub_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {306; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f32_nxv8f32_nxv8f32:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma309; CHECK-NEXT: vfsub.vv v8, v8, v12310; CHECK-NEXT: ret311entry:312 %a = call <vscale x 8 x float> @llvm.riscv.vfsub.nxv8f32.nxv8f32(313 <vscale x 8 x float> poison,314 <vscale x 8 x float> %0,315 <vscale x 8 x float> %1,316 iXLen 7, iXLen %2)317 318 ret <vscale x 8 x float> %a319}320 321define <vscale x 8 x float> @intrinsic_vfsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {322; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f32_nxv8f32_nxv8f32:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu325; CHECK-NEXT: vfsub.vv v8, v12, v16, v0.t326; CHECK-NEXT: ret327entry:328 %a = call <vscale x 8 x float> @llvm.riscv.vfsub.mask.nxv8f32.nxv8f32(329 <vscale x 8 x float> %0,330 <vscale x 8 x float> %1,331 <vscale x 8 x float> %2,332 <vscale x 8 x i1> %3,333 iXLen 7, iXLen %4, iXLen 1)334 335 ret <vscale x 8 x float> %a336}337 338define <vscale x 16 x float> @intrinsic_vfsub_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, iXLen %2) nounwind {339; CHECK-LABEL: intrinsic_vfsub_vv_nxv16f32_nxv16f32_nxv16f32:340; CHECK: # %bb.0: # %entry341; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma342; CHECK-NEXT: vfsub.vv v8, v8, v16343; CHECK-NEXT: ret344entry:345 %a = call <vscale x 16 x float> @llvm.riscv.vfsub.nxv16f32.nxv16f32(346 <vscale x 16 x float> poison,347 <vscale x 16 x float> %0,348 <vscale x 16 x float> %1,349 iXLen 7, iXLen %2)350 351 ret <vscale x 16 x float> %a352}353 354define <vscale x 16 x float> @intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {355; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32:356; CHECK: # %bb.0: # %entry357; CHECK-NEXT: vl8re32.v v24, (a0)358; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu359; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t360; CHECK-NEXT: ret361entry:362 %a = call <vscale x 16 x float> @llvm.riscv.vfsub.mask.nxv16f32.nxv16f32(363 <vscale x 16 x float> %0,364 <vscale x 16 x float> %1,365 <vscale x 16 x float> %2,366 <vscale x 16 x i1> %3,367 iXLen 7, iXLen %4, iXLen 1)368 369 ret <vscale x 16 x float> %a370}371 372define <vscale x 1 x double> @intrinsic_vfsub_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {373; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f64_nxv1f64_nxv1f64:374; CHECK: # %bb.0: # %entry375; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma376; CHECK-NEXT: vfsub.vv v8, v8, v9377; CHECK-NEXT: ret378entry:379 %a = call <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(380 <vscale x 1 x double> poison,381 <vscale x 1 x double> %0,382 <vscale x 1 x double> %1,383 iXLen 7, iXLen %2)384 385 ret <vscale x 1 x double> %a386}387 388define <vscale x 1 x double> @intrinsic_vfsub_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {389; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f64_nxv1f64_nxv1f64:390; CHECK: # %bb.0: # %entry391; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu392; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t393; CHECK-NEXT: ret394entry:395 %a = call <vscale x 1 x double> @llvm.riscv.vfsub.mask.nxv1f64.nxv1f64(396 <vscale x 1 x double> %0,397 <vscale x 1 x double> %1,398 <vscale x 1 x double> %2,399 <vscale x 1 x i1> %3,400 iXLen 7, iXLen %4, iXLen 1)401 402 ret <vscale x 1 x double> %a403}404 405define <vscale x 2 x double> @intrinsic_vfsub_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {406; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f64_nxv2f64_nxv2f64:407; CHECK: # %bb.0: # %entry408; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma409; CHECK-NEXT: vfsub.vv v8, v8, v10410; CHECK-NEXT: ret411entry:412 %a = call <vscale x 2 x double> @llvm.riscv.vfsub.nxv2f64.nxv2f64(413 <vscale x 2 x double> poison,414 <vscale x 2 x double> %0,415 <vscale x 2 x double> %1,416 iXLen 7, iXLen %2)417 418 ret <vscale x 2 x double> %a419}420 421define <vscale x 2 x double> @intrinsic_vfsub_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {422; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f64_nxv2f64_nxv2f64:423; CHECK: # %bb.0: # %entry424; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu425; CHECK-NEXT: vfsub.vv v8, v10, v12, v0.t426; CHECK-NEXT: ret427entry:428 %a = call <vscale x 2 x double> @llvm.riscv.vfsub.mask.nxv2f64.nxv2f64(429 <vscale x 2 x double> %0,430 <vscale x 2 x double> %1,431 <vscale x 2 x double> %2,432 <vscale x 2 x i1> %3,433 iXLen 7, iXLen %4, iXLen 1)434 435 ret <vscale x 2 x double> %a436}437 438define <vscale x 4 x double> @intrinsic_vfsub_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {439; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f64_nxv4f64_nxv4f64:440; CHECK: # %bb.0: # %entry441; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma442; CHECK-NEXT: vfsub.vv v8, v8, v12443; CHECK-NEXT: ret444entry:445 %a = call <vscale x 4 x double> @llvm.riscv.vfsub.nxv4f64.nxv4f64(446 <vscale x 4 x double> poison,447 <vscale x 4 x double> %0,448 <vscale x 4 x double> %1,449 iXLen 7, iXLen %2)450 451 ret <vscale x 4 x double> %a452}453 454define <vscale x 4 x double> @intrinsic_vfsub_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {455; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f64_nxv4f64_nxv4f64:456; CHECK: # %bb.0: # %entry457; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu458; CHECK-NEXT: vfsub.vv v8, v12, v16, v0.t459; CHECK-NEXT: ret460entry:461 %a = call <vscale x 4 x double> @llvm.riscv.vfsub.mask.nxv4f64.nxv4f64(462 <vscale x 4 x double> %0,463 <vscale x 4 x double> %1,464 <vscale x 4 x double> %2,465 <vscale x 4 x i1> %3,466 iXLen 7, iXLen %4, iXLen 1)467 468 ret <vscale x 4 x double> %a469}470 471define <vscale x 8 x double> @intrinsic_vfsub_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, iXLen %2) nounwind {472; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f64_nxv8f64_nxv8f64:473; CHECK: # %bb.0: # %entry474; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma475; CHECK-NEXT: vfsub.vv v8, v8, v16476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 8 x double> @llvm.riscv.vfsub.nxv8f64.nxv8f64(479 <vscale x 8 x double> poison,480 <vscale x 8 x double> %0,481 <vscale x 8 x double> %1,482 iXLen 7, iXLen %2)483 484 ret <vscale x 8 x double> %a485}486 487define <vscale x 8 x double> @intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {488; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64:489; CHECK: # %bb.0: # %entry490; CHECK-NEXT: vl8re64.v v24, (a0)491; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu492; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t493; CHECK-NEXT: ret494entry:495 %a = call <vscale x 8 x double> @llvm.riscv.vfsub.mask.nxv8f64.nxv8f64(496 <vscale x 8 x double> %0,497 <vscale x 8 x double> %1,498 <vscale x 8 x double> %2,499 <vscale x 8 x i1> %3,500 iXLen 7, iXLen %4, iXLen 1)501 502 ret <vscale x 8 x double> %a503}504 505define <vscale x 1 x half> @intrinsic_vfsub_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {506; CHECK-LABEL: intrinsic_vfsub_vf_nxv1f16_nxv1f16_f16:507; CHECK: # %bb.0: # %entry508; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma509; CHECK-NEXT: vfsub.vf v8, v8, fa0510; CHECK-NEXT: ret511entry:512 %a = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.f16(513 <vscale x 1 x half> poison,514 <vscale x 1 x half> %0,515 half %1,516 iXLen 7, iXLen %2)517 518 ret <vscale x 1 x half> %a519}520 521define <vscale x 1 x half> @intrinsic_vfsub_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {522; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv1f16_nxv1f16_f16:523; CHECK: # %bb.0: # %entry524; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu525; CHECK-NEXT: vfsub.vf v8, v9, fa0, v0.t526; CHECK-NEXT: ret527entry:528 %a = call <vscale x 1 x half> @llvm.riscv.vfsub.mask.nxv1f16.f16(529 <vscale x 1 x half> %0,530 <vscale x 1 x half> %1,531 half %2,532 <vscale x 1 x i1> %3,533 iXLen 7, iXLen %4, iXLen 1)534 535 ret <vscale x 1 x half> %a536}537 538define <vscale x 2 x half> @intrinsic_vfsub_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {539; CHECK-LABEL: intrinsic_vfsub_vf_nxv2f16_nxv2f16_f16:540; CHECK: # %bb.0: # %entry541; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma542; CHECK-NEXT: vfsub.vf v8, v8, fa0543; CHECK-NEXT: ret544entry:545 %a = call <vscale x 2 x half> @llvm.riscv.vfsub.nxv2f16.f16(546 <vscale x 2 x half> poison,547 <vscale x 2 x half> %0,548 half %1,549 iXLen 7, iXLen %2)550 551 ret <vscale x 2 x half> %a552}553 554define <vscale x 2 x half> @intrinsic_vfsub_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {555; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv2f16_nxv2f16_f16:556; CHECK: # %bb.0: # %entry557; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu558; CHECK-NEXT: vfsub.vf v8, v9, fa0, v0.t559; CHECK-NEXT: ret560entry:561 %a = call <vscale x 2 x half> @llvm.riscv.vfsub.mask.nxv2f16.f16(562 <vscale x 2 x half> %0,563 <vscale x 2 x half> %1,564 half %2,565 <vscale x 2 x i1> %3,566 iXLen 7, iXLen %4, iXLen 1)567 568 ret <vscale x 2 x half> %a569}570 571define <vscale x 4 x half> @intrinsic_vfsub_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {572; CHECK-LABEL: intrinsic_vfsub_vf_nxv4f16_nxv4f16_f16:573; CHECK: # %bb.0: # %entry574; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma575; CHECK-NEXT: vfsub.vf v8, v8, fa0576; CHECK-NEXT: ret577entry:578 %a = call <vscale x 4 x half> @llvm.riscv.vfsub.nxv4f16.f16(579 <vscale x 4 x half> poison,580 <vscale x 4 x half> %0,581 half %1,582 iXLen 7, iXLen %2)583 584 ret <vscale x 4 x half> %a585}586 587define <vscale x 4 x half> @intrinsic_vfsub_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {588; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv4f16_nxv4f16_f16:589; CHECK: # %bb.0: # %entry590; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu591; CHECK-NEXT: vfsub.vf v8, v9, fa0, v0.t592; CHECK-NEXT: ret593entry:594 %a = call <vscale x 4 x half> @llvm.riscv.vfsub.mask.nxv4f16.f16(595 <vscale x 4 x half> %0,596 <vscale x 4 x half> %1,597 half %2,598 <vscale x 4 x i1> %3,599 iXLen 7, iXLen %4, iXLen 1)600 601 ret <vscale x 4 x half> %a602}603 604define <vscale x 8 x half> @intrinsic_vfsub_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {605; CHECK-LABEL: intrinsic_vfsub_vf_nxv8f16_nxv8f16_f16:606; CHECK: # %bb.0: # %entry607; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma608; CHECK-NEXT: vfsub.vf v8, v8, fa0609; CHECK-NEXT: ret610entry:611 %a = call <vscale x 8 x half> @llvm.riscv.vfsub.nxv8f16.f16(612 <vscale x 8 x half> poison,613 <vscale x 8 x half> %0,614 half %1,615 iXLen 7, iXLen %2)616 617 ret <vscale x 8 x half> %a618}619 620define <vscale x 8 x half> @intrinsic_vfsub_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {621; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv8f16_nxv8f16_f16:622; CHECK: # %bb.0: # %entry623; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu624; CHECK-NEXT: vfsub.vf v8, v10, fa0, v0.t625; CHECK-NEXT: ret626entry:627 %a = call <vscale x 8 x half> @llvm.riscv.vfsub.mask.nxv8f16.f16(628 <vscale x 8 x half> %0,629 <vscale x 8 x half> %1,630 half %2,631 <vscale x 8 x i1> %3,632 iXLen 7, iXLen %4, iXLen 1)633 634 ret <vscale x 8 x half> %a635}636 637define <vscale x 16 x half> @intrinsic_vfsub_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {638; CHECK-LABEL: intrinsic_vfsub_vf_nxv16f16_nxv16f16_f16:639; CHECK: # %bb.0: # %entry640; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma641; CHECK-NEXT: vfsub.vf v8, v8, fa0642; CHECK-NEXT: ret643entry:644 %a = call <vscale x 16 x half> @llvm.riscv.vfsub.nxv16f16.f16(645 <vscale x 16 x half> poison,646 <vscale x 16 x half> %0,647 half %1,648 iXLen 7, iXLen %2)649 650 ret <vscale x 16 x half> %a651}652 653define <vscale x 16 x half> @intrinsic_vfsub_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {654; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv16f16_nxv16f16_f16:655; CHECK: # %bb.0: # %entry656; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu657; CHECK-NEXT: vfsub.vf v8, v12, fa0, v0.t658; CHECK-NEXT: ret659entry:660 %a = call <vscale x 16 x half> @llvm.riscv.vfsub.mask.nxv16f16.f16(661 <vscale x 16 x half> %0,662 <vscale x 16 x half> %1,663 half %2,664 <vscale x 16 x i1> %3,665 iXLen 7, iXLen %4, iXLen 1)666 667 ret <vscale x 16 x half> %a668}669 670define <vscale x 32 x half> @intrinsic_vfsub_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, iXLen %2) nounwind {671; CHECK-LABEL: intrinsic_vfsub_vf_nxv32f16_nxv32f16_f16:672; CHECK: # %bb.0: # %entry673; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma674; CHECK-NEXT: vfsub.vf v8, v8, fa0675; CHECK-NEXT: ret676entry:677 %a = call <vscale x 32 x half> @llvm.riscv.vfsub.nxv32f16.f16(678 <vscale x 32 x half> poison,679 <vscale x 32 x half> %0,680 half %1,681 iXLen 7, iXLen %2)682 683 ret <vscale x 32 x half> %a684}685 686define <vscale x 32 x half> @intrinsic_vfsub_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {687; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv32f16_nxv32f16_f16:688; CHECK: # %bb.0: # %entry689; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu690; CHECK-NEXT: vfsub.vf v8, v16, fa0, v0.t691; CHECK-NEXT: ret692entry:693 %a = call <vscale x 32 x half> @llvm.riscv.vfsub.mask.nxv32f16.f16(694 <vscale x 32 x half> %0,695 <vscale x 32 x half> %1,696 half %2,697 <vscale x 32 x i1> %3,698 iXLen 7, iXLen %4, iXLen 1)699 700 ret <vscale x 32 x half> %a701}702 703define <vscale x 1 x float> @intrinsic_vfsub_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {704; CHECK-LABEL: intrinsic_vfsub_vf_nxv1f32_nxv1f32_f32:705; CHECK: # %bb.0: # %entry706; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma707; CHECK-NEXT: vfsub.vf v8, v8, fa0708; CHECK-NEXT: ret709entry:710 %a = call <vscale x 1 x float> @llvm.riscv.vfsub.nxv1f32.f32(711 <vscale x 1 x float> poison,712 <vscale x 1 x float> %0,713 float %1,714 iXLen 7, iXLen %2)715 716 ret <vscale x 1 x float> %a717}718 719define <vscale x 1 x float> @intrinsic_vfsub_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {720; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv1f32_nxv1f32_f32:721; CHECK: # %bb.0: # %entry722; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu723; CHECK-NEXT: vfsub.vf v8, v9, fa0, v0.t724; CHECK-NEXT: ret725entry:726 %a = call <vscale x 1 x float> @llvm.riscv.vfsub.mask.nxv1f32.f32(727 <vscale x 1 x float> %0,728 <vscale x 1 x float> %1,729 float %2,730 <vscale x 1 x i1> %3,731 iXLen 7, iXLen %4, iXLen 1)732 733 ret <vscale x 1 x float> %a734}735 736define <vscale x 2 x float> @intrinsic_vfsub_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {737; CHECK-LABEL: intrinsic_vfsub_vf_nxv2f32_nxv2f32_f32:738; CHECK: # %bb.0: # %entry739; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma740; CHECK-NEXT: vfsub.vf v8, v8, fa0741; CHECK-NEXT: ret742entry:743 %a = call <vscale x 2 x float> @llvm.riscv.vfsub.nxv2f32.f32(744 <vscale x 2 x float> poison,745 <vscale x 2 x float> %0,746 float %1,747 iXLen 7, iXLen %2)748 749 ret <vscale x 2 x float> %a750}751 752define <vscale x 2 x float> @intrinsic_vfsub_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {753; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv2f32_nxv2f32_f32:754; CHECK: # %bb.0: # %entry755; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu756; CHECK-NEXT: vfsub.vf v8, v9, fa0, v0.t757; CHECK-NEXT: ret758entry:759 %a = call <vscale x 2 x float> @llvm.riscv.vfsub.mask.nxv2f32.f32(760 <vscale x 2 x float> %0,761 <vscale x 2 x float> %1,762 float %2,763 <vscale x 2 x i1> %3,764 iXLen 7, iXLen %4, iXLen 1)765 766 ret <vscale x 2 x float> %a767}768 769define <vscale x 4 x float> @intrinsic_vfsub_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {770; CHECK-LABEL: intrinsic_vfsub_vf_nxv4f32_nxv4f32_f32:771; CHECK: # %bb.0: # %entry772; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma773; CHECK-NEXT: vfsub.vf v8, v8, fa0774; CHECK-NEXT: ret775entry:776 %a = call <vscale x 4 x float> @llvm.riscv.vfsub.nxv4f32.f32(777 <vscale x 4 x float> poison,778 <vscale x 4 x float> %0,779 float %1,780 iXLen 7, iXLen %2)781 782 ret <vscale x 4 x float> %a783}784 785define <vscale x 4 x float> @intrinsic_vfsub_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {786; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv4f32_nxv4f32_f32:787; CHECK: # %bb.0: # %entry788; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu789; CHECK-NEXT: vfsub.vf v8, v10, fa0, v0.t790; CHECK-NEXT: ret791entry:792 %a = call <vscale x 4 x float> @llvm.riscv.vfsub.mask.nxv4f32.f32(793 <vscale x 4 x float> %0,794 <vscale x 4 x float> %1,795 float %2,796 <vscale x 4 x i1> %3,797 iXLen 7, iXLen %4, iXLen 1)798 799 ret <vscale x 4 x float> %a800}801 802define <vscale x 8 x float> @intrinsic_vfsub_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {803; CHECK-LABEL: intrinsic_vfsub_vf_nxv8f32_nxv8f32_f32:804; CHECK: # %bb.0: # %entry805; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma806; CHECK-NEXT: vfsub.vf v8, v8, fa0807; CHECK-NEXT: ret808entry:809 %a = call <vscale x 8 x float> @llvm.riscv.vfsub.nxv8f32.f32(810 <vscale x 8 x float> poison,811 <vscale x 8 x float> %0,812 float %1,813 iXLen 7, iXLen %2)814 815 ret <vscale x 8 x float> %a816}817 818define <vscale x 8 x float> @intrinsic_vfsub_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {819; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv8f32_nxv8f32_f32:820; CHECK: # %bb.0: # %entry821; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu822; CHECK-NEXT: vfsub.vf v8, v12, fa0, v0.t823; CHECK-NEXT: ret824entry:825 %a = call <vscale x 8 x float> @llvm.riscv.vfsub.mask.nxv8f32.f32(826 <vscale x 8 x float> %0,827 <vscale x 8 x float> %1,828 float %2,829 <vscale x 8 x i1> %3,830 iXLen 7, iXLen %4, iXLen 1)831 832 ret <vscale x 8 x float> %a833}834 835define <vscale x 16 x float> @intrinsic_vfsub_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, iXLen %2) nounwind {836; CHECK-LABEL: intrinsic_vfsub_vf_nxv16f32_nxv16f32_f32:837; CHECK: # %bb.0: # %entry838; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma839; CHECK-NEXT: vfsub.vf v8, v8, fa0840; CHECK-NEXT: ret841entry:842 %a = call <vscale x 16 x float> @llvm.riscv.vfsub.nxv16f32.f32(843 <vscale x 16 x float> poison,844 <vscale x 16 x float> %0,845 float %1,846 iXLen 7, iXLen %2)847 848 ret <vscale x 16 x float> %a849}850 851define <vscale x 16 x float> @intrinsic_vfsub_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {852; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv16f32_nxv16f32_f32:853; CHECK: # %bb.0: # %entry854; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu855; CHECK-NEXT: vfsub.vf v8, v16, fa0, v0.t856; CHECK-NEXT: ret857entry:858 %a = call <vscale x 16 x float> @llvm.riscv.vfsub.mask.nxv16f32.f32(859 <vscale x 16 x float> %0,860 <vscale x 16 x float> %1,861 float %2,862 <vscale x 16 x i1> %3,863 iXLen 7, iXLen %4, iXLen 1)864 865 ret <vscale x 16 x float> %a866}867 868define <vscale x 1 x double> @intrinsic_vfsub_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {869; CHECK-LABEL: intrinsic_vfsub_vf_nxv1f64_nxv1f64_f64:870; CHECK: # %bb.0: # %entry871; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma872; CHECK-NEXT: vfsub.vf v8, v8, fa0873; CHECK-NEXT: ret874entry:875 %a = call <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.f64(876 <vscale x 1 x double> poison,877 <vscale x 1 x double> %0,878 double %1,879 iXLen 7, iXLen %2)880 881 ret <vscale x 1 x double> %a882}883 884define <vscale x 1 x double> @intrinsic_vfsub_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {885; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv1f64_nxv1f64_f64:886; CHECK: # %bb.0: # %entry887; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu888; CHECK-NEXT: vfsub.vf v8, v9, fa0, v0.t889; CHECK-NEXT: ret890entry:891 %a = call <vscale x 1 x double> @llvm.riscv.vfsub.mask.nxv1f64.f64(892 <vscale x 1 x double> %0,893 <vscale x 1 x double> %1,894 double %2,895 <vscale x 1 x i1> %3,896 iXLen 7, iXLen %4, iXLen 1)897 898 ret <vscale x 1 x double> %a899}900 901define <vscale x 2 x double> @intrinsic_vfsub_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {902; CHECK-LABEL: intrinsic_vfsub_vf_nxv2f64_nxv2f64_f64:903; CHECK: # %bb.0: # %entry904; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma905; CHECK-NEXT: vfsub.vf v8, v8, fa0906; CHECK-NEXT: ret907entry:908 %a = call <vscale x 2 x double> @llvm.riscv.vfsub.nxv2f64.f64(909 <vscale x 2 x double> poison,910 <vscale x 2 x double> %0,911 double %1,912 iXLen 7, iXLen %2)913 914 ret <vscale x 2 x double> %a915}916 917define <vscale x 2 x double> @intrinsic_vfsub_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {918; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv2f64_nxv2f64_f64:919; CHECK: # %bb.0: # %entry920; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu921; CHECK-NEXT: vfsub.vf v8, v10, fa0, v0.t922; CHECK-NEXT: ret923entry:924 %a = call <vscale x 2 x double> @llvm.riscv.vfsub.mask.nxv2f64.f64(925 <vscale x 2 x double> %0,926 <vscale x 2 x double> %1,927 double %2,928 <vscale x 2 x i1> %3,929 iXLen 7, iXLen %4, iXLen 1)930 931 ret <vscale x 2 x double> %a932}933 934define <vscale x 4 x double> @intrinsic_vfsub_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {935; CHECK-LABEL: intrinsic_vfsub_vf_nxv4f64_nxv4f64_f64:936; CHECK: # %bb.0: # %entry937; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma938; CHECK-NEXT: vfsub.vf v8, v8, fa0939; CHECK-NEXT: ret940entry:941 %a = call <vscale x 4 x double> @llvm.riscv.vfsub.nxv4f64.f64(942 <vscale x 4 x double> poison,943 <vscale x 4 x double> %0,944 double %1,945 iXLen 7, iXLen %2)946 947 ret <vscale x 4 x double> %a948}949 950define <vscale x 4 x double> @intrinsic_vfsub_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {951; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv4f64_nxv4f64_f64:952; CHECK: # %bb.0: # %entry953; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu954; CHECK-NEXT: vfsub.vf v8, v12, fa0, v0.t955; CHECK-NEXT: ret956entry:957 %a = call <vscale x 4 x double> @llvm.riscv.vfsub.mask.nxv4f64.f64(958 <vscale x 4 x double> %0,959 <vscale x 4 x double> %1,960 double %2,961 <vscale x 4 x i1> %3,962 iXLen 7, iXLen %4, iXLen 1)963 964 ret <vscale x 4 x double> %a965}966 967define <vscale x 8 x double> @intrinsic_vfsub_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, iXLen %2) nounwind {968; CHECK-LABEL: intrinsic_vfsub_vf_nxv8f64_nxv8f64_f64:969; CHECK: # %bb.0: # %entry970; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma971; CHECK-NEXT: vfsub.vf v8, v8, fa0972; CHECK-NEXT: ret973entry:974 %a = call <vscale x 8 x double> @llvm.riscv.vfsub.nxv8f64.f64(975 <vscale x 8 x double> poison,976 <vscale x 8 x double> %0,977 double %1,978 iXLen 7, iXLen %2)979 980 ret <vscale x 8 x double> %a981}982 983define <vscale x 8 x double> @intrinsic_vfsub_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {984; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv8f64_nxv8f64_f64:985; CHECK: # %bb.0: # %entry986; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu987; CHECK-NEXT: vfsub.vf v8, v16, fa0, v0.t988; CHECK-NEXT: ret989entry:990 %a = call <vscale x 8 x double> @llvm.riscv.vfsub.mask.nxv8f64.f64(991 <vscale x 8 x double> %0,992 <vscale x 8 x double> %1,993 double %2,994 <vscale x 8 x i1> %3,995 iXLen 7, iXLen %4, iXLen 1)996 997 ret <vscale x 8 x double> %a998}999