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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x float> @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1bf16(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma12; CHECK-NEXT: vfwadd.wv v8, v8, v913; CHECK-NEXT: fsrm a114; CHECK-NEXT: ret15entry:16 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16(17 <vscale x 1 x float> poison,18 <vscale x 1 x float> %0,19 <vscale x 1 x bfloat> %1,20 iXLen 0, iXLen %2)21 22 ret <vscale x 1 x float> %a23}24 25define <vscale x 1 x float> @intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1bf16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {26; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1bf16:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: fsrmi a1, 029; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu30; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t31; CHECK-NEXT: fsrm a132; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1bf16(35 <vscale x 1 x float> %0,36 <vscale x 1 x float> %1,37 <vscale x 1 x bfloat> %2,38 <vscale x 1 x i1> %3,39 iXLen 0, iXLen %4, iXLen 1)40 41 ret <vscale x 1 x float> %a42}43 44define <vscale x 2 x float> @intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2bf16(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, iXLen %2) nounwind {45; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2bf16:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: fsrmi a1, 048; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma49; CHECK-NEXT: vfwadd.wv v8, v8, v950; CHECK-NEXT: fsrm a151; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16(54 <vscale x 2 x float> poison,55 <vscale x 2 x float> %0,56 <vscale x 2 x bfloat> %1,57 iXLen 0, iXLen %2)58 59 ret <vscale x 2 x float> %a60}61 62define <vscale x 2 x float> @intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2bf16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {63; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2bf16:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: fsrmi a1, 066; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu67; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t68; CHECK-NEXT: fsrm a169; CHECK-NEXT: ret70entry:71 %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2bf16(72 <vscale x 2 x float> %0,73 <vscale x 2 x float> %1,74 <vscale x 2 x bfloat> %2,75 <vscale x 2 x i1> %3,76 iXLen 0, iXLen %4, iXLen 1)77 78 ret <vscale x 2 x float> %a79}80 81define <vscale x 4 x float> @intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4bf16(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, iXLen %2) nounwind {82; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4bf16:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: fsrmi a1, 085; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma86; CHECK-NEXT: vfwadd.wv v8, v8, v1087; CHECK-NEXT: fsrm a188; CHECK-NEXT: ret89entry:90 %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.nxv4bf16(91 <vscale x 4 x float> poison,92 <vscale x 4 x float> %0,93 <vscale x 4 x bfloat> %1,94 iXLen 0, iXLen %2)95 96 ret <vscale x 4 x float> %a97}98 99define <vscale x 4 x float> @intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4bf16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {100; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4bf16:101; CHECK: # %bb.0: # %entry102; CHECK-NEXT: fsrmi a1, 0103; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu104; CHECK-NEXT: vfwadd.wv v8, v10, v12, v0.t105; CHECK-NEXT: fsrm a1106; CHECK-NEXT: ret107entry:108 %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4bf16(109 <vscale x 4 x float> %0,110 <vscale x 4 x float> %1,111 <vscale x 4 x bfloat> %2,112 <vscale x 4 x i1> %3,113 iXLen 0, iXLen %4, iXLen 1)114 115 ret <vscale x 4 x float> %a116}117 118define <vscale x 8 x float> @intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8bf16(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, iXLen %2) nounwind {119; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8bf16:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: fsrmi a1, 0122; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma123; CHECK-NEXT: vfwadd.wv v8, v8, v12124; CHECK-NEXT: fsrm a1125; CHECK-NEXT: ret126entry:127 %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.nxv8bf16(128 <vscale x 8 x float> poison,129 <vscale x 8 x float> %0,130 <vscale x 8 x bfloat> %1,131 iXLen 0, iXLen %2)132 133 ret <vscale x 8 x float> %a134}135 136define <vscale x 8 x float> @intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8bf16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {137; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8bf16:138; CHECK: # %bb.0: # %entry139; CHECK-NEXT: fsrmi a1, 0140; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu141; CHECK-NEXT: vfwadd.wv v8, v12, v16, v0.t142; CHECK-NEXT: fsrm a1143; CHECK-NEXT: ret144entry:145 %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8bf16(146 <vscale x 8 x float> %0,147 <vscale x 8 x float> %1,148 <vscale x 8 x bfloat> %2,149 <vscale x 8 x i1> %3,150 iXLen 0, iXLen %4, iXLen 1)151 152 ret <vscale x 8 x float> %a153}154 155define <vscale x 16 x float> @intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16bf16(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, iXLen %2) nounwind {156; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16bf16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: fsrmi a1, 0159; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma160; CHECK-NEXT: vfwadd.wv v8, v8, v16161; CHECK-NEXT: fsrm a1162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.nxv16bf16(165 <vscale x 16 x float> poison,166 <vscale x 16 x float> %0,167 <vscale x 16 x bfloat> %1,168 iXLen 0, iXLen %2)169 170 ret <vscale x 16 x float> %a171}172 173define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16bf16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x bfloat> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {174; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16bf16:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: vl4re16.v v24, (a0)177; CHECK-NEXT: fsrmi a0, 0178; CHECK-NEXT: vsetvli zero, a1, e16alt, m4, ta, mu179; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t180; CHECK-NEXT: fsrm a0181; CHECK-NEXT: ret182entry:183 %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16bf16(184 <vscale x 16 x float> %0,185 <vscale x 16 x float> %1,186 <vscale x 16 x bfloat> %2,187 <vscale x 16 x i1> %3,188 iXLen 0, iXLen %4, iXLen 1)189 190 ret <vscale x 16 x float> %a191}192 193define <vscale x 1 x float> @intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_bf16(<vscale x 1 x float> %0, bfloat %1, iXLen %2) nounwind {194; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_bf16:195; CHECK: # %bb.0: # %entry196; CHECK-NEXT: fsrmi a1, 0197; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma198; CHECK-NEXT: vfwadd.wf v8, v8, fa0199; CHECK-NEXT: fsrm a1200; CHECK-NEXT: ret201entry:202 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.bf16(203 <vscale x 1 x float> poison,204 <vscale x 1 x float> %0,205 bfloat %1,206 iXLen 0, iXLen %2)207 208 ret <vscale x 1 x float> %a209}210 211define <vscale x 1 x float> @intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_bf16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, bfloat %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {212; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_bf16:213; CHECK: # %bb.0: # %entry214; CHECK-NEXT: fsrmi a1, 0215; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu216; CHECK-NEXT: vfwadd.wf v8, v9, fa0, v0.t217; CHECK-NEXT: fsrm a1218; CHECK-NEXT: ret219entry:220 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.bf16(221 <vscale x 1 x float> %0,222 <vscale x 1 x float> %1,223 bfloat %2,224 <vscale x 1 x i1> %3,225 iXLen 0, iXLen %4, iXLen 1)226 227 ret <vscale x 1 x float> %a228}229 230define <vscale x 2 x float> @intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_bf16(<vscale x 2 x float> %0, bfloat %1, iXLen %2) nounwind {231; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_bf16:232; CHECK: # %bb.0: # %entry233; CHECK-NEXT: fsrmi a1, 0234; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma235; CHECK-NEXT: vfwadd.wf v8, v8, fa0236; CHECK-NEXT: fsrm a1237; CHECK-NEXT: ret238entry:239 %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.bf16(240 <vscale x 2 x float> poison,241 <vscale x 2 x float> %0,242 bfloat %1,243 iXLen 0, iXLen %2)244 245 ret <vscale x 2 x float> %a246}247 248define <vscale x 2 x float> @intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_bf16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, bfloat %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {249; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_bf16:250; CHECK: # %bb.0: # %entry251; CHECK-NEXT: fsrmi a1, 0252; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu253; CHECK-NEXT: vfwadd.wf v8, v9, fa0, v0.t254; CHECK-NEXT: fsrm a1255; CHECK-NEXT: ret256entry:257 %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.bf16(258 <vscale x 2 x float> %0,259 <vscale x 2 x float> %1,260 bfloat %2,261 <vscale x 2 x i1> %3,262 iXLen 0, iXLen %4, iXLen 1)263 264 ret <vscale x 2 x float> %a265}266 267define <vscale x 4 x float> @intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_bf16(<vscale x 4 x float> %0, bfloat %1, iXLen %2) nounwind {268; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_bf16:269; CHECK: # %bb.0: # %entry270; CHECK-NEXT: fsrmi a1, 0271; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma272; CHECK-NEXT: vfwadd.wf v8, v8, fa0273; CHECK-NEXT: fsrm a1274; CHECK-NEXT: ret275entry:276 %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.bf16(277 <vscale x 4 x float> poison,278 <vscale x 4 x float> %0,279 bfloat %1,280 iXLen 0, iXLen %2)281 282 ret <vscale x 4 x float> %a283}284 285define <vscale x 4 x float> @intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_bf16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, bfloat %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {286; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_bf16:287; CHECK: # %bb.0: # %entry288; CHECK-NEXT: fsrmi a1, 0289; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu290; CHECK-NEXT: vfwadd.wf v8, v10, fa0, v0.t291; CHECK-NEXT: fsrm a1292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.bf16(295 <vscale x 4 x float> %0,296 <vscale x 4 x float> %1,297 bfloat %2,298 <vscale x 4 x i1> %3,299 iXLen 0, iXLen %4, iXLen 1)300 301 ret <vscale x 4 x float> %a302}303 304define <vscale x 8 x float> @intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_bf16(<vscale x 8 x float> %0, bfloat %1, iXLen %2) nounwind {305; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_bf16:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: fsrmi a1, 0308; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma309; CHECK-NEXT: vfwadd.wf v8, v8, fa0310; CHECK-NEXT: fsrm a1311; CHECK-NEXT: ret312entry:313 %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.bf16(314 <vscale x 8 x float> poison,315 <vscale x 8 x float> %0,316 bfloat %1,317 iXLen 0, iXLen %2)318 319 ret <vscale x 8 x float> %a320}321 322define <vscale x 8 x float> @intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_bf16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, bfloat %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {323; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_bf16:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: fsrmi a1, 0326; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu327; CHECK-NEXT: vfwadd.wf v8, v12, fa0, v0.t328; CHECK-NEXT: fsrm a1329; CHECK-NEXT: ret330entry:331 %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.bf16(332 <vscale x 8 x float> %0,333 <vscale x 8 x float> %1,334 bfloat %2,335 <vscale x 8 x i1> %3,336 iXLen 0, iXLen %4, iXLen 1)337 338 ret <vscale x 8 x float> %a339}340 341define <vscale x 16 x float> @intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_bf16(<vscale x 16 x float> %0, bfloat %1, iXLen %2) nounwind {342; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_bf16:343; CHECK: # %bb.0: # %entry344; CHECK-NEXT: fsrmi a1, 0345; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma346; CHECK-NEXT: vfwadd.wf v8, v8, fa0347; CHECK-NEXT: fsrm a1348; CHECK-NEXT: ret349entry:350 %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.bf16(351 <vscale x 16 x float> poison,352 <vscale x 16 x float> %0,353 bfloat %1,354 iXLen 0, iXLen %2)355 356 ret <vscale x 16 x float> %a357}358 359define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_bf16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, bfloat %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {360; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_bf16:361; CHECK: # %bb.0: # %entry362; CHECK-NEXT: fsrmi a1, 0363; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu364; CHECK-NEXT: vfwadd.wf v8, v16, fa0, v0.t365; CHECK-NEXT: fsrm a1366; CHECK-NEXT: ret367entry:368 %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.bf16(369 <vscale x 16 x float> %0,370 <vscale x 16 x float> %1,371 bfloat %2,372 <vscale x 16 x i1> %3,373 iXLen 0, iXLen %4, iXLen 1)374 375 ret <vscale x 16 x float> %a376}377 378define <vscale x 1 x float> @intrinsic_vfwadd.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1bf16(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {379; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1bf16:380; CHECK: # %bb.0: # %entry381; CHECK-NEXT: fsrmi a1, 0382; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu383; CHECK-NEXT: vfwadd.wv v8, v8, v9, v0.t384; CHECK-NEXT: fsrm a1385; CHECK-NEXT: ret386entry:387 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1bf16(388 <vscale x 1 x float> %0,389 <vscale x 1 x float> %0,390 <vscale x 1 x bfloat> %1,391 <vscale x 1 x i1> %2,392 iXLen 0, iXLen %3, iXLen 1)393 394 ret <vscale x 1 x float> %a395}396 397define <vscale x 2 x float> @intrinsic_vfwadd.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2bf16(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {398; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2bf16:399; CHECK: # %bb.0: # %entry400; CHECK-NEXT: fsrmi a1, 0401; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu402; CHECK-NEXT: vfwadd.wv v8, v8, v9, v0.t403; CHECK-NEXT: fsrm a1404; CHECK-NEXT: ret405entry:406 %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2bf16(407 <vscale x 2 x float> %0,408 <vscale x 2 x float> %0,409 <vscale x 2 x bfloat> %1,410 <vscale x 2 x i1> %2,411 iXLen 0, iXLen %3, iXLen 1)412 413 ret <vscale x 2 x float> %a414}415 416define <vscale x 4 x float> @intrinsic_vfwadd.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4bf16(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {417; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4bf16:418; CHECK: # %bb.0: # %entry419; CHECK-NEXT: fsrmi a1, 0420; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu421; CHECK-NEXT: vfwadd.wv v8, v8, v10, v0.t422; CHECK-NEXT: fsrm a1423; CHECK-NEXT: ret424entry:425 %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4bf16(426 <vscale x 4 x float> %0,427 <vscale x 4 x float> %0,428 <vscale x 4 x bfloat> %1,429 <vscale x 4 x i1> %2,430 iXLen 0, iXLen %3, iXLen 1)431 432 ret <vscale x 4 x float> %a433}434 435define <vscale x 8 x float> @intrinsic_vfwadd.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8bf16(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {436; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8bf16:437; CHECK: # %bb.0: # %entry438; CHECK-NEXT: fsrmi a1, 0439; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu440; CHECK-NEXT: vfwadd.wv v8, v8, v12, v0.t441; CHECK-NEXT: fsrm a1442; CHECK-NEXT: ret443entry:444 %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8bf16(445 <vscale x 8 x float> %0,446 <vscale x 8 x float> %0,447 <vscale x 8 x bfloat> %1,448 <vscale x 8 x i1> %2,449 iXLen 0, iXLen %3, iXLen 1)450 451 ret <vscale x 8 x float> %a452}453 454define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16bf16(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {455; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16bf16:456; CHECK: # %bb.0: # %entry457; CHECK-NEXT: fsrmi a1, 0458; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu459; CHECK-NEXT: vfwadd.wv v8, v8, v16, v0.t460; CHECK-NEXT: fsrm a1461; CHECK-NEXT: ret462entry:463 %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16bf16(464 <vscale x 16 x float> %0,465 <vscale x 16 x float> %0,466 <vscale x 16 x bfloat> %1,467 <vscale x 16 x i1> %2,468 iXLen 0, iXLen %3, iXLen 1)469 470 ret <vscale x 16 x float> %a471}472 473define <vscale x 1 x float> @intrinsic_vfwadd.w_mask_wf_tie_nxv1f32_nxv1f32_bf16(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {474; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv1f32_nxv1f32_bf16:475; CHECK: # %bb.0: # %entry476; CHECK-NEXT: fsrmi a1, 0477; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu478; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t479; CHECK-NEXT: fsrm a1480; CHECK-NEXT: ret481entry:482 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.mask.nxv1f32.bf16(483 <vscale x 1 x float> %0,484 <vscale x 1 x float> %0,485 bfloat %1,486 <vscale x 1 x i1> %2,487 iXLen 0, iXLen %3, iXLen 1)488 489 ret <vscale x 1 x float> %a490}491 492define <vscale x 2 x float> @intrinsic_vfwadd.w_mask_wf_tie_nxv2f32_nxv2f32_bf16(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {493; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv2f32_nxv2f32_bf16:494; CHECK: # %bb.0: # %entry495; CHECK-NEXT: fsrmi a1, 0496; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu497; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t498; CHECK-NEXT: fsrm a1499; CHECK-NEXT: ret500entry:501 %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.mask.nxv2f32.bf16(502 <vscale x 2 x float> %0,503 <vscale x 2 x float> %0,504 bfloat %1,505 <vscale x 2 x i1> %2,506 iXLen 0, iXLen %3, iXLen 1)507 508 ret <vscale x 2 x float> %a509}510 511define <vscale x 4 x float> @intrinsic_vfwadd.w_mask_wf_tie_nxv4f32_nxv4f32_bf16(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {512; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv4f32_nxv4f32_bf16:513; CHECK: # %bb.0: # %entry514; CHECK-NEXT: fsrmi a1, 0515; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu516; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t517; CHECK-NEXT: fsrm a1518; CHECK-NEXT: ret519entry:520 %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.mask.nxv4f32.bf16(521 <vscale x 4 x float> %0,522 <vscale x 4 x float> %0,523 bfloat %1,524 <vscale x 4 x i1> %2,525 iXLen 0, iXLen %3, iXLen 1)526 527 ret <vscale x 4 x float> %a528}529 530define <vscale x 8 x float> @intrinsic_vfwadd.w_mask_wf_tie_nxv8f32_nxv8f32_bf16(<vscale x 8 x float> %0, bfloat %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {531; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv8f32_nxv8f32_bf16:532; CHECK: # %bb.0: # %entry533; CHECK-NEXT: fsrmi a1, 0534; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu535; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t536; CHECK-NEXT: fsrm a1537; CHECK-NEXT: ret538entry:539 %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.mask.nxv8f32.bf16(540 <vscale x 8 x float> %0,541 <vscale x 8 x float> %0,542 bfloat %1,543 <vscale x 8 x i1> %2,544 iXLen 0, iXLen %3, iXLen 1)545 546 ret <vscale x 8 x float> %a547}548 549define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wf_tie_nxv16f32_nxv16f32_bf16(<vscale x 16 x float> %0, bfloat %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {550; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv16f32_nxv16f32_bf16:551; CHECK: # %bb.0: # %entry552; CHECK-NEXT: fsrmi a1, 0553; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu554; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t555; CHECK-NEXT: fsrm a1556; CHECK-NEXT: ret557entry:558 %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.bf16(559 <vscale x 16 x float> %0,560 <vscale x 16 x float> %0,561 bfloat %1,562 <vscale x 16 x i1> %2,563 iXLen 0, iXLen %3, iXLen 1)564 565 ret <vscale x 16 x float> %a566}567 568define <vscale x 1 x float> @intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {569; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1bf16:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: fsrmi a1, 0572; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma573; CHECK-NEXT: vfwadd.wv v10, v9, v8574; CHECK-NEXT: fsrm a1575; CHECK-NEXT: vmv1r.v v8, v10576; CHECK-NEXT: ret577entry:578 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16(579 <vscale x 1 x float> poison,580 <vscale x 1 x float> %1,581 <vscale x 1 x bfloat> %0,582 iXLen 0, iXLen %2)583 584 ret <vscale x 1 x float> %a585}586 587define <vscale x 2 x float> @intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {588; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2bf16:589; CHECK: # %bb.0: # %entry590; CHECK-NEXT: fsrmi a1, 0591; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma592; CHECK-NEXT: vfwadd.wv v10, v9, v8593; CHECK-NEXT: fsrm a1594; CHECK-NEXT: vmv1r.v v8, v10595; CHECK-NEXT: ret596entry:597 %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16(598 <vscale x 2 x float> poison,599 <vscale x 2 x float> %1,600 <vscale x 2 x bfloat> %0,601 iXLen 0, iXLen %2)602 603 ret <vscale x 2 x float> %a604}605 606define <vscale x 4 x float> @intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {607; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4bf16:608; CHECK: # %bb.0: # %entry609; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma610; CHECK-NEXT: vmv1r.v v12, v8611; CHECK-NEXT: fsrmi a0, 0612; CHECK-NEXT: vfwadd.wv v8, v10, v12613; CHECK-NEXT: fsrm a0614; CHECK-NEXT: ret615entry:616 %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.nxv4bf16(617 <vscale x 4 x float> poison,618 <vscale x 4 x float> %1,619 <vscale x 4 x bfloat> %0,620 iXLen 0, iXLen %2)621 622 ret <vscale x 4 x float> %a623}624 625define <vscale x 8 x float> @intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {626; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8bf16:627; CHECK: # %bb.0: # %entry628; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma629; CHECK-NEXT: vmv2r.v v16, v8630; CHECK-NEXT: fsrmi a0, 0631; CHECK-NEXT: vfwadd.wv v8, v12, v16632; CHECK-NEXT: fsrm a0633; CHECK-NEXT: ret634entry:635 %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.nxv8bf16(636 <vscale x 8 x float> poison,637 <vscale x 8 x float> %1,638 <vscale x 8 x bfloat> %0,639 iXLen 0, iXLen %2)640 641 ret <vscale x 8 x float> %a642}643 644