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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x float> @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma12; CHECK-NEXT: vfwadd.vv v10, v8, v913; CHECK-NEXT: fsrm a114; CHECK-NEXT: vmv1r.v v8, v1015; CHECK-NEXT: ret16entry:17 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16(18 <vscale x 1 x float> poison,19 <vscale x 1 x half> %0,20 <vscale x 1 x half> %1,21 iXLen 0, iXLen %2)22 23 ret <vscale x 1 x float> %a24}25 26define <vscale x 1 x float> @intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {27; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16:28; CHECK: # %bb.0: # %entry29; CHECK-NEXT: fsrmi a1, 030; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu31; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t32; CHECK-NEXT: fsrm a133; CHECK-NEXT: ret34entry:35 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16(36 <vscale x 1 x float> %0,37 <vscale x 1 x half> %1,38 <vscale x 1 x half> %2,39 <vscale x 1 x i1> %3,40 iXLen 0, iXLen %4, iXLen 1)41 42 ret <vscale x 1 x float> %a43}44 45define <vscale x 2 x float> @intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {46; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16:47; CHECK: # %bb.0: # %entry48; CHECK-NEXT: fsrmi a1, 049; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma50; CHECK-NEXT: vfwadd.vv v10, v8, v951; CHECK-NEXT: fsrm a152; CHECK-NEXT: vmv1r.v v8, v1053; CHECK-NEXT: ret54entry:55 %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16(56 <vscale x 2 x float> poison,57 <vscale x 2 x half> %0,58 <vscale x 2 x half> %1,59 iXLen 0, iXLen %2)60 61 ret <vscale x 2 x float> %a62}63 64define <vscale x 2 x float> @intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {65; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16:66; CHECK: # %bb.0: # %entry67; CHECK-NEXT: fsrmi a1, 068; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu69; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t70; CHECK-NEXT: fsrm a171; CHECK-NEXT: ret72entry:73 %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16(74 <vscale x 2 x float> %0,75 <vscale x 2 x half> %1,76 <vscale x 2 x half> %2,77 <vscale x 2 x i1> %3,78 iXLen 0, iXLen %4, iXLen 1)79 80 ret <vscale x 2 x float> %a81}82 83define <vscale x 4 x float> @intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {84; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16:85; CHECK: # %bb.0: # %entry86; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma87; CHECK-NEXT: vmv1r.v v10, v988; CHECK-NEXT: vmv1r.v v11, v889; CHECK-NEXT: fsrmi a0, 090; CHECK-NEXT: vfwadd.vv v8, v11, v1091; CHECK-NEXT: fsrm a092; CHECK-NEXT: ret93entry:94 %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16(95 <vscale x 4 x float> poison,96 <vscale x 4 x half> %0,97 <vscale x 4 x half> %1,98 iXLen 0, iXLen %2)99 100 ret <vscale x 4 x float> %a101}102 103define <vscale x 4 x float> @intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {104; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: fsrmi a1, 0107; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu108; CHECK-NEXT: vfwadd.vv v8, v10, v11, v0.t109; CHECK-NEXT: fsrm a1110; CHECK-NEXT: ret111entry:112 %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16(113 <vscale x 4 x float> %0,114 <vscale x 4 x half> %1,115 <vscale x 4 x half> %2,116 <vscale x 4 x i1> %3,117 iXLen 0, iXLen %4, iXLen 1)118 119 ret <vscale x 4 x float> %a120}121 122define <vscale x 8 x float> @intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {123; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma126; CHECK-NEXT: vmv2r.v v12, v10127; CHECK-NEXT: vmv2r.v v14, v8128; CHECK-NEXT: fsrmi a0, 0129; CHECK-NEXT: vfwadd.vv v8, v14, v12130; CHECK-NEXT: fsrm a0131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f32.nxv8f16.nxv8f16(134 <vscale x 8 x float> poison,135 <vscale x 8 x half> %0,136 <vscale x 8 x half> %1,137 iXLen 0, iXLen %2)138 139 ret <vscale x 8 x float> %a140}141 142define <vscale x 8 x float> @intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {143; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16:144; CHECK: # %bb.0: # %entry145; CHECK-NEXT: fsrmi a1, 0146; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu147; CHECK-NEXT: vfwadd.vv v8, v12, v14, v0.t148; CHECK-NEXT: fsrm a1149; CHECK-NEXT: ret150entry:151 %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16(152 <vscale x 8 x float> %0,153 <vscale x 8 x half> %1,154 <vscale x 8 x half> %2,155 <vscale x 8 x i1> %3,156 iXLen 0, iXLen %4, iXLen 1)157 158 ret <vscale x 8 x float> %a159}160 161define <vscale x 16 x float> @intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {162; CHECK-LABEL: intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma165; CHECK-NEXT: vmv4r.v v16, v12166; CHECK-NEXT: vmv4r.v v20, v8167; CHECK-NEXT: fsrmi a0, 0168; CHECK-NEXT: vfwadd.vv v8, v20, v16169; CHECK-NEXT: fsrm a0170; CHECK-NEXT: ret171entry:172 %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f32.nxv16f16.nxv16f16(173 <vscale x 16 x float> poison,174 <vscale x 16 x half> %0,175 <vscale x 16 x half> %1,176 iXLen 0, iXLen %2)177 178 ret <vscale x 16 x float> %a179}180 181define <vscale x 16 x float> @intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {182; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16:183; CHECK: # %bb.0: # %entry184; CHECK-NEXT: fsrmi a1, 0185; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu186; CHECK-NEXT: vfwadd.vv v8, v16, v20, v0.t187; CHECK-NEXT: fsrm a1188; CHECK-NEXT: ret189entry:190 %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16(191 <vscale x 16 x float> %0,192 <vscale x 16 x half> %1,193 <vscale x 16 x half> %2,194 <vscale x 16 x i1> %3,195 iXLen 0, iXLen %4, iXLen 1)196 197 ret <vscale x 16 x float> %a198}199 200define <vscale x 1 x double> @intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {201; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32:202; CHECK: # %bb.0: # %entry203; CHECK-NEXT: fsrmi a1, 0204; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma205; CHECK-NEXT: vfwadd.vv v10, v8, v9206; CHECK-NEXT: fsrm a1207; CHECK-NEXT: vmv1r.v v8, v10208; CHECK-NEXT: ret209entry:210 %a = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32(211 <vscale x 1 x double> poison,212 <vscale x 1 x float> %0,213 <vscale x 1 x float> %1,214 iXLen 0, iXLen %2)215 216 ret <vscale x 1 x double> %a217}218 219define <vscale x 1 x double> @intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {220; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32:221; CHECK: # %bb.0: # %entry222; CHECK-NEXT: fsrmi a1, 0223; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu224; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t225; CHECK-NEXT: fsrm a1226; CHECK-NEXT: ret227entry:228 %a = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32(229 <vscale x 1 x double> %0,230 <vscale x 1 x float> %1,231 <vscale x 1 x float> %2,232 <vscale x 1 x i1> %3,233 iXLen 0, iXLen %4, iXLen 1)234 235 ret <vscale x 1 x double> %a236}237 238define <vscale x 2 x double> @intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {239; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma242; CHECK-NEXT: vmv1r.v v10, v9243; CHECK-NEXT: vmv1r.v v11, v8244; CHECK-NEXT: fsrmi a0, 0245; CHECK-NEXT: vfwadd.vv v8, v11, v10246; CHECK-NEXT: fsrm a0247; CHECK-NEXT: ret248entry:249 %a = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f64.nxv2f32.nxv2f32(250 <vscale x 2 x double> poison,251 <vscale x 2 x float> %0,252 <vscale x 2 x float> %1,253 iXLen 0, iXLen %2)254 255 ret <vscale x 2 x double> %a256}257 258define <vscale x 2 x double> @intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {259; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32:260; CHECK: # %bb.0: # %entry261; CHECK-NEXT: fsrmi a1, 0262; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu263; CHECK-NEXT: vfwadd.vv v8, v10, v11, v0.t264; CHECK-NEXT: fsrm a1265; CHECK-NEXT: ret266entry:267 %a = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32(268 <vscale x 2 x double> %0,269 <vscale x 2 x float> %1,270 <vscale x 2 x float> %2,271 <vscale x 2 x i1> %3,272 iXLen 0, iXLen %4, iXLen 1)273 274 ret <vscale x 2 x double> %a275}276 277define <vscale x 4 x double> @intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {278; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32:279; CHECK: # %bb.0: # %entry280; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma281; CHECK-NEXT: vmv2r.v v12, v10282; CHECK-NEXT: vmv2r.v v14, v8283; CHECK-NEXT: fsrmi a0, 0284; CHECK-NEXT: vfwadd.vv v8, v14, v12285; CHECK-NEXT: fsrm a0286; CHECK-NEXT: ret287entry:288 %a = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32(289 <vscale x 4 x double> poison,290 <vscale x 4 x float> %0,291 <vscale x 4 x float> %1,292 iXLen 0, iXLen %2)293 294 ret <vscale x 4 x double> %a295}296 297define <vscale x 4 x double> @intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {298; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32:299; CHECK: # %bb.0: # %entry300; CHECK-NEXT: fsrmi a1, 0301; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu302; CHECK-NEXT: vfwadd.vv v8, v12, v14, v0.t303; CHECK-NEXT: fsrm a1304; CHECK-NEXT: ret305entry:306 %a = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32(307 <vscale x 4 x double> %0,308 <vscale x 4 x float> %1,309 <vscale x 4 x float> %2,310 <vscale x 4 x i1> %3,311 iXLen 0, iXLen %4, iXLen 1)312 313 ret <vscale x 4 x double> %a314}315 316define <vscale x 8 x double> @intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {317; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32:318; CHECK: # %bb.0: # %entry319; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma320; CHECK-NEXT: vmv4r.v v16, v12321; CHECK-NEXT: vmv4r.v v20, v8322; CHECK-NEXT: fsrmi a0, 0323; CHECK-NEXT: vfwadd.vv v8, v20, v16324; CHECK-NEXT: fsrm a0325; CHECK-NEXT: ret326entry:327 %a = call <vscale x 8 x double> @llvm.riscv.vfwadd.nxv8f64.nxv8f32.nxv8f32(328 <vscale x 8 x double> poison,329 <vscale x 8 x float> %0,330 <vscale x 8 x float> %1,331 iXLen 0, iXLen %2)332 333 ret <vscale x 8 x double> %a334}335 336define <vscale x 8 x double> @intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {337; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32:338; CHECK: # %bb.0: # %entry339; CHECK-NEXT: fsrmi a1, 0340; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu341; CHECK-NEXT: vfwadd.vv v8, v16, v20, v0.t342; CHECK-NEXT: fsrm a1343; CHECK-NEXT: ret344entry:345 %a = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32(346 <vscale x 8 x double> %0,347 <vscale x 8 x float> %1,348 <vscale x 8 x float> %2,349 <vscale x 8 x i1> %3,350 iXLen 0, iXLen %4, iXLen 1)351 352 ret <vscale x 8 x double> %a353}354 355define <vscale x 1 x float> @intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {356; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16:357; CHECK: # %bb.0: # %entry358; CHECK-NEXT: fsrmi a1, 0359; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma360; CHECK-NEXT: vfwadd.vf v9, v8, fa0361; CHECK-NEXT: fsrm a1362; CHECK-NEXT: vmv1r.v v8, v9363; CHECK-NEXT: ret364entry:365 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16(366 <vscale x 1 x float> poison,367 <vscale x 1 x half> %0,368 half %1,369 iXLen 0, iXLen %2)370 371 ret <vscale x 1 x float> %a372}373 374define <vscale x 1 x float> @intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {375; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16:376; CHECK: # %bb.0: # %entry377; CHECK-NEXT: fsrmi a1, 0378; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu379; CHECK-NEXT: vfwadd.vf v8, v9, fa0, v0.t380; CHECK-NEXT: fsrm a1381; CHECK-NEXT: ret382entry:383 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16(384 <vscale x 1 x float> %0,385 <vscale x 1 x half> %1,386 half %2,387 <vscale x 1 x i1> %3,388 iXLen 0, iXLen %4, iXLen 1)389 390 ret <vscale x 1 x float> %a391}392 393define <vscale x 2 x float> @intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {394; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16:395; CHECK: # %bb.0: # %entry396; CHECK-NEXT: fsrmi a1, 0397; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma398; CHECK-NEXT: vfwadd.vf v9, v8, fa0399; CHECK-NEXT: fsrm a1400; CHECK-NEXT: vmv1r.v v8, v9401; CHECK-NEXT: ret402entry:403 %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16(404 <vscale x 2 x float> poison,405 <vscale x 2 x half> %0,406 half %1,407 iXLen 0, iXLen %2)408 409 ret <vscale x 2 x float> %a410}411 412define <vscale x 2 x float> @intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {413; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16:414; CHECK: # %bb.0: # %entry415; CHECK-NEXT: fsrmi a1, 0416; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu417; CHECK-NEXT: vfwadd.vf v8, v9, fa0, v0.t418; CHECK-NEXT: fsrm a1419; CHECK-NEXT: ret420entry:421 %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16(422 <vscale x 2 x float> %0,423 <vscale x 2 x half> %1,424 half %2,425 <vscale x 2 x i1> %3,426 iXLen 0, iXLen %4, iXLen 1)427 428 ret <vscale x 2 x float> %a429}430 431define <vscale x 4 x float> @intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {432; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16:433; CHECK: # %bb.0: # %entry434; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma435; CHECK-NEXT: vmv1r.v v10, v8436; CHECK-NEXT: fsrmi a0, 0437; CHECK-NEXT: vfwadd.vf v8, v10, fa0438; CHECK-NEXT: fsrm a0439; CHECK-NEXT: ret440entry:441 %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.nxv4f32.nxv4f16.f16(442 <vscale x 4 x float> poison,443 <vscale x 4 x half> %0,444 half %1,445 iXLen 0, iXLen %2)446 447 ret <vscale x 4 x float> %a448}449 450define <vscale x 4 x float> @intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {451; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16:452; CHECK: # %bb.0: # %entry453; CHECK-NEXT: fsrmi a1, 0454; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu455; CHECK-NEXT: vfwadd.vf v8, v10, fa0, v0.t456; CHECK-NEXT: fsrm a1457; CHECK-NEXT: ret458entry:459 %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16(460 <vscale x 4 x float> %0,461 <vscale x 4 x half> %1,462 half %2,463 <vscale x 4 x i1> %3,464 iXLen 0, iXLen %4, iXLen 1)465 466 ret <vscale x 4 x float> %a467}468 469define <vscale x 8 x float> @intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {470; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma473; CHECK-NEXT: vmv2r.v v12, v8474; CHECK-NEXT: fsrmi a0, 0475; CHECK-NEXT: vfwadd.vf v8, v12, fa0476; CHECK-NEXT: fsrm a0477; CHECK-NEXT: ret478entry:479 %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.nxv8f32.nxv8f16.f16(480 <vscale x 8 x float> poison,481 <vscale x 8 x half> %0,482 half %1,483 iXLen 0, iXLen %2)484 485 ret <vscale x 8 x float> %a486}487 488define <vscale x 8 x float> @intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {489; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16:490; CHECK: # %bb.0: # %entry491; CHECK-NEXT: fsrmi a1, 0492; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu493; CHECK-NEXT: vfwadd.vf v8, v12, fa0, v0.t494; CHECK-NEXT: fsrm a1495; CHECK-NEXT: ret496entry:497 %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16(498 <vscale x 8 x float> %0,499 <vscale x 8 x half> %1,500 half %2,501 <vscale x 8 x i1> %3,502 iXLen 0, iXLen %4, iXLen 1)503 504 ret <vscale x 8 x float> %a505}506 507define <vscale x 16 x float> @intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {508; CHECK-LABEL: intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16:509; CHECK: # %bb.0: # %entry510; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma511; CHECK-NEXT: vmv4r.v v16, v8512; CHECK-NEXT: fsrmi a0, 0513; CHECK-NEXT: vfwadd.vf v8, v16, fa0514; CHECK-NEXT: fsrm a0515; CHECK-NEXT: ret516entry:517 %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.nxv16f32.nxv16f16.f16(518 <vscale x 16 x float> poison,519 <vscale x 16 x half> %0,520 half %1,521 iXLen 0, iXLen %2)522 523 ret <vscale x 16 x float> %a524}525 526define <vscale x 16 x float> @intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {527; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16:528; CHECK: # %bb.0: # %entry529; CHECK-NEXT: fsrmi a1, 0530; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu531; CHECK-NEXT: vfwadd.vf v8, v16, fa0, v0.t532; CHECK-NEXT: fsrm a1533; CHECK-NEXT: ret534entry:535 %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16(536 <vscale x 16 x float> %0,537 <vscale x 16 x half> %1,538 half %2,539 <vscale x 16 x i1> %3,540 iXLen 0, iXLen %4, iXLen 1)541 542 ret <vscale x 16 x float> %a543}544 545define <vscale x 1 x double> @intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {546; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32:547; CHECK: # %bb.0: # %entry548; CHECK-NEXT: fsrmi a1, 0549; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma550; CHECK-NEXT: vfwadd.vf v9, v8, fa0551; CHECK-NEXT: fsrm a1552; CHECK-NEXT: vmv1r.v v8, v9553; CHECK-NEXT: ret554entry:555 %a = call <vscale x 1 x double> @llvm.riscv.vfwadd.nxv1f64.nxv1f32.f32(556 <vscale x 1 x double> poison,557 <vscale x 1 x float> %0,558 float %1,559 iXLen 0, iXLen %2)560 561 ret <vscale x 1 x double> %a562}563 564define <vscale x 1 x double> @intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {565; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32:566; CHECK: # %bb.0: # %entry567; CHECK-NEXT: fsrmi a1, 0568; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu569; CHECK-NEXT: vfwadd.vf v8, v9, fa0, v0.t570; CHECK-NEXT: fsrm a1571; CHECK-NEXT: ret572entry:573 %a = call <vscale x 1 x double> @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32(574 <vscale x 1 x double> %0,575 <vscale x 1 x float> %1,576 float %2,577 <vscale x 1 x i1> %3,578 iXLen 0, iXLen %4, iXLen 1)579 580 ret <vscale x 1 x double> %a581}582 583define <vscale x 2 x double> @intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {584; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32:585; CHECK: # %bb.0: # %entry586; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma587; CHECK-NEXT: vmv1r.v v10, v8588; CHECK-NEXT: fsrmi a0, 0589; CHECK-NEXT: vfwadd.vf v8, v10, fa0590; CHECK-NEXT: fsrm a0591; CHECK-NEXT: ret592entry:593 %a = call <vscale x 2 x double> @llvm.riscv.vfwadd.nxv2f64.nxv2f32.f32(594 <vscale x 2 x double> poison,595 <vscale x 2 x float> %0,596 float %1,597 iXLen 0, iXLen %2)598 599 ret <vscale x 2 x double> %a600}601 602define <vscale x 2 x double> @intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {603; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32:604; CHECK: # %bb.0: # %entry605; CHECK-NEXT: fsrmi a1, 0606; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu607; CHECK-NEXT: vfwadd.vf v8, v10, fa0, v0.t608; CHECK-NEXT: fsrm a1609; CHECK-NEXT: ret610entry:611 %a = call <vscale x 2 x double> @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32(612 <vscale x 2 x double> %0,613 <vscale x 2 x float> %1,614 float %2,615 <vscale x 2 x i1> %3,616 iXLen 0, iXLen %4, iXLen 1)617 618 ret <vscale x 2 x double> %a619}620 621define <vscale x 4 x double> @intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {622; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32:623; CHECK: # %bb.0: # %entry624; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma625; CHECK-NEXT: vmv2r.v v12, v8626; CHECK-NEXT: fsrmi a0, 0627; CHECK-NEXT: vfwadd.vf v8, v12, fa0628; CHECK-NEXT: fsrm a0629; CHECK-NEXT: ret630entry:631 %a = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32(632 <vscale x 4 x double> poison,633 <vscale x 4 x float> %0,634 float %1,635 iXLen 0, iXLen %2)636 637 ret <vscale x 4 x double> %a638}639 640define <vscale x 4 x double> @intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {641; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32:642; CHECK: # %bb.0: # %entry643; CHECK-NEXT: fsrmi a1, 0644; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu645; CHECK-NEXT: vfwadd.vf v8, v12, fa0, v0.t646; CHECK-NEXT: fsrm a1647; CHECK-NEXT: ret648entry:649 %a = call <vscale x 4 x double> @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32(650 <vscale x 4 x double> %0,651 <vscale x 4 x float> %1,652 float %2,653 <vscale x 4 x i1> %3,654 iXLen 0, iXLen %4, iXLen 1)655 656 ret <vscale x 4 x double> %a657}658 659define <vscale x 8 x double> @intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {660; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32:661; CHECK: # %bb.0: # %entry662; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma663; CHECK-NEXT: vmv4r.v v16, v8664; CHECK-NEXT: fsrmi a0, 0665; CHECK-NEXT: vfwadd.vf v8, v16, fa0666; CHECK-NEXT: fsrm a0667; CHECK-NEXT: ret668entry:669 %a = call <vscale x 8 x double> @llvm.riscv.vfwadd.nxv8f64.nxv8f32.f32(670 <vscale x 8 x double> poison,671 <vscale x 8 x float> %0,672 float %1,673 iXLen 0, iXLen %2)674 675 ret <vscale x 8 x double> %a676}677 678define <vscale x 8 x double> @intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {679; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32:680; CHECK: # %bb.0: # %entry681; CHECK-NEXT: fsrmi a1, 0682; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu683; CHECK-NEXT: vfwadd.vf v8, v16, fa0, v0.t684; CHECK-NEXT: fsrm a1685; CHECK-NEXT: ret686entry:687 %a = call <vscale x 8 x double> @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32(688 <vscale x 8 x double> %0,689 <vscale x 8 x float> %1,690 float %2,691 <vscale x 8 x i1> %3,692 iXLen 0, iXLen %4, iXLen 1)693 694 ret <vscale x 8 x double> %a695}696