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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin \7; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s8; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin \9; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s10 11define <vscale x 1 x float> @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {12; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma15; CHECK-NEXT: vfwcvt.f.f.v v9, v816; CHECK-NEXT: vmv1r.v v8, v917; CHECK-NEXT: ret18entry:19 %a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(20 <vscale x 1 x float> poison,21 <vscale x 1 x half> %0,22 iXLen %1)23 24 ret <vscale x 1 x float> %a25}26 27define <vscale x 1 x float> @intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {28; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16:29; CHECK: # %bb.0: # %entry30; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu31; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t32; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16(35 <vscale x 1 x float> %0,36 <vscale x 1 x half> %1,37 <vscale x 1 x i1> %2,38 iXLen %3, iXLen 1)39 40 ret <vscale x 1 x float> %a41}42 43define <vscale x 2 x float> @intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {44; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma47; CHECK-NEXT: vfwcvt.f.f.v v9, v848; CHECK-NEXT: vmv1r.v v8, v949; CHECK-NEXT: ret50entry:51 %a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16(52 <vscale x 2 x float> poison,53 <vscale x 2 x half> %0,54 iXLen %1)55 56 ret <vscale x 2 x float> %a57}58 59define <vscale x 2 x float> @intrinsic_vfwcvt_mask_f.f.v_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {60; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f32_nxv2f16:61; CHECK: # %bb.0: # %entry62; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu63; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t64; CHECK-NEXT: ret65entry:66 %a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16(67 <vscale x 2 x float> %0,68 <vscale x 2 x half> %1,69 <vscale x 2 x i1> %2,70 iXLen %3, iXLen 1)71 72 ret <vscale x 2 x float> %a73}74 75define <vscale x 4 x float> @intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {76; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma79; CHECK-NEXT: vmv1r.v v10, v880; CHECK-NEXT: vfwcvt.f.f.v v8, v1081; CHECK-NEXT: ret82entry:83 %a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16(84 <vscale x 4 x float> poison,85 <vscale x 4 x half> %0,86 iXLen %1)87 88 ret <vscale x 4 x float> %a89}90 91define <vscale x 4 x float> @intrinsic_vfwcvt_mask_f.f.v_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {92; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f32_nxv4f16:93; CHECK: # %bb.0: # %entry94; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu95; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t96; CHECK-NEXT: ret97entry:98 %a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f32.nxv4f16(99 <vscale x 4 x float> %0,100 <vscale x 4 x half> %1,101 <vscale x 4 x i1> %2,102 iXLen %3, iXLen 1)103 104 ret <vscale x 4 x float> %a105}106 107define <vscale x 8 x float> @intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {108; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16:109; CHECK: # %bb.0: # %entry110; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma111; CHECK-NEXT: vmv2r.v v12, v8112; CHECK-NEXT: vfwcvt.f.f.v v8, v12113; CHECK-NEXT: ret114entry:115 %a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16(116 <vscale x 8 x float> poison,117 <vscale x 8 x half> %0,118 iXLen %1)119 120 ret <vscale x 8 x float> %a121}122 123define <vscale x 8 x float> @intrinsic_vfwcvt_mask_f.f.v_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {124; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f32_nxv8f16:125; CHECK: # %bb.0: # %entry126; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu127; CHECK-NEXT: vfwcvt.f.f.v v8, v12, v0.t128; CHECK-NEXT: ret129entry:130 %a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f32.nxv8f16(131 <vscale x 8 x float> %0,132 <vscale x 8 x half> %1,133 <vscale x 8 x i1> %2,134 iXLen %3, iXLen 1)135 136 ret <vscale x 8 x float> %a137}138 139define <vscale x 16 x float> @intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {140; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma143; CHECK-NEXT: vmv4r.v v16, v8144; CHECK-NEXT: vfwcvt.f.f.v v8, v16145; CHECK-NEXT: ret146entry:147 %a = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16(148 <vscale x 16 x float> poison,149 <vscale x 16 x half> %0,150 iXLen %1)151 152 ret <vscale x 16 x float> %a153}154 155define <vscale x 16 x float> @intrinsic_vfwcvt_mask_f.f.v_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {156; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv16f32_nxv16f16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu159; CHECK-NEXT: vfwcvt.f.f.v v8, v16, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv16f32.nxv16f16(163 <vscale x 16 x float> %0,164 <vscale x 16 x half> %1,165 <vscale x 16 x i1> %2,166 iXLen %3, iXLen 1)167 168 ret <vscale x 16 x float> %a169}170 171define <vscale x 1 x double> @intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {172; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32:173; CHECK: # %bb.0: # %entry174; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma175; CHECK-NEXT: vfwcvt.f.f.v v9, v8176; CHECK-NEXT: vmv1r.v v8, v9177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32(180 <vscale x 1 x double> poison,181 <vscale x 1 x float> %0,182 iXLen %1)183 184 ret <vscale x 1 x double> %a185}186 187define <vscale x 1 x double> @intrinsic_vfwcvt_mask_f.f.v_nxv1f64_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {188; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f64_nxv1f32:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu191; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t192; CHECK-NEXT: ret193entry:194 %a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f64.nxv1f32(195 <vscale x 1 x double> %0,196 <vscale x 1 x float> %1,197 <vscale x 1 x i1> %2,198 iXLen %3, iXLen 1)199 200 ret <vscale x 1 x double> %a201}202 203define <vscale x 2 x double> @intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {204; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32:205; CHECK: # %bb.0: # %entry206; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma207; CHECK-NEXT: vmv1r.v v10, v8208; CHECK-NEXT: vfwcvt.f.f.v v8, v10209; CHECK-NEXT: ret210entry:211 %a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32(212 <vscale x 2 x double> poison,213 <vscale x 2 x float> %0,214 iXLen %1)215 216 ret <vscale x 2 x double> %a217}218 219define <vscale x 2 x double> @intrinsic_vfwcvt_mask_f.f.v_nxv2f64_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {220; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f64_nxv2f32:221; CHECK: # %bb.0: # %entry222; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu223; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t224; CHECK-NEXT: ret225entry:226 %a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32(227 <vscale x 2 x double> %0,228 <vscale x 2 x float> %1,229 <vscale x 2 x i1> %2,230 iXLen %3, iXLen 1)231 232 ret <vscale x 2 x double> %a233}234 235define <vscale x 4 x double> @intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {236; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32:237; CHECK: # %bb.0: # %entry238; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma239; CHECK-NEXT: vmv2r.v v12, v8240; CHECK-NEXT: vfwcvt.f.f.v v8, v12241; CHECK-NEXT: ret242entry:243 %a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32(244 <vscale x 4 x double> poison,245 <vscale x 4 x float> %0,246 iXLen %1)247 248 ret <vscale x 4 x double> %a249}250 251define <vscale x 4 x double> @intrinsic_vfwcvt_mask_f.f.v_nxv4f64_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {252; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f64_nxv4f32:253; CHECK: # %bb.0: # %entry254; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu255; CHECK-NEXT: vfwcvt.f.f.v v8, v12, v0.t256; CHECK-NEXT: ret257entry:258 %a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32(259 <vscale x 4 x double> %0,260 <vscale x 4 x float> %1,261 <vscale x 4 x i1> %2,262 iXLen %3, iXLen 1)263 264 ret <vscale x 4 x double> %a265}266 267define <vscale x 8 x double> @intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {268; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32:269; CHECK: # %bb.0: # %entry270; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma271; CHECK-NEXT: vmv4r.v v16, v8272; CHECK-NEXT: vfwcvt.f.f.v v8, v16273; CHECK-NEXT: ret274entry:275 %a = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32(276 <vscale x 8 x double> poison,277 <vscale x 8 x float> %0,278 iXLen %1)279 280 ret <vscale x 8 x double> %a281}282 283define <vscale x 8 x double> @intrinsic_vfwcvt_mask_f.f.v_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {284; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f64_nxv8f32:285; CHECK: # %bb.0: # %entry286; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu287; CHECK-NEXT: vfwcvt.f.f.v v8, v16, v0.t288; CHECK-NEXT: ret289entry:290 %a = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f64.nxv8f32(291 <vscale x 8 x double> %0,292 <vscale x 8 x float> %1,293 <vscale x 8 x i1> %2,294 iXLen %3, iXLen 1)295 296 ret <vscale x 8 x double> %a297}298