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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfbfmin,+zvfbfwma\3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfbfmin,+zvfbfwma \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x float> @intrinsic_vfwmaccbf16_vv_nxv1f32_nxv1bf16_nxv1bf16(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vfwmaccbf16_vv_nxv1f32_nxv1bf16_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma11; CHECK-NEXT: vfwmaccbf16.vv v8, v9, v1012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16(15 <vscale x 1 x float> %0,16 <vscale x 1 x bfloat> %1,17 <vscale x 1 x bfloat> %2,18 iXLen 7, iXLen %3, iXLen 0)19 20 ret <vscale x 1 x float> %a21}22 23define <vscale x 1 x float> @intrinsic_vfwmaccbf16_mask_vv_nxv1f32_nxv1bf16_nxv1bf16(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vfwmaccbf16_mask_vv_nxv1f32_nxv1bf16_nxv1bf16:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu27; CHECK-NEXT: vfwmaccbf16.vv v8, v9, v10, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.nxv1bf16(31 <vscale x 1 x float> %0,32 <vscale x 1 x bfloat> %1,33 <vscale x 1 x bfloat> %2,34 <vscale x 1 x i1> %3,35 iXLen 7, iXLen %4, iXLen 0)36 37 ret <vscale x 1 x float> %a38}39 40define <vscale x 2 x float> @intrinsic_vfwmaccbf16_vv_nxv2f32_nxv2bf16_nxv2bf16(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {41; CHECK-LABEL: intrinsic_vfwmaccbf16_vv_nxv2f32_nxv2bf16_nxv2bf16:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma44; CHECK-NEXT: vfwmaccbf16.vv v8, v9, v1045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16(48 <vscale x 2 x float> %0,49 <vscale x 2 x bfloat> %1,50 <vscale x 2 x bfloat> %2,51 iXLen 7, iXLen %3, iXLen 0)52 53 ret <vscale x 2 x float> %a54}55 56define <vscale x 2 x float> @intrinsic_vfwmaccbf16_mask_vv_nxv2f32_nxv2bf16_nxv2bf16(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vfwmaccbf16_mask_vv_nxv2f32_nxv2bf16_nxv2bf16:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu60; CHECK-NEXT: vfwmaccbf16.vv v8, v9, v10, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.nxv2bf16(64 <vscale x 2 x float> %0,65 <vscale x 2 x bfloat> %1,66 <vscale x 2 x bfloat> %2,67 <vscale x 2 x i1> %3,68 iXLen 7, iXLen %4, iXLen 0)69 70 ret <vscale x 2 x float> %a71}72 73define <vscale x 4 x float> @intrinsic_vfwmaccbf16_vv_nxv4f32_nxv4bf16_nxv4bf16(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, iXLen %3) nounwind {74; CHECK-LABEL: intrinsic_vfwmaccbf16_vv_nxv4f32_nxv4bf16_nxv4bf16:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma77; CHECK-NEXT: vfwmaccbf16.vv v8, v10, v1178; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16(81 <vscale x 4 x float> %0,82 <vscale x 4 x bfloat> %1,83 <vscale x 4 x bfloat> %2,84 iXLen 7, iXLen %3, iXLen 0)85 86 ret <vscale x 4 x float> %a87}88 89define <vscale x 4 x float> @intrinsic_vfwmaccbf16_mask_vv_nxv4f32_nxv4bf16_nxv4bf16(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vfwmaccbf16_mask_vv_nxv4f32_nxv4bf16_nxv4bf16:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu93; CHECK-NEXT: vfwmaccbf16.vv v8, v10, v11, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.nxv4bf16(97 <vscale x 4 x float> %0,98 <vscale x 4 x bfloat> %1,99 <vscale x 4 x bfloat> %2,100 <vscale x 4 x i1> %3,101 iXLen 7, iXLen %4, iXLen 0)102 103 ret <vscale x 4 x float> %a104}105 106define <vscale x 8 x float> @intrinsic_vfwmaccbf16_vv_nxv8f32_nxv8bf16_nxv8bf16(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {107; CHECK-LABEL: intrinsic_vfwmaccbf16_vv_nxv8f32_nxv8bf16_nxv8bf16:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma110; CHECK-NEXT: vfwmaccbf16.vv v8, v12, v14111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16(114 <vscale x 8 x float> %0,115 <vscale x 8 x bfloat> %1,116 <vscale x 8 x bfloat> %2,117 iXLen 7, iXLen %3, iXLen 0)118 119 ret <vscale x 8 x float> %a120}121 122define <vscale x 8 x float> @intrinsic_vfwmaccbf16_mask_vv_nxv8f32_nxv8bf16_nxv8bf16(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vfwmaccbf16_mask_vv_nxv8f32_nxv8bf16_nxv8bf16:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu126; CHECK-NEXT: vfwmaccbf16.vv v8, v12, v14, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.nxv8bf16(130 <vscale x 8 x float> %0,131 <vscale x 8 x bfloat> %1,132 <vscale x 8 x bfloat> %2,133 <vscale x 8 x i1> %3,134 iXLen 7, iXLen %4, iXLen 0)135 136 ret <vscale x 8 x float> %a137}138 139define <vscale x 16 x float> @intrinsic_vfwmaccbf16_vv_nxv16f32_nxv16bf16_nxv16bf16(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {140; CHECK-LABEL: intrinsic_vfwmaccbf16_vv_nxv16f32_nxv16bf16_nxv16bf16:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma143; CHECK-NEXT: vfwmaccbf16.vv v8, v16, v20144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.nxv16f32.nxv16bf16(147 <vscale x 16 x float> %0,148 <vscale x 16 x bfloat> %1,149 <vscale x 16 x bfloat> %2,150 iXLen 7, iXLen %3, iXLen 0)151 152 ret <vscale x 16 x float> %a153}154 155define <vscale x 16 x float> @intrinsic_vfwmaccbf16_mask_vv_nxv16f32_nxv16bf16_nxv16bf16(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vfwmaccbf16_mask_vv_nxv16f32_nxv16bf16_nxv16bf16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu159; CHECK-NEXT: vfwmaccbf16.vv v8, v16, v20, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.nxv16bf16(163 <vscale x 16 x float> %0,164 <vscale x 16 x bfloat> %1,165 <vscale x 16 x bfloat> %2,166 <vscale x 16 x i1> %3,167 iXLen 7, iXLen %4, iXLen 0)168 169 ret <vscale x 16 x float> %a170}171 172define <vscale x 1 x float> @intrinsic_vfwmaccbf16_vf_nxv1f32_bf16_nxv1bf16(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {173; CHECK-LABEL: intrinsic_vfwmaccbf16_vf_nxv1f32_bf16_nxv1bf16:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma176; CHECK-NEXT: vfwmaccbf16.vf v8, fa0, v9177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.nxv1f32.bf16(180 <vscale x 1 x float> %0,181 bfloat %1,182 <vscale x 1 x bfloat> %2,183 iXLen 7, iXLen %3, iXLen 0)184 185 ret <vscale x 1 x float> %a186}187 188define <vscale x 1 x float> @intrinsic_vfwmaccbf16_mask_vf_nxv1f32_bf16_nxv1bf16(<vscale x 1 x float> %0, bfloat %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vfwmaccbf16_mask_vf_nxv1f32_bf16_nxv1bf16:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu192; CHECK-NEXT: vfwmaccbf16.vf v8, fa0, v9, v0.t193; CHECK-NEXT: ret194entry:195 %a = call <vscale x 1 x float> @llvm.riscv.vfwmaccbf16.mask.nxv1f32.bf16(196 <vscale x 1 x float> %0,197 bfloat %1,198 <vscale x 1 x bfloat> %2,199 <vscale x 1 x i1> %3,200 iXLen 7, iXLen %4, iXLen 0)201 202 ret <vscale x 1 x float> %a203}204 205define <vscale x 2 x float> @intrinsic_vfwmaccbf16_vf_nxv2f32_bf16_nxv2bf16(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {206; CHECK-LABEL: intrinsic_vfwmaccbf16_vf_nxv2f32_bf16_nxv2bf16:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma209; CHECK-NEXT: vfwmaccbf16.vf v8, fa0, v9210; CHECK-NEXT: ret211entry:212 %a = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.nxv2f32.bf16(213 <vscale x 2 x float> %0,214 bfloat %1,215 <vscale x 2 x bfloat> %2,216 iXLen 7, iXLen %3, iXLen 0)217 218 ret <vscale x 2 x float> %a219}220 221define <vscale x 2 x float> @intrinsic_vfwmaccbf16_mask_vf_nxv2f32_bf16_nxv2bf16(<vscale x 2 x float> %0, bfloat %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vfwmaccbf16_mask_vf_nxv2f32_bf16_nxv2bf16:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu225; CHECK-NEXT: vfwmaccbf16.vf v8, fa0, v9, v0.t226; CHECK-NEXT: ret227entry:228 %a = call <vscale x 2 x float> @llvm.riscv.vfwmaccbf16.mask.nxv2f32.bf16(229 <vscale x 2 x float> %0,230 bfloat %1,231 <vscale x 2 x bfloat> %2,232 <vscale x 2 x i1> %3,233 iXLen 7, iXLen %4, iXLen 0)234 235 ret <vscale x 2 x float> %a236}237 238define <vscale x 4 x float> @intrinsic_vfwmaccbf16_vf_nxv4f32_bf16_nxv4bf16(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, iXLen %3) nounwind {239; CHECK-LABEL: intrinsic_vfwmaccbf16_vf_nxv4f32_bf16_nxv4bf16:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma242; CHECK-NEXT: vfwmaccbf16.vf v8, fa0, v10243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.nxv4f32.bf16(246 <vscale x 4 x float> %0,247 bfloat %1,248 <vscale x 4 x bfloat> %2,249 iXLen 7, iXLen %3, iXLen 0)250 251 ret <vscale x 4 x float> %a252}253 254define <vscale x 4 x float> @intrinsic_vfwmaccbf16_mask_vf_nxv4f32_bf16_nxv4bf16(<vscale x 4 x float> %0, bfloat %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {255; CHECK-LABEL: intrinsic_vfwmaccbf16_mask_vf_nxv4f32_bf16_nxv4bf16:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu258; CHECK-NEXT: vfwmaccbf16.vf v8, fa0, v10, v0.t259; CHECK-NEXT: ret260entry:261 %a = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16.mask.nxv4f32.bf16(262 <vscale x 4 x float> %0,263 bfloat %1,264 <vscale x 4 x bfloat> %2,265 <vscale x 4 x i1> %3,266 iXLen 7, iXLen %4, iXLen 0)267 268 ret <vscale x 4 x float> %a269}270 271define <vscale x 8 x float> @intrinsic_vfwmaccbf16_vf_nxv8f32_bf16_nxv8bf16(<vscale x 8 x float> %0, bfloat %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {272; CHECK-LABEL: intrinsic_vfwmaccbf16_vf_nxv8f32_bf16_nxv8bf16:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma275; CHECK-NEXT: vfwmaccbf16.vf v8, fa0, v12276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.nxv8f32.bf16(279 <vscale x 8 x float> %0,280 bfloat %1,281 <vscale x 8 x bfloat> %2,282 iXLen 7, iXLen %3, iXLen 0)283 284 ret <vscale x 8 x float> %a285}286 287define <vscale x 8 x float> @intrinsic_vfwmaccbf16_mask_vf_nxv8f32_bf16_nxv8bf16(<vscale x 8 x float> %0, bfloat %1, <vscale x 8 x bfloat> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {288; CHECK-LABEL: intrinsic_vfwmaccbf16_mask_vf_nxv8f32_bf16_nxv8bf16:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu291; CHECK-NEXT: vfwmaccbf16.vf v8, fa0, v12, v0.t292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 8 x float> @llvm.riscv.vfwmaccbf16.mask.nxv8f32.bf16(295 <vscale x 8 x float> %0,296 bfloat %1,297 <vscale x 8 x bfloat> %2,298 <vscale x 8 x i1> %3,299 iXLen 7, iXLen %4, iXLen 0)300 301 ret <vscale x 8 x float> %a302}303 304define <vscale x 16 x float> @intrinsic_vfwmaccbf16_vf_nxv16f32_bf16_nxv16bf16(<vscale x 16 x float> %0, bfloat %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {305; CHECK-LABEL: intrinsic_vfwmaccbf16_vf_nxv16f32_bf16_nxv16bf16:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma308; CHECK-NEXT: vfwmaccbf16.vf v8, fa0, v16309; CHECK-NEXT: ret310entry:311 %a = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.nxv16f32.bf16(312 <vscale x 16 x float> %0,313 bfloat %1,314 <vscale x 16 x bfloat> %2,315 iXLen 7, iXLen %3, iXLen 0)316 317 ret <vscale x 16 x float> %a318}319 320define <vscale x 16 x float> @intrinsic_vfwmaccbf16_mask_vf_nxv16f32_bf16_nxv16bf16(<vscale x 16 x float> %0, bfloat %1, <vscale x 16 x bfloat> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {321; CHECK-LABEL: intrinsic_vfwmaccbf16_mask_vf_nxv16f32_bf16_nxv16bf16:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu324; CHECK-NEXT: vfwmaccbf16.vf v8, fa0, v16, v0.t325; CHECK-NEXT: ret326entry:327 %a = call <vscale x 16 x float> @llvm.riscv.vfwmaccbf16.mask.nxv16f32.bf16(328 <vscale x 16 x float> %0,329 bfloat %1,330 <vscale x 16 x bfloat> %2,331 <vscale x 16 x i1> %3,332 iXLen 7, iXLen %4, iXLen 0)333 334 ret <vscale x 16 x float> %a335}336