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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x float> @intrinsic_vfwsub_vv_nxv1f32_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1bf16_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma12; CHECK-NEXT: vfwsub.vv v10, v8, v913; CHECK-NEXT: fsrm a114; CHECK-NEXT: vmv1r.v v8, v1015; CHECK-NEXT: ret16entry:17 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16(18 <vscale x 1 x float> poison,19 <vscale x 1 x bfloat> %0,20 <vscale x 1 x bfloat> %1,21 iXLen 0, iXLen %2)22 23 ret <vscale x 1 x float> %a24}25 26define <vscale x 1 x float> @intrinsic_vfwsub_mask_vv_nxv1f32_nxv1bf16_nxv1bf16(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {27; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f32_nxv1bf16_nxv1bf16:28; CHECK: # %bb.0: # %entry29; CHECK-NEXT: fsrmi a1, 030; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu31; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t32; CHECK-NEXT: fsrm a133; CHECK-NEXT: ret34entry:35 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f32.nxv1bf16.nxv1bf16(36 <vscale x 1 x float> %0,37 <vscale x 1 x bfloat> %1,38 <vscale x 1 x bfloat> %2,39 <vscale x 1 x i1> %3,40 iXLen 0, iXLen %4, iXLen 1)41 42 ret <vscale x 1 x float> %a43}44 45define <vscale x 2 x float> @intrinsic_vfwsub_vv_nxv2f32_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, iXLen %2) nounwind {46; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f32_nxv2bf16_nxv2bf16:47; CHECK: # %bb.0: # %entry48; CHECK-NEXT: fsrmi a1, 049; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma50; CHECK-NEXT: vfwsub.vv v10, v8, v951; CHECK-NEXT: fsrm a152; CHECK-NEXT: vmv1r.v v8, v1053; CHECK-NEXT: ret54entry:55 %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16(56 <vscale x 2 x float> poison,57 <vscale x 2 x bfloat> %0,58 <vscale x 2 x bfloat> %1,59 iXLen 0, iXLen %2)60 61 ret <vscale x 2 x float> %a62}63 64define <vscale x 2 x float> @intrinsic_vfwsub_mask_vv_nxv2f32_nxv2bf16_nxv2bf16(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {65; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f32_nxv2bf16_nxv2bf16:66; CHECK: # %bb.0: # %entry67; CHECK-NEXT: fsrmi a1, 068; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu69; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t70; CHECK-NEXT: fsrm a171; CHECK-NEXT: ret72entry:73 %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f32.nxv2bf16.nxv2bf16(74 <vscale x 2 x float> %0,75 <vscale x 2 x bfloat> %1,76 <vscale x 2 x bfloat> %2,77 <vscale x 2 x i1> %3,78 iXLen 0, iXLen %4, iXLen 1)79 80 ret <vscale x 2 x float> %a81}82 83define <vscale x 4 x float> @intrinsic_vfwsub_vv_nxv4f32_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, iXLen %2) nounwind {84; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f32_nxv4bf16_nxv4bf16:85; CHECK: # %bb.0: # %entry86; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma87; CHECK-NEXT: vmv1r.v v10, v988; CHECK-NEXT: vmv1r.v v11, v889; CHECK-NEXT: fsrmi a0, 090; CHECK-NEXT: vfwsub.vv v8, v11, v1091; CHECK-NEXT: fsrm a092; CHECK-NEXT: ret93entry:94 %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16(95 <vscale x 4 x float> poison,96 <vscale x 4 x bfloat> %0,97 <vscale x 4 x bfloat> %1,98 iXLen 0, iXLen %2)99 100 ret <vscale x 4 x float> %a101}102 103define <vscale x 4 x float> @intrinsic_vfwsub_mask_vv_nxv4f32_nxv4bf16_nxv4bf16(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {104; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f32_nxv4bf16_nxv4bf16:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: fsrmi a1, 0107; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu108; CHECK-NEXT: vfwsub.vv v8, v10, v11, v0.t109; CHECK-NEXT: fsrm a1110; CHECK-NEXT: ret111entry:112 %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f32.nxv4bf16.nxv4bf16(113 <vscale x 4 x float> %0,114 <vscale x 4 x bfloat> %1,115 <vscale x 4 x bfloat> %2,116 <vscale x 4 x i1> %3,117 iXLen 0, iXLen %4, iXLen 1)118 119 ret <vscale x 4 x float> %a120}121 122define <vscale x 8 x float> @intrinsic_vfwsub_vv_nxv8f32_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, iXLen %2) nounwind {123; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f32_nxv8bf16_nxv8bf16:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma126; CHECK-NEXT: vmv2r.v v12, v10127; CHECK-NEXT: vmv2r.v v14, v8128; CHECK-NEXT: fsrmi a0, 0129; CHECK-NEXT: vfwsub.vv v8, v14, v12130; CHECK-NEXT: fsrm a0131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f32.nxv8bf16.nxv8bf16(134 <vscale x 8 x float> poison,135 <vscale x 8 x bfloat> %0,136 <vscale x 8 x bfloat> %1,137 iXLen 0, iXLen %2)138 139 ret <vscale x 8 x float> %a140}141 142define <vscale x 8 x float> @intrinsic_vfwsub_mask_vv_nxv8f32_nxv8bf16_nxv8bf16(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {143; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f32_nxv8bf16_nxv8bf16:144; CHECK: # %bb.0: # %entry145; CHECK-NEXT: fsrmi a1, 0146; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu147; CHECK-NEXT: vfwsub.vv v8, v12, v14, v0.t148; CHECK-NEXT: fsrm a1149; CHECK-NEXT: ret150entry:151 %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f32.nxv8bf16.nxv8bf16(152 <vscale x 8 x float> %0,153 <vscale x 8 x bfloat> %1,154 <vscale x 8 x bfloat> %2,155 <vscale x 8 x i1> %3,156 iXLen 0, iXLen %4, iXLen 1)157 158 ret <vscale x 8 x float> %a159}160 161define <vscale x 16 x float> @intrinsic_vfwsub_vv_nxv16f32_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, iXLen %2) nounwind {162; CHECK-LABEL: intrinsic_vfwsub_vv_nxv16f32_nxv16bf16_nxv16bf16:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma165; CHECK-NEXT: vmv4r.v v16, v12166; CHECK-NEXT: vmv4r.v v20, v8167; CHECK-NEXT: fsrmi a0, 0168; CHECK-NEXT: vfwsub.vv v8, v20, v16169; CHECK-NEXT: fsrm a0170; CHECK-NEXT: ret171entry:172 %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f32.nxv16bf16.nxv16bf16(173 <vscale x 16 x float> poison,174 <vscale x 16 x bfloat> %0,175 <vscale x 16 x bfloat> %1,176 iXLen 0, iXLen %2)177 178 ret <vscale x 16 x float> %a179}180 181define <vscale x 16 x float> @intrinsic_vfwsub_mask_vv_nxv16f32_nxv16bf16_nxv16bf16(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {182; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv16f32_nxv16bf16_nxv16bf16:183; CHECK: # %bb.0: # %entry184; CHECK-NEXT: fsrmi a1, 0185; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu186; CHECK-NEXT: vfwsub.vv v8, v16, v20, v0.t187; CHECK-NEXT: fsrm a1188; CHECK-NEXT: ret189entry:190 %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f32.nxv16bf16.nxv16bf16(191 <vscale x 16 x float> %0,192 <vscale x 16 x bfloat> %1,193 <vscale x 16 x bfloat> %2,194 <vscale x 16 x i1> %3,195 iXLen 0, iXLen %4, iXLen 1)196 197 ret <vscale x 16 x float> %a198}199 200define <vscale x 1 x float> @intrinsic_vfwsub_vf_nxv1f32_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, bfloat %1, iXLen %2) nounwind {201; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f32_nxv1bf16_bf16:202; CHECK: # %bb.0: # %entry203; CHECK-NEXT: fsrmi a1, 0204; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma205; CHECK-NEXT: vfwsub.vf v9, v8, fa0206; CHECK-NEXT: fsrm a1207; CHECK-NEXT: vmv1r.v v8, v9208; CHECK-NEXT: ret209entry:210 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16(211 <vscale x 1 x float> poison,212 <vscale x 1 x bfloat> %0,213 bfloat %1,214 iXLen 0, iXLen %2)215 216 ret <vscale x 1 x float> %a217}218 219define <vscale x 1 x float> @intrinsic_vfwsub_mask_vf_nxv1f32_nxv1bf16_bf16(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {220; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f32_nxv1bf16_bf16:221; CHECK: # %bb.0: # %entry222; CHECK-NEXT: fsrmi a1, 0223; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu224; CHECK-NEXT: vfwsub.vf v8, v9, fa0, v0.t225; CHECK-NEXT: fsrm a1226; CHECK-NEXT: ret227entry:228 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f32.nxv1bf16.bf16(229 <vscale x 1 x float> %0,230 <vscale x 1 x bfloat> %1,231 bfloat %2,232 <vscale x 1 x i1> %3,233 iXLen 0, iXLen %4, iXLen 1)234 235 ret <vscale x 1 x float> %a236}237 238define <vscale x 2 x float> @intrinsic_vfwsub_vf_nxv2f32_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, bfloat %1, iXLen %2) nounwind {239; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f32_nxv2bf16_bf16:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: fsrmi a1, 0242; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma243; CHECK-NEXT: vfwsub.vf v9, v8, fa0244; CHECK-NEXT: fsrm a1245; CHECK-NEXT: vmv1r.v v8, v9246; CHECK-NEXT: ret247entry:248 %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16(249 <vscale x 2 x float> poison,250 <vscale x 2 x bfloat> %0,251 bfloat %1,252 iXLen 0, iXLen %2)253 254 ret <vscale x 2 x float> %a255}256 257define <vscale x 2 x float> @intrinsic_vfwsub_mask_vf_nxv2f32_nxv2bf16_bf16(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {258; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f32_nxv2bf16_bf16:259; CHECK: # %bb.0: # %entry260; CHECK-NEXT: fsrmi a1, 0261; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu262; CHECK-NEXT: vfwsub.vf v8, v9, fa0, v0.t263; CHECK-NEXT: fsrm a1264; CHECK-NEXT: ret265entry:266 %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f32.nxv2bf16.bf16(267 <vscale x 2 x float> %0,268 <vscale x 2 x bfloat> %1,269 bfloat %2,270 <vscale x 2 x i1> %3,271 iXLen 0, iXLen %4, iXLen 1)272 273 ret <vscale x 2 x float> %a274}275 276define <vscale x 4 x float> @intrinsic_vfwsub_vf_nxv4f32_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, bfloat %1, iXLen %2) nounwind {277; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f32_nxv4bf16_bf16:278; CHECK: # %bb.0: # %entry279; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma280; CHECK-NEXT: vmv1r.v v10, v8281; CHECK-NEXT: fsrmi a0, 0282; CHECK-NEXT: vfwsub.vf v8, v10, fa0283; CHECK-NEXT: fsrm a0284; CHECK-NEXT: ret285entry:286 %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.bf16(287 <vscale x 4 x float> poison,288 <vscale x 4 x bfloat> %0,289 bfloat %1,290 iXLen 0, iXLen %2)291 292 ret <vscale x 4 x float> %a293}294 295define <vscale x 4 x float> @intrinsic_vfwsub_mask_vf_nxv4f32_nxv4bf16_bf16(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {296; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f32_nxv4bf16_bf16:297; CHECK: # %bb.0: # %entry298; CHECK-NEXT: fsrmi a1, 0299; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu300; CHECK-NEXT: vfwsub.vf v8, v10, fa0, v0.t301; CHECK-NEXT: fsrm a1302; CHECK-NEXT: ret303entry:304 %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f32.nxv4bf16.bf16(305 <vscale x 4 x float> %0,306 <vscale x 4 x bfloat> %1,307 bfloat %2,308 <vscale x 4 x i1> %3,309 iXLen 0, iXLen %4, iXLen 1)310 311 ret <vscale x 4 x float> %a312}313 314define <vscale x 8 x float> @intrinsic_vfwsub_vf_nxv8f32_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, bfloat %1, iXLen %2) nounwind {315; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f32_nxv8bf16_bf16:316; CHECK: # %bb.0: # %entry317; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma318; CHECK-NEXT: vmv2r.v v12, v8319; CHECK-NEXT: fsrmi a0, 0320; CHECK-NEXT: vfwsub.vf v8, v12, fa0321; CHECK-NEXT: fsrm a0322; CHECK-NEXT: ret323entry:324 %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f32.nxv8bf16.bf16(325 <vscale x 8 x float> poison,326 <vscale x 8 x bfloat> %0,327 bfloat %1,328 iXLen 0, iXLen %2)329 330 ret <vscale x 8 x float> %a331}332 333define <vscale x 8 x float> @intrinsic_vfwsub_mask_vf_nxv8f32_nxv8bf16_bf16(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {334; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f32_nxv8bf16_bf16:335; CHECK: # %bb.0: # %entry336; CHECK-NEXT: fsrmi a1, 0337; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu338; CHECK-NEXT: vfwsub.vf v8, v12, fa0, v0.t339; CHECK-NEXT: fsrm a1340; CHECK-NEXT: ret341entry:342 %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f32.nxv8bf16.bf16(343 <vscale x 8 x float> %0,344 <vscale x 8 x bfloat> %1,345 bfloat %2,346 <vscale x 8 x i1> %3,347 iXLen 0, iXLen %4, iXLen 1)348 349 ret <vscale x 8 x float> %a350}351 352define <vscale x 16 x float> @intrinsic_vfwsub_vf_nxv16f32_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, bfloat %1, iXLen %2) nounwind {353; CHECK-LABEL: intrinsic_vfwsub_vf_nxv16f32_nxv16bf16_bf16:354; CHECK: # %bb.0: # %entry355; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma356; CHECK-NEXT: vmv4r.v v16, v8357; CHECK-NEXT: fsrmi a0, 0358; CHECK-NEXT: vfwsub.vf v8, v16, fa0359; CHECK-NEXT: fsrm a0360; CHECK-NEXT: ret361entry:362 %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f32.nxv16bf16.bf16(363 <vscale x 16 x float> poison,364 <vscale x 16 x bfloat> %0,365 bfloat %1,366 iXLen 0, iXLen %2)367 368 ret <vscale x 16 x float> %a369}370 371define <vscale x 16 x float> @intrinsic_vfwsub_mask_vf_nxv16f32_nxv16bf16_bf16(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {372; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv16f32_nxv16bf16_bf16:373; CHECK: # %bb.0: # %entry374; CHECK-NEXT: fsrmi a1, 0375; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu376; CHECK-NEXT: vfwsub.vf v8, v16, fa0, v0.t377; CHECK-NEXT: fsrm a1378; CHECK-NEXT: ret379entry:380 %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f32.nxv16bf16.bf16(381 <vscale x 16 x float> %0,382 <vscale x 16 x bfloat> %1,383 bfloat %2,384 <vscale x 16 x i1> %3,385 iXLen 0, iXLen %4, iXLen 1)386 387 ret <vscale x 16 x float> %a388}389 390