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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma12; CHECK-NEXT: vfwsub.wv v8, v8, v913; CHECK-NEXT: fsrm a114; CHECK-NEXT: ret15entry:16 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16(17 <vscale x 1 x float> poison,18 <vscale x 1 x float> %0,19 <vscale x 1 x half> %1,20 iXLen 0, iXLen %2)21 22 ret <vscale x 1 x float> %a23}24 25define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {26; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: fsrmi a1, 029; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu30; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t31; CHECK-NEXT: fsrm a132; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.nxv1f16(35 <vscale x 1 x float> %0,36 <vscale x 1 x float> %1,37 <vscale x 1 x half> %2,38 <vscale x 1 x i1> %3,39 iXLen 0, iXLen %4, iXLen 1)40 41 ret <vscale x 1 x float> %a42}43 44define <vscale x 2 x float> @intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {45; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: fsrmi a1, 048; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma49; CHECK-NEXT: vfwsub.wv v8, v8, v950; CHECK-NEXT: fsrm a151; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16(54 <vscale x 2 x float> poison,55 <vscale x 2 x float> %0,56 <vscale x 2 x half> %1,57 iXLen 0, iXLen %2)58 59 ret <vscale x 2 x float> %a60}61 62define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {63; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: fsrmi a1, 066; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu67; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t68; CHECK-NEXT: fsrm a169; CHECK-NEXT: ret70entry:71 %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.nxv2f16(72 <vscale x 2 x float> %0,73 <vscale x 2 x float> %1,74 <vscale x 2 x half> %2,75 <vscale x 2 x i1> %3,76 iXLen 0, iXLen %4, iXLen 1)77 78 ret <vscale x 2 x float> %a79}80 81define <vscale x 4 x float> @intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {82; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: fsrmi a1, 085; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma86; CHECK-NEXT: vfwsub.wv v8, v8, v1087; CHECK-NEXT: fsrm a188; CHECK-NEXT: ret89entry:90 %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16(91 <vscale x 4 x float> poison,92 <vscale x 4 x float> %0,93 <vscale x 4 x half> %1,94 iXLen 0, iXLen %2)95 96 ret <vscale x 4 x float> %a97}98 99define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {100; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16:101; CHECK: # %bb.0: # %entry102; CHECK-NEXT: fsrmi a1, 0103; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu104; CHECK-NEXT: vfwsub.wv v8, v10, v12, v0.t105; CHECK-NEXT: fsrm a1106; CHECK-NEXT: ret107entry:108 %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.nxv4f16(109 <vscale x 4 x float> %0,110 <vscale x 4 x float> %1,111 <vscale x 4 x half> %2,112 <vscale x 4 x i1> %3,113 iXLen 0, iXLen %4, iXLen 1)114 115 ret <vscale x 4 x float> %a116}117 118define <vscale x 8 x float> @intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {119; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: fsrmi a1, 0122; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma123; CHECK-NEXT: vfwsub.wv v8, v8, v12124; CHECK-NEXT: fsrm a1125; CHECK-NEXT: ret126entry:127 %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16(128 <vscale x 8 x float> poison,129 <vscale x 8 x float> %0,130 <vscale x 8 x half> %1,131 iXLen 0, iXLen %2)132 133 ret <vscale x 8 x float> %a134}135 136define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {137; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16:138; CHECK: # %bb.0: # %entry139; CHECK-NEXT: fsrmi a1, 0140; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu141; CHECK-NEXT: vfwsub.wv v8, v12, v16, v0.t142; CHECK-NEXT: fsrm a1143; CHECK-NEXT: ret144entry:145 %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.nxv8f16(146 <vscale x 8 x float> %0,147 <vscale x 8 x float> %1,148 <vscale x 8 x half> %2,149 <vscale x 8 x i1> %3,150 iXLen 0, iXLen %4, iXLen 1)151 152 ret <vscale x 8 x float> %a153}154 155define <vscale x 16 x float> @intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {156; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: fsrmi a1, 0159; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma160; CHECK-NEXT: vfwsub.wv v8, v8, v16161; CHECK-NEXT: fsrm a1162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16(165 <vscale x 16 x float> poison,166 <vscale x 16 x float> %0,167 <vscale x 16 x half> %1,168 iXLen 0, iXLen %2)169 170 ret <vscale x 16 x float> %a171}172 173define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {174; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: vl4re16.v v24, (a0)177; CHECK-NEXT: fsrmi a0, 0178; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu179; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t180; CHECK-NEXT: fsrm a0181; CHECK-NEXT: ret182entry:183 %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16(184 <vscale x 16 x float> %0,185 <vscale x 16 x float> %1,186 <vscale x 16 x half> %2,187 <vscale x 16 x i1> %3,188 iXLen 0, iXLen %4, iXLen 1)189 190 ret <vscale x 16 x float> %a191}192 193define <vscale x 1 x double> @intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {194; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32:195; CHECK: # %bb.0: # %entry196; CHECK-NEXT: fsrmi a1, 0197; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma198; CHECK-NEXT: vfwsub.wv v8, v8, v9199; CHECK-NEXT: fsrm a1200; CHECK-NEXT: ret201entry:202 %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32(203 <vscale x 1 x double> poison,204 <vscale x 1 x double> %0,205 <vscale x 1 x float> %1,206 iXLen 0, iXLen %2)207 208 ret <vscale x 1 x double> %a209}210 211define <vscale x 1 x double> @intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {212; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32:213; CHECK: # %bb.0: # %entry214; CHECK-NEXT: fsrmi a1, 0215; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu216; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t217; CHECK-NEXT: fsrm a1218; CHECK-NEXT: ret219entry:220 %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.nxv1f32(221 <vscale x 1 x double> %0,222 <vscale x 1 x double> %1,223 <vscale x 1 x float> %2,224 <vscale x 1 x i1> %3,225 iXLen 0, iXLen %4, iXLen 1)226 227 ret <vscale x 1 x double> %a228}229 230define <vscale x 2 x double> @intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {231; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32:232; CHECK: # %bb.0: # %entry233; CHECK-NEXT: fsrmi a1, 0234; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma235; CHECK-NEXT: vfwsub.wv v8, v8, v10236; CHECK-NEXT: fsrm a1237; CHECK-NEXT: ret238entry:239 %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32(240 <vscale x 2 x double> poison,241 <vscale x 2 x double> %0,242 <vscale x 2 x float> %1,243 iXLen 0, iXLen %2)244 245 ret <vscale x 2 x double> %a246}247 248define <vscale x 2 x double> @intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {249; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32:250; CHECK: # %bb.0: # %entry251; CHECK-NEXT: fsrmi a1, 0252; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu253; CHECK-NEXT: vfwsub.wv v8, v10, v12, v0.t254; CHECK-NEXT: fsrm a1255; CHECK-NEXT: ret256entry:257 %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.nxv2f32(258 <vscale x 2 x double> %0,259 <vscale x 2 x double> %1,260 <vscale x 2 x float> %2,261 <vscale x 2 x i1> %3,262 iXLen 0, iXLen %4, iXLen 1)263 264 ret <vscale x 2 x double> %a265}266 267define <vscale x 4 x double> @intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {268; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32:269; CHECK: # %bb.0: # %entry270; CHECK-NEXT: fsrmi a1, 0271; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma272; CHECK-NEXT: vfwsub.wv v8, v8, v12273; CHECK-NEXT: fsrm a1274; CHECK-NEXT: ret275entry:276 %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32(277 <vscale x 4 x double> poison,278 <vscale x 4 x double> %0,279 <vscale x 4 x float> %1,280 iXLen 0, iXLen %2)281 282 ret <vscale x 4 x double> %a283}284 285define <vscale x 4 x double> @intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {286; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32:287; CHECK: # %bb.0: # %entry288; CHECK-NEXT: fsrmi a1, 0289; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu290; CHECK-NEXT: vfwsub.wv v8, v12, v16, v0.t291; CHECK-NEXT: fsrm a1292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.nxv4f32(295 <vscale x 4 x double> %0,296 <vscale x 4 x double> %1,297 <vscale x 4 x float> %2,298 <vscale x 4 x i1> %3,299 iXLen 0, iXLen %4, iXLen 1)300 301 ret <vscale x 4 x double> %a302}303 304define <vscale x 8 x double> @intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {305; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: fsrmi a1, 0308; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma309; CHECK-NEXT: vfwsub.wv v8, v8, v16310; CHECK-NEXT: fsrm a1311; CHECK-NEXT: ret312entry:313 %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.nxv8f32(314 <vscale x 8 x double> poison,315 <vscale x 8 x double> %0,316 <vscale x 8 x float> %1,317 iXLen 0, iXLen %2)318 319 ret <vscale x 8 x double> %a320}321 322define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {323; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: vl4re32.v v24, (a0)326; CHECK-NEXT: fsrmi a0, 0327; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu328; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t329; CHECK-NEXT: fsrm a0330; CHECK-NEXT: ret331entry:332 %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32(333 <vscale x 8 x double> %0,334 <vscale x 8 x double> %1,335 <vscale x 8 x float> %2,336 <vscale x 8 x i1> %3,337 iXLen 0, iXLen %4, iXLen 1)338 339 ret <vscale x 8 x double> %a340}341 342define <vscale x 1 x float> @intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, iXLen %2) nounwind {343; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16:344; CHECK: # %bb.0: # %entry345; CHECK-NEXT: fsrmi a1, 0346; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma347; CHECK-NEXT: vfwsub.wf v8, v8, fa0348; CHECK-NEXT: fsrm a1349; CHECK-NEXT: ret350entry:351 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16(352 <vscale x 1 x float> poison,353 <vscale x 1 x float> %0,354 half %1,355 iXLen 0, iXLen %2)356 357 ret <vscale x 1 x float> %a358}359 360define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {361; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16:362; CHECK: # %bb.0: # %entry363; CHECK-NEXT: fsrmi a1, 0364; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu365; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t366; CHECK-NEXT: fsrm a1367; CHECK-NEXT: ret368entry:369 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16(370 <vscale x 1 x float> %0,371 <vscale x 1 x float> %1,372 half %2,373 <vscale x 1 x i1> %3,374 iXLen 0, iXLen %4, iXLen 1)375 376 ret <vscale x 1 x float> %a377}378 379define <vscale x 2 x float> @intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, iXLen %2) nounwind {380; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16:381; CHECK: # %bb.0: # %entry382; CHECK-NEXT: fsrmi a1, 0383; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma384; CHECK-NEXT: vfwsub.wf v8, v8, fa0385; CHECK-NEXT: fsrm a1386; CHECK-NEXT: ret387entry:388 %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16(389 <vscale x 2 x float> poison,390 <vscale x 2 x float> %0,391 half %1,392 iXLen 0, iXLen %2)393 394 ret <vscale x 2 x float> %a395}396 397define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, <vscale x 2 x float> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {398; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16:399; CHECK: # %bb.0: # %entry400; CHECK-NEXT: fsrmi a1, 0401; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu402; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t403; CHECK-NEXT: fsrm a1404; CHECK-NEXT: ret405entry:406 %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16(407 <vscale x 2 x float> %0,408 <vscale x 2 x float> %1,409 half %2,410 <vscale x 2 x i1> %3,411 iXLen 0, iXLen %4, iXLen 1)412 413 ret <vscale x 2 x float> %a414}415 416define <vscale x 4 x float> @intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, iXLen %2) nounwind {417; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16:418; CHECK: # %bb.0: # %entry419; CHECK-NEXT: fsrmi a1, 0420; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma421; CHECK-NEXT: vfwsub.wf v8, v8, fa0422; CHECK-NEXT: fsrm a1423; CHECK-NEXT: ret424entry:425 %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16(426 <vscale x 4 x float> poison,427 <vscale x 4 x float> %0,428 half %1,429 iXLen 0, iXLen %2)430 431 ret <vscale x 4 x float> %a432}433 434define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, <vscale x 4 x float> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {435; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16:436; CHECK: # %bb.0: # %entry437; CHECK-NEXT: fsrmi a1, 0438; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu439; CHECK-NEXT: vfwsub.wf v8, v10, fa0, v0.t440; CHECK-NEXT: fsrm a1441; CHECK-NEXT: ret442entry:443 %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16(444 <vscale x 4 x float> %0,445 <vscale x 4 x float> %1,446 half %2,447 <vscale x 4 x i1> %3,448 iXLen 0, iXLen %4, iXLen 1)449 450 ret <vscale x 4 x float> %a451}452 453define <vscale x 8 x float> @intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, iXLen %2) nounwind {454; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16:455; CHECK: # %bb.0: # %entry456; CHECK-NEXT: fsrmi a1, 0457; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma458; CHECK-NEXT: vfwsub.wf v8, v8, fa0459; CHECK-NEXT: fsrm a1460; CHECK-NEXT: ret461entry:462 %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16(463 <vscale x 8 x float> poison,464 <vscale x 8 x float> %0,465 half %1,466 iXLen 0, iXLen %2)467 468 ret <vscale x 8 x float> %a469}470 471define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, <vscale x 8 x float> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {472; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16:473; CHECK: # %bb.0: # %entry474; CHECK-NEXT: fsrmi a1, 0475; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu476; CHECK-NEXT: vfwsub.wf v8, v12, fa0, v0.t477; CHECK-NEXT: fsrm a1478; CHECK-NEXT: ret479entry:480 %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16(481 <vscale x 8 x float> %0,482 <vscale x 8 x float> %1,483 half %2,484 <vscale x 8 x i1> %3,485 iXLen 0, iXLen %4, iXLen 1)486 487 ret <vscale x 8 x float> %a488}489 490define <vscale x 16 x float> @intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, iXLen %2) nounwind {491; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16:492; CHECK: # %bb.0: # %entry493; CHECK-NEXT: fsrmi a1, 0494; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma495; CHECK-NEXT: vfwsub.wf v8, v8, fa0496; CHECK-NEXT: fsrm a1497; CHECK-NEXT: ret498entry:499 %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16(500 <vscale x 16 x float> poison,501 <vscale x 16 x float> %0,502 half %1,503 iXLen 0, iXLen %2)504 505 ret <vscale x 16 x float> %a506}507 508define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {509; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16:510; CHECK: # %bb.0: # %entry511; CHECK-NEXT: fsrmi a1, 0512; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu513; CHECK-NEXT: vfwsub.wf v8, v16, fa0, v0.t514; CHECK-NEXT: fsrm a1515; CHECK-NEXT: ret516entry:517 %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16(518 <vscale x 16 x float> %0,519 <vscale x 16 x float> %1,520 half %2,521 <vscale x 16 x i1> %3,522 iXLen 0, iXLen %4, iXLen 1)523 524 ret <vscale x 16 x float> %a525}526 527define <vscale x 1 x double> @intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, iXLen %2) nounwind {528; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32:529; CHECK: # %bb.0: # %entry530; CHECK-NEXT: fsrmi a1, 0531; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma532; CHECK-NEXT: vfwsub.wf v8, v8, fa0533; CHECK-NEXT: fsrm a1534; CHECK-NEXT: ret535entry:536 %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32(537 <vscale x 1 x double> poison,538 <vscale x 1 x double> %0,539 float %1,540 iXLen 0, iXLen %2)541 542 ret <vscale x 1 x double> %a543}544 545define <vscale x 1 x double> @intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, <vscale x 1 x double> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {546; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32:547; CHECK: # %bb.0: # %entry548; CHECK-NEXT: fsrmi a1, 0549; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu550; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t551; CHECK-NEXT: fsrm a1552; CHECK-NEXT: ret553entry:554 %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.f32(555 <vscale x 1 x double> %0,556 <vscale x 1 x double> %1,557 float %2,558 <vscale x 1 x i1> %3,559 iXLen 0, iXLen %4, iXLen 1)560 561 ret <vscale x 1 x double> %a562}563 564define <vscale x 2 x double> @intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, iXLen %2) nounwind {565; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32:566; CHECK: # %bb.0: # %entry567; CHECK-NEXT: fsrmi a1, 0568; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma569; CHECK-NEXT: vfwsub.wf v8, v8, fa0570; CHECK-NEXT: fsrm a1571; CHECK-NEXT: ret572entry:573 %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32(574 <vscale x 2 x double> poison,575 <vscale x 2 x double> %0,576 float %1,577 iXLen 0, iXLen %2)578 579 ret <vscale x 2 x double> %a580}581 582define <vscale x 2 x double> @intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, <vscale x 2 x double> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {583; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32:584; CHECK: # %bb.0: # %entry585; CHECK-NEXT: fsrmi a1, 0586; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu587; CHECK-NEXT: vfwsub.wf v8, v10, fa0, v0.t588; CHECK-NEXT: fsrm a1589; CHECK-NEXT: ret590entry:591 %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.f32(592 <vscale x 2 x double> %0,593 <vscale x 2 x double> %1,594 float %2,595 <vscale x 2 x i1> %3,596 iXLen 0, iXLen %4, iXLen 1)597 598 ret <vscale x 2 x double> %a599}600 601define <vscale x 4 x double> @intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, iXLen %2) nounwind {602; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32:603; CHECK: # %bb.0: # %entry604; CHECK-NEXT: fsrmi a1, 0605; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma606; CHECK-NEXT: vfwsub.wf v8, v8, fa0607; CHECK-NEXT: fsrm a1608; CHECK-NEXT: ret609entry:610 %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32(611 <vscale x 4 x double> poison,612 <vscale x 4 x double> %0,613 float %1,614 iXLen 0, iXLen %2)615 616 ret <vscale x 4 x double> %a617}618 619define <vscale x 4 x double> @intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, <vscale x 4 x double> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {620; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32:621; CHECK: # %bb.0: # %entry622; CHECK-NEXT: fsrmi a1, 0623; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu624; CHECK-NEXT: vfwsub.wf v8, v12, fa0, v0.t625; CHECK-NEXT: fsrm a1626; CHECK-NEXT: ret627entry:628 %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.f32(629 <vscale x 4 x double> %0,630 <vscale x 4 x double> %1,631 float %2,632 <vscale x 4 x i1> %3,633 iXLen 0, iXLen %4, iXLen 1)634 635 ret <vscale x 4 x double> %a636}637 638define <vscale x 8 x double> @intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, iXLen %2) nounwind {639; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32:640; CHECK: # %bb.0: # %entry641; CHECK-NEXT: fsrmi a1, 0642; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma643; CHECK-NEXT: vfwsub.wf v8, v8, fa0644; CHECK-NEXT: fsrm a1645; CHECK-NEXT: ret646entry:647 %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32(648 <vscale x 8 x double> poison,649 <vscale x 8 x double> %0,650 float %1,651 iXLen 0, iXLen %2)652 653 ret <vscale x 8 x double> %a654}655 656define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {657; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32:658; CHECK: # %bb.0: # %entry659; CHECK-NEXT: fsrmi a1, 0660; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu661; CHECK-NEXT: vfwsub.wf v8, v16, fa0, v0.t662; CHECK-NEXT: fsrm a1663; CHECK-NEXT: ret664entry:665 %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.f32(666 <vscale x 8 x double> %0,667 <vscale x 8 x double> %1,668 float %2,669 <vscale x 8 x i1> %3,670 iXLen 0, iXLen %4, iXLen 1)671 672 ret <vscale x 8 x double> %a673}674 675define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {676; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1f16:677; CHECK: # %bb.0: # %entry678; CHECK-NEXT: fsrmi a1, 0679; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu680; CHECK-NEXT: vfwsub.wv v8, v8, v9, v0.t681; CHECK-NEXT: fsrm a1682; CHECK-NEXT: ret683entry:684 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.nxv1f16(685 <vscale x 1 x float> %0,686 <vscale x 1 x float> %0,687 <vscale x 1 x half> %1,688 <vscale x 1 x i1> %2,689 iXLen 0, iXLen %3, iXLen 1)690 691 ret <vscale x 1 x float> %a692}693 694define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {695; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2f16:696; CHECK: # %bb.0: # %entry697; CHECK-NEXT: fsrmi a1, 0698; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu699; CHECK-NEXT: vfwsub.wv v8, v8, v9, v0.t700; CHECK-NEXT: fsrm a1701; CHECK-NEXT: ret702entry:703 %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.nxv2f16(704 <vscale x 2 x float> %0,705 <vscale x 2 x float> %0,706 <vscale x 2 x half> %1,707 <vscale x 2 x i1> %2,708 iXLen 0, iXLen %3, iXLen 1)709 710 ret <vscale x 2 x float> %a711}712 713define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {714; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4f16:715; CHECK: # %bb.0: # %entry716; CHECK-NEXT: fsrmi a1, 0717; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu718; CHECK-NEXT: vfwsub.wv v8, v8, v10, v0.t719; CHECK-NEXT: fsrm a1720; CHECK-NEXT: ret721entry:722 %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.nxv4f16(723 <vscale x 4 x float> %0,724 <vscale x 4 x float> %0,725 <vscale x 4 x half> %1,726 <vscale x 4 x i1> %2,727 iXLen 0, iXLen %3, iXLen 1)728 729 ret <vscale x 4 x float> %a730}731 732define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {733; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8f16:734; CHECK: # %bb.0: # %entry735; CHECK-NEXT: fsrmi a1, 0736; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu737; CHECK-NEXT: vfwsub.wv v8, v8, v12, v0.t738; CHECK-NEXT: fsrm a1739; CHECK-NEXT: ret740entry:741 %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.nxv8f16(742 <vscale x 8 x float> %0,743 <vscale x 8 x float> %0,744 <vscale x 8 x half> %1,745 <vscale x 8 x i1> %2,746 iXLen 0, iXLen %3, iXLen 1)747 748 ret <vscale x 8 x float> %a749}750 751define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {752; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16f16:753; CHECK: # %bb.0: # %entry754; CHECK-NEXT: fsrmi a1, 0755; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu756; CHECK-NEXT: vfwsub.wv v8, v8, v16, v0.t757; CHECK-NEXT: fsrm a1758; CHECK-NEXT: ret759entry:760 %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16(761 <vscale x 16 x float> %0,762 <vscale x 16 x float> %0,763 <vscale x 16 x half> %1,764 <vscale x 16 x i1> %2,765 iXLen 0, iXLen %3, iXLen 1)766 767 ret <vscale x 16 x float> %a768}769 770define <vscale x 1 x double> @intrinsic_vfwsub.w_mask_wv_tie_nxv1f64_nxv1f64_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {771; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv1f64_nxv1f64_nxv1f32:772; CHECK: # %bb.0: # %entry773; CHECK-NEXT: fsrmi a1, 0774; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu775; CHECK-NEXT: vfwsub.wv v8, v8, v9, v0.t776; CHECK-NEXT: fsrm a1777; CHECK-NEXT: ret778entry:779 %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.nxv1f32(780 <vscale x 1 x double> %0,781 <vscale x 1 x double> %0,782 <vscale x 1 x float> %1,783 <vscale x 1 x i1> %2,784 iXLen 0, iXLen %3, iXLen 1)785 786 ret <vscale x 1 x double> %a787}788 789define <vscale x 2 x double> @intrinsic_vfwsub.w_mask_wv_tie_nxv2f64_nxv2f64_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {790; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv2f64_nxv2f64_nxv2f32:791; CHECK: # %bb.0: # %entry792; CHECK-NEXT: fsrmi a1, 0793; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu794; CHECK-NEXT: vfwsub.wv v8, v8, v10, v0.t795; CHECK-NEXT: fsrm a1796; CHECK-NEXT: ret797entry:798 %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.nxv2f32(799 <vscale x 2 x double> %0,800 <vscale x 2 x double> %0,801 <vscale x 2 x float> %1,802 <vscale x 2 x i1> %2,803 iXLen 0, iXLen %3, iXLen 1)804 805 ret <vscale x 2 x double> %a806}807 808define <vscale x 4 x double> @intrinsic_vfwsub.w_mask_wv_tie_nxv4f64_nxv4f64_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {809; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv4f64_nxv4f64_nxv4f32:810; CHECK: # %bb.0: # %entry811; CHECK-NEXT: fsrmi a1, 0812; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu813; CHECK-NEXT: vfwsub.wv v8, v8, v12, v0.t814; CHECK-NEXT: fsrm a1815; CHECK-NEXT: ret816entry:817 %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.nxv4f32(818 <vscale x 4 x double> %0,819 <vscale x 4 x double> %0,820 <vscale x 4 x float> %1,821 <vscale x 4 x i1> %2,822 iXLen 0, iXLen %3, iXLen 1)823 824 ret <vscale x 4 x double> %a825}826 827define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wv_tie_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {828; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv8f64_nxv8f64_nxv8f32:829; CHECK: # %bb.0: # %entry830; CHECK-NEXT: fsrmi a1, 0831; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu832; CHECK-NEXT: vfwsub.wv v8, v8, v16, v0.t833; CHECK-NEXT: fsrm a1834; CHECK-NEXT: ret835entry:836 %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32(837 <vscale x 8 x double> %0,838 <vscale x 8 x double> %0,839 <vscale x 8 x float> %1,840 <vscale x 8 x i1> %2,841 iXLen 0, iXLen %3, iXLen 1)842 843 ret <vscale x 8 x double> %a844}845 846define <vscale x 1 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {847; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv1f32_nxv1f32_f16:848; CHECK: # %bb.0: # %entry849; CHECK-NEXT: fsrmi a1, 0850; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu851; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t852; CHECK-NEXT: fsrm a1853; CHECK-NEXT: ret854entry:855 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.mask.nxv1f32.f16(856 <vscale x 1 x float> %0,857 <vscale x 1 x float> %0,858 half %1,859 <vscale x 1 x i1> %2,860 iXLen 0, iXLen %3, iXLen 1)861 862 ret <vscale x 1 x float> %a863}864 865define <vscale x 2 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {866; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv2f32_nxv2f32_f16:867; CHECK: # %bb.0: # %entry868; CHECK-NEXT: fsrmi a1, 0869; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu870; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t871; CHECK-NEXT: fsrm a1872; CHECK-NEXT: ret873entry:874 %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.mask.nxv2f32.f16(875 <vscale x 2 x float> %0,876 <vscale x 2 x float> %0,877 half %1,878 <vscale x 2 x i1> %2,879 iXLen 0, iXLen %3, iXLen 1)880 881 ret <vscale x 2 x float> %a882}883 884define <vscale x 4 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {885; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv4f32_nxv4f32_f16:886; CHECK: # %bb.0: # %entry887; CHECK-NEXT: fsrmi a1, 0888; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu889; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t890; CHECK-NEXT: fsrm a1891; CHECK-NEXT: ret892entry:893 %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.mask.nxv4f32.f16(894 <vscale x 4 x float> %0,895 <vscale x 4 x float> %0,896 half %1,897 <vscale x 4 x i1> %2,898 iXLen 0, iXLen %3, iXLen 1)899 900 ret <vscale x 4 x float> %a901}902 903define <vscale x 8 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {904; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv8f32_nxv8f32_f16:905; CHECK: # %bb.0: # %entry906; CHECK-NEXT: fsrmi a1, 0907; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu908; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t909; CHECK-NEXT: fsrm a1910; CHECK-NEXT: ret911entry:912 %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.mask.nxv8f32.f16(913 <vscale x 8 x float> %0,914 <vscale x 8 x float> %0,915 half %1,916 <vscale x 8 x i1> %2,917 iXLen 0, iXLen %3, iXLen 1)918 919 ret <vscale x 8 x float> %a920}921 922define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wf_tie_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {923; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv16f32_nxv16f32_f16:924; CHECK: # %bb.0: # %entry925; CHECK-NEXT: fsrmi a1, 0926; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu927; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t928; CHECK-NEXT: fsrm a1929; CHECK-NEXT: ret930entry:931 %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.f16(932 <vscale x 16 x float> %0,933 <vscale x 16 x float> %0,934 half %1,935 <vscale x 16 x i1> %2,936 iXLen 0, iXLen %3, iXLen 1)937 938 ret <vscale x 16 x float> %a939}940 941define <vscale x 1 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {942; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv1f64_nxv1f64_f32:943; CHECK: # %bb.0: # %entry944; CHECK-NEXT: fsrmi a1, 0945; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu946; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t947; CHECK-NEXT: fsrm a1948; CHECK-NEXT: ret949entry:950 %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.mask.nxv1f64.f32(951 <vscale x 1 x double> %0,952 <vscale x 1 x double> %0,953 float %1,954 <vscale x 1 x i1> %2,955 iXLen 0, iXLen %3, iXLen 1)956 957 ret <vscale x 1 x double> %a958}959 960define <vscale x 2 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {961; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv2f64_nxv2f64_f32:962; CHECK: # %bb.0: # %entry963; CHECK-NEXT: fsrmi a1, 0964; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu965; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t966; CHECK-NEXT: fsrm a1967; CHECK-NEXT: ret968entry:969 %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.mask.nxv2f64.f32(970 <vscale x 2 x double> %0,971 <vscale x 2 x double> %0,972 float %1,973 <vscale x 2 x i1> %2,974 iXLen 0, iXLen %3, iXLen 1)975 976 ret <vscale x 2 x double> %a977}978 979define <vscale x 4 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {980; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv4f64_nxv4f64_f32:981; CHECK: # %bb.0: # %entry982; CHECK-NEXT: fsrmi a1, 0983; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu984; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t985; CHECK-NEXT: fsrm a1986; CHECK-NEXT: ret987entry:988 %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.mask.nxv4f64.f32(989 <vscale x 4 x double> %0,990 <vscale x 4 x double> %0,991 float %1,992 <vscale x 4 x i1> %2,993 iXLen 0, iXLen %3, iXLen 1)994 995 ret <vscale x 4 x double> %a996}997 998define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wf_tie_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {999; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv8f64_nxv8f64_f32:1000; CHECK: # %bb.0: # %entry1001; CHECK-NEXT: fsrmi a1, 01002; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu1003; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t1004; CHECK-NEXT: fsrm a11005; CHECK-NEXT: ret1006entry:1007 %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.f32(1008 <vscale x 8 x double> %0,1009 <vscale x 8 x double> %0,1010 float %1,1011 <vscale x 8 x i1> %2,1012 iXLen 0, iXLen %3, iXLen 1)1013 1014 ret <vscale x 8 x double> %a1015}1016 1017define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {1018; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16:1019; CHECK: # %bb.0: # %entry1020; CHECK-NEXT: fsrmi a1, 01021; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1022; CHECK-NEXT: vfwsub.wv v10, v9, v81023; CHECK-NEXT: fsrm a11024; CHECK-NEXT: vmv1r.v v8, v101025; CHECK-NEXT: ret1026entry:1027 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16(1028 <vscale x 1 x float> poison,1029 <vscale x 1 x float> %1,1030 <vscale x 1 x half> %0,1031 iXLen 0, iXLen %2)1032 1033 ret <vscale x 1 x float> %a1034}1035 1036define <vscale x 2 x float> @intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {1037; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16:1038; CHECK: # %bb.0: # %entry1039; CHECK-NEXT: fsrmi a1, 01040; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1041; CHECK-NEXT: vfwsub.wv v10, v9, v81042; CHECK-NEXT: fsrm a11043; CHECK-NEXT: vmv1r.v v8, v101044; CHECK-NEXT: ret1045entry:1046 %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16(1047 <vscale x 2 x float> poison,1048 <vscale x 2 x float> %1,1049 <vscale x 2 x half> %0,1050 iXLen 0, iXLen %2)1051 1052 ret <vscale x 2 x float> %a1053}1054 1055define <vscale x 4 x float> @intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {1056; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16:1057; CHECK: # %bb.0: # %entry1058; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1059; CHECK-NEXT: vmv1r.v v12, v81060; CHECK-NEXT: fsrmi a0, 01061; CHECK-NEXT: vfwsub.wv v8, v10, v121062; CHECK-NEXT: fsrm a01063; CHECK-NEXT: ret1064entry:1065 %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16(1066 <vscale x 4 x float> poison,1067 <vscale x 4 x float> %1,1068 <vscale x 4 x half> %0,1069 iXLen 0, iXLen %2)1070 1071 ret <vscale x 4 x float> %a1072}1073 1074define <vscale x 8 x float> @intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {1075; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16:1076; CHECK: # %bb.0: # %entry1077; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1078; CHECK-NEXT: vmv2r.v v16, v81079; CHECK-NEXT: fsrmi a0, 01080; CHECK-NEXT: vfwsub.wv v8, v12, v161081; CHECK-NEXT: fsrm a01082; CHECK-NEXT: ret1083entry:1084 %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16(1085 <vscale x 8 x float> poison,1086 <vscale x 8 x float> %1,1087 <vscale x 8 x half> %0,1088 iXLen 0, iXLen %2)1089 1090 ret <vscale x 8 x float> %a1091}1092 1093define <vscale x 1 x double> @intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {1094; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f32:1095; CHECK: # %bb.0: # %entry1096; CHECK-NEXT: fsrmi a1, 01097; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1098; CHECK-NEXT: vfwsub.wv v10, v9, v81099; CHECK-NEXT: fsrm a11100; CHECK-NEXT: vmv1r.v v8, v101101; CHECK-NEXT: ret1102entry:1103 %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32(1104 <vscale x 1 x double> poison,1105 <vscale x 1 x double> %1,1106 <vscale x 1 x float> %0,1107 iXLen 0, iXLen %2)1108 1109 ret <vscale x 1 x double> %a1110}1111 1112define <vscale x 2 x double> @intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {1113; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f32:1114; CHECK: # %bb.0: # %entry1115; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1116; CHECK-NEXT: vmv1r.v v12, v81117; CHECK-NEXT: fsrmi a0, 01118; CHECK-NEXT: vfwsub.wv v8, v10, v121119; CHECK-NEXT: fsrm a01120; CHECK-NEXT: ret1121entry:1122 %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32(1123 <vscale x 2 x double> poison,1124 <vscale x 2 x double> %1,1125 <vscale x 2 x float> %0,1126 iXLen 0, iXLen %2)1127 1128 ret <vscale x 2 x double> %a1129}1130 1131define <vscale x 4 x double> @intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {1132; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f32:1133; CHECK: # %bb.0: # %entry1134; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1135; CHECK-NEXT: vmv2r.v v16, v81136; CHECK-NEXT: fsrmi a0, 01137; CHECK-NEXT: vfwsub.wv v8, v12, v161138; CHECK-NEXT: fsrm a01139; CHECK-NEXT: ret1140entry:1141 %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32(1142 <vscale x 4 x double> poison,1143 <vscale x 4 x double> %1,1144 <vscale x 4 x float> %0,1145 iXLen 0, iXLen %2)1146 1147 ret <vscale x 4 x double> %a1148}1149 1150define <vscale x 8 x double> @intrinsic_vfwsub.w_wv_untie_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x double> %1, iXLen %2) nounwind {1151; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv8f64_nxv8f64_nxv8f32:1152; CHECK: # %bb.0: # %entry1153; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1154; CHECK-NEXT: vmv4r.v v24, v81155; CHECK-NEXT: fsrmi a0, 01156; CHECK-NEXT: vfwsub.wv v8, v16, v241157; CHECK-NEXT: fsrm a01158; CHECK-NEXT: ret1159entry:1160 %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.nxv8f32(1161 <vscale x 8 x double> poison,1162 <vscale x 8 x double> %1,1163 <vscale x 8 x float> %0,1164 iXLen 0, iXLen %2)1165 1166 ret <vscale x 8 x double> %a1167}1168