92 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkg \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkg \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 1 x i32> @intrinsic_vghsh_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vghsh_vv_nxv1i32_nxv1i32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma11; CHECK-NEXT: vghsh.vv v8, v9, v1012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i32> @llvm.riscv.vghsh.nxv1i32.nxv1i32(15 <vscale x 1 x i32> %0,16 <vscale x 1 x i32> %1,17 <vscale x 1 x i32> %2,18 iXLen %3,19 iXLen 2)20 21 ret <vscale x 1 x i32> %a22}23 24define <vscale x 2 x i32> @intrinsic_vghsh_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {25; CHECK-LABEL: intrinsic_vghsh_vv_nxv2i32_nxv2i32:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma28; CHECK-NEXT: vghsh.vv v8, v9, v1029; CHECK-NEXT: ret30entry:31 %a = call <vscale x 2 x i32> @llvm.riscv.vghsh.nxv2i32.nxv2i32(32 <vscale x 2 x i32> %0,33 <vscale x 2 x i32> %1,34 <vscale x 2 x i32> %2,35 iXLen %3,36 iXLen 2)37 38 ret <vscale x 2 x i32> %a39}40 41define <vscale x 4 x i32> @intrinsic_vghsh_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {42; CHECK-LABEL: intrinsic_vghsh_vv_nxv4i32_nxv4i32:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma45; CHECK-NEXT: vghsh.vv v8, v10, v1246; CHECK-NEXT: ret47entry:48 %a = call <vscale x 4 x i32> @llvm.riscv.vghsh.nxv4i32.nxv4i32(49 <vscale x 4 x i32> %0,50 <vscale x 4 x i32> %1,51 <vscale x 4 x i32> %2,52 iXLen %3,53 iXLen 2)54 55 ret <vscale x 4 x i32> %a56}57 58define <vscale x 8 x i32> @intrinsic_vghsh_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {59; CHECK-LABEL: intrinsic_vghsh_vv_nxv8i32_nxv8i32:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma62; CHECK-NEXT: vghsh.vv v8, v12, v1663; CHECK-NEXT: ret64entry:65 %a = call <vscale x 8 x i32> @llvm.riscv.vghsh.nxv8i32.nxv8i32(66 <vscale x 8 x i32> %0,67 <vscale x 8 x i32> %1,68 <vscale x 8 x i32> %2,69 iXLen %3,70 iXLen 2)71 72 ret <vscale x 8 x i32> %a73}74 75define <vscale x 16 x i32> @intrinsic_vghsh_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {76; CHECK-LABEL: intrinsic_vghsh_vv_nxv16i32_nxv16i32:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vl8re32.v v24, (a0)79; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma80; CHECK-NEXT: vghsh.vv v8, v16, v2481; CHECK-NEXT: ret82entry:83 %a = call <vscale x 16 x i32> @llvm.riscv.vghsh.nxv16i32.nxv16i32(84 <vscale x 16 x i32> %0,85 <vscale x 16 x i32> %1,86 <vscale x 16 x i32> %2,87 iXLen %3,88 iXLen 2)89 90 ret <vscale x 16 x i32> %a91}92