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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vid_v_nxv1i8(iXLen %0) nounwind {8; CHECK-LABEL: intrinsic_vid_v_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vid.v v812; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(15 <vscale x 1 x i8> poison,16 iXLen %0)17 18 ret <vscale x 1 x i8> %a19}20 21define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {22; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu25; CHECK-NEXT: vid.v v8, v0.t26; CHECK-NEXT: ret27entry:28 %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(29 <vscale x 1 x i8> %0,30 <vscale x 1 x i1> %1,31 iXLen %2, iXLen 0)32 33 ret <vscale x 1 x i8> %a34}35 36define <vscale x 2 x i8> @intrinsic_vid_v_nxv2i8(iXLen %0) nounwind {37; CHECK-LABEL: intrinsic_vid_v_nxv2i8:38; CHECK: # %bb.0: # %entry39; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma40; CHECK-NEXT: vid.v v841; CHECK-NEXT: ret42entry:43 %a = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(44 <vscale x 2 x i8> poison,45 iXLen %0)46 47 ret <vscale x 2 x i8> %a48}49 50define <vscale x 2 x i8> @intrinsic_vid_mask_v_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {51; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i8:52; CHECK: # %bb.0: # %entry53; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu54; CHECK-NEXT: vid.v v8, v0.t55; CHECK-NEXT: ret56entry:57 %a = call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(58 <vscale x 2 x i8> %0,59 <vscale x 2 x i1> %1,60 iXLen %2, iXLen 0)61 62 ret <vscale x 2 x i8> %a63}64 65define <vscale x 4 x i8> @intrinsic_vid_v_nxv4i8(iXLen %0) nounwind {66; CHECK-LABEL: intrinsic_vid_v_nxv4i8:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma69; CHECK-NEXT: vid.v v870; CHECK-NEXT: ret71entry:72 %a = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(73 <vscale x 4 x i8> poison,74 iXLen %0)75 76 ret <vscale x 4 x i8> %a77}78 79define <vscale x 4 x i8> @intrinsic_vid_mask_v_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {80; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i8:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu83; CHECK-NEXT: vid.v v8, v0.t84; CHECK-NEXT: ret85entry:86 %a = call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(87 <vscale x 4 x i8> %0,88 <vscale x 4 x i1> %1,89 iXLen %2, iXLen 0)90 91 ret <vscale x 4 x i8> %a92}93 94define <vscale x 8 x i8> @intrinsic_vid_v_nxv8i8(iXLen %0) nounwind {95; CHECK-LABEL: intrinsic_vid_v_nxv8i8:96; CHECK: # %bb.0: # %entry97; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma98; CHECK-NEXT: vid.v v899; CHECK-NEXT: ret100entry:101 %a = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(102 <vscale x 8 x i8> poison,103 iXLen %0)104 105 ret <vscale x 8 x i8> %a106}107 108define <vscale x 8 x i8> @intrinsic_vid_mask_v_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {109; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i8:110; CHECK: # %bb.0: # %entry111; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu112; CHECK-NEXT: vid.v v8, v0.t113; CHECK-NEXT: ret114entry:115 %a = call <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(116 <vscale x 8 x i8> %0,117 <vscale x 8 x i1> %1,118 iXLen %2, iXLen 0)119 120 ret <vscale x 8 x i8> %a121}122 123define <vscale x 16 x i8> @intrinsic_vid_v_nxv16i8(iXLen %0) nounwind {124; CHECK-LABEL: intrinsic_vid_v_nxv16i8:125; CHECK: # %bb.0: # %entry126; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma127; CHECK-NEXT: vid.v v8128; CHECK-NEXT: ret129entry:130 %a = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(131 <vscale x 16 x i8> poison,132 iXLen %0)133 134 ret <vscale x 16 x i8> %a135}136 137define <vscale x 16 x i8> @intrinsic_vid_mask_v_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {138; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i8:139; CHECK: # %bb.0: # %entry140; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu141; CHECK-NEXT: vid.v v8, v0.t142; CHECK-NEXT: ret143entry:144 %a = call <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(145 <vscale x 16 x i8> %0,146 <vscale x 16 x i1> %1,147 iXLen %2, iXLen 0)148 149 ret <vscale x 16 x i8> %a150}151 152define <vscale x 32 x i8> @intrinsic_vid_v_nxv32i8(iXLen %0) nounwind {153; CHECK-LABEL: intrinsic_vid_v_nxv32i8:154; CHECK: # %bb.0: # %entry155; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma156; CHECK-NEXT: vid.v v8157; CHECK-NEXT: ret158entry:159 %a = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(160 <vscale x 32 x i8> poison,161 iXLen %0)162 163 ret <vscale x 32 x i8> %a164}165 166define <vscale x 32 x i8> @intrinsic_vid_mask_v_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {167; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i8:168; CHECK: # %bb.0: # %entry169; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu170; CHECK-NEXT: vid.v v8, v0.t171; CHECK-NEXT: ret172entry:173 %a = call <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(174 <vscale x 32 x i8> %0,175 <vscale x 32 x i1> %1,176 iXLen %2, iXLen 0)177 178 ret <vscale x 32 x i8> %a179}180 181define <vscale x 1 x i16> @intrinsic_vid_v_nxv1i16(iXLen %0) nounwind {182; CHECK-LABEL: intrinsic_vid_v_nxv1i16:183; CHECK: # %bb.0: # %entry184; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma185; CHECK-NEXT: vid.v v8186; CHECK-NEXT: ret187entry:188 %a = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(189 <vscale x 1 x i16> poison,190 iXLen %0)191 192 ret <vscale x 1 x i16> %a193}194 195define <vscale x 1 x i16> @intrinsic_vid_mask_v_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {196; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i16:197; CHECK: # %bb.0: # %entry198; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu199; CHECK-NEXT: vid.v v8, v0.t200; CHECK-NEXT: ret201entry:202 %a = call <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(203 <vscale x 1 x i16> %0,204 <vscale x 1 x i1> %1,205 iXLen %2, iXLen 0)206 207 ret <vscale x 1 x i16> %a208}209 210define <vscale x 2 x i16> @intrinsic_vid_v_nxv2i16(iXLen %0) nounwind {211; CHECK-LABEL: intrinsic_vid_v_nxv2i16:212; CHECK: # %bb.0: # %entry213; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma214; CHECK-NEXT: vid.v v8215; CHECK-NEXT: ret216entry:217 %a = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(218 <vscale x 2 x i16> poison,219 iXLen %0)220 221 ret <vscale x 2 x i16> %a222}223 224define <vscale x 2 x i16> @intrinsic_vid_mask_v_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {225; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i16:226; CHECK: # %bb.0: # %entry227; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu228; CHECK-NEXT: vid.v v8, v0.t229; CHECK-NEXT: ret230entry:231 %a = call <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(232 <vscale x 2 x i16> %0,233 <vscale x 2 x i1> %1,234 iXLen %2, iXLen 0)235 236 ret <vscale x 2 x i16> %a237}238 239define <vscale x 4 x i16> @intrinsic_vid_v_nxv4i16(iXLen %0) nounwind {240; CHECK-LABEL: intrinsic_vid_v_nxv4i16:241; CHECK: # %bb.0: # %entry242; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma243; CHECK-NEXT: vid.v v8244; CHECK-NEXT: ret245entry:246 %a = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(247 <vscale x 4 x i16> poison,248 iXLen %0)249 250 ret <vscale x 4 x i16> %a251}252 253define <vscale x 4 x i16> @intrinsic_vid_mask_v_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {254; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i16:255; CHECK: # %bb.0: # %entry256; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu257; CHECK-NEXT: vid.v v8, v0.t258; CHECK-NEXT: ret259entry:260 %a = call <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(261 <vscale x 4 x i16> %0,262 <vscale x 4 x i1> %1,263 iXLen %2, iXLen 0)264 265 ret <vscale x 4 x i16> %a266}267 268define <vscale x 8 x i16> @intrinsic_vid_v_nxv8i16(iXLen %0) nounwind {269; CHECK-LABEL: intrinsic_vid_v_nxv8i16:270; CHECK: # %bb.0: # %entry271; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma272; CHECK-NEXT: vid.v v8273; CHECK-NEXT: ret274entry:275 %a = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(276 <vscale x 8 x i16> poison,277 iXLen %0)278 279 ret <vscale x 8 x i16> %a280}281 282define <vscale x 8 x i16> @intrinsic_vid_mask_v_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {283; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i16:284; CHECK: # %bb.0: # %entry285; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu286; CHECK-NEXT: vid.v v8, v0.t287; CHECK-NEXT: ret288entry:289 %a = call <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(290 <vscale x 8 x i16> %0,291 <vscale x 8 x i1> %1,292 iXLen %2, iXLen 0)293 294 ret <vscale x 8 x i16> %a295}296 297define <vscale x 16 x i16> @intrinsic_vid_v_nxv16i16(iXLen %0) nounwind {298; CHECK-LABEL: intrinsic_vid_v_nxv16i16:299; CHECK: # %bb.0: # %entry300; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma301; CHECK-NEXT: vid.v v8302; CHECK-NEXT: ret303entry:304 %a = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(305 <vscale x 16 x i16> poison,306 iXLen %0)307 308 ret <vscale x 16 x i16> %a309}310 311define <vscale x 16 x i16> @intrinsic_vid_mask_v_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {312; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i16:313; CHECK: # %bb.0: # %entry314; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu315; CHECK-NEXT: vid.v v8, v0.t316; CHECK-NEXT: ret317entry:318 %a = call <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(319 <vscale x 16 x i16> %0,320 <vscale x 16 x i1> %1,321 iXLen %2, iXLen 0)322 323 ret <vscale x 16 x i16> %a324}325 326define <vscale x 32 x i16> @intrinsic_vid_v_nxv32i16(iXLen %0) nounwind {327; CHECK-LABEL: intrinsic_vid_v_nxv32i16:328; CHECK: # %bb.0: # %entry329; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma330; CHECK-NEXT: vid.v v8331; CHECK-NEXT: ret332entry:333 %a = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(334 <vscale x 32 x i16> poison,335 iXLen %0)336 337 ret <vscale x 32 x i16> %a338}339 340define <vscale x 32 x i16> @intrinsic_vid_mask_v_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {341; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i16:342; CHECK: # %bb.0: # %entry343; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu344; CHECK-NEXT: vid.v v8, v0.t345; CHECK-NEXT: ret346entry:347 %a = call <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(348 <vscale x 32 x i16> %0,349 <vscale x 32 x i1> %1,350 iXLen %2, iXLen 0)351 352 ret <vscale x 32 x i16> %a353}354 355define <vscale x 1 x i32> @intrinsic_vid_v_nxv1i32(iXLen %0) nounwind {356; CHECK-LABEL: intrinsic_vid_v_nxv1i32:357; CHECK: # %bb.0: # %entry358; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma359; CHECK-NEXT: vid.v v8360; CHECK-NEXT: ret361entry:362 %a = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(363 <vscale x 1 x i32> poison,364 iXLen %0)365 366 ret <vscale x 1 x i32> %a367}368 369define <vscale x 1 x i32> @intrinsic_vid_mask_v_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {370; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i32:371; CHECK: # %bb.0: # %entry372; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu373; CHECK-NEXT: vid.v v8, v0.t374; CHECK-NEXT: ret375entry:376 %a = call <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(377 <vscale x 1 x i32> %0,378 <vscale x 1 x i1> %1,379 iXLen %2, iXLen 0)380 381 ret <vscale x 1 x i32> %a382}383 384define <vscale x 2 x i32> @intrinsic_vid_v_nxv2i32(iXLen %0) nounwind {385; CHECK-LABEL: intrinsic_vid_v_nxv2i32:386; CHECK: # %bb.0: # %entry387; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma388; CHECK-NEXT: vid.v v8389; CHECK-NEXT: ret390entry:391 %a = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(392 <vscale x 2 x i32> poison,393 iXLen %0)394 395 ret <vscale x 2 x i32> %a396}397 398define <vscale x 2 x i32> @intrinsic_vid_mask_v_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {399; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i32:400; CHECK: # %bb.0: # %entry401; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu402; CHECK-NEXT: vid.v v8, v0.t403; CHECK-NEXT: ret404entry:405 %a = call <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(406 <vscale x 2 x i32> %0,407 <vscale x 2 x i1> %1,408 iXLen %2, iXLen 0)409 410 ret <vscale x 2 x i32> %a411}412 413define <vscale x 4 x i32> @intrinsic_vid_v_nxv4i32(iXLen %0) nounwind {414; CHECK-LABEL: intrinsic_vid_v_nxv4i32:415; CHECK: # %bb.0: # %entry416; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma417; CHECK-NEXT: vid.v v8418; CHECK-NEXT: ret419entry:420 %a = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(421 <vscale x 4 x i32> poison,422 iXLen %0)423 424 ret <vscale x 4 x i32> %a425}426 427define <vscale x 4 x i32> @intrinsic_vid_mask_v_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {428; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i32:429; CHECK: # %bb.0: # %entry430; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu431; CHECK-NEXT: vid.v v8, v0.t432; CHECK-NEXT: ret433entry:434 %a = call <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(435 <vscale x 4 x i32> %0,436 <vscale x 4 x i1> %1,437 iXLen %2, iXLen 0)438 439 ret <vscale x 4 x i32> %a440}441 442define <vscale x 8 x i32> @intrinsic_vid_v_nxv8i32(iXLen %0) nounwind {443; CHECK-LABEL: intrinsic_vid_v_nxv8i32:444; CHECK: # %bb.0: # %entry445; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma446; CHECK-NEXT: vid.v v8447; CHECK-NEXT: ret448entry:449 %a = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(450 <vscale x 8 x i32> poison,451 iXLen %0)452 453 ret <vscale x 8 x i32> %a454}455 456define <vscale x 8 x i32> @intrinsic_vid_mask_v_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {457; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i32:458; CHECK: # %bb.0: # %entry459; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu460; CHECK-NEXT: vid.v v8, v0.t461; CHECK-NEXT: ret462entry:463 %a = call <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(464 <vscale x 8 x i32> %0,465 <vscale x 8 x i1> %1,466 iXLen %2, iXLen 0)467 468 ret <vscale x 8 x i32> %a469}470 471define <vscale x 16 x i32> @intrinsic_vid_v_nxv16i32(iXLen %0) nounwind {472; CHECK-LABEL: intrinsic_vid_v_nxv16i32:473; CHECK: # %bb.0: # %entry474; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma475; CHECK-NEXT: vid.v v8476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(479 <vscale x 16 x i32> poison,480 iXLen %0)481 482 ret <vscale x 16 x i32> %a483}484 485define <vscale x 16 x i32> @intrinsic_vid_mask_v_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {486; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i32:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu489; CHECK-NEXT: vid.v v8, v0.t490; CHECK-NEXT: ret491entry:492 %a = call <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(493 <vscale x 16 x i32> %0,494 <vscale x 16 x i1> %1,495 iXLen %2, iXLen 0)496 497 ret <vscale x 16 x i32> %a498}499 500define <vscale x 1 x i64> @intrinsic_vid_v_nxv1i64(iXLen %0) nounwind {501; CHECK-LABEL: intrinsic_vid_v_nxv1i64:502; CHECK: # %bb.0: # %entry503; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma504; CHECK-NEXT: vid.v v8505; CHECK-NEXT: ret506entry:507 %a = call <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64(508 <vscale x 1 x i64> poison,509 iXLen %0)510 511 ret <vscale x 1 x i64> %a512}513 514define <vscale x 1 x i64> @intrinsic_vid_mask_v_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {515; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i64:516; CHECK: # %bb.0: # %entry517; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu518; CHECK-NEXT: vid.v v8, v0.t519; CHECK-NEXT: ret520entry:521 %a = call <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64(522 <vscale x 1 x i64> %0,523 <vscale x 1 x i1> %1,524 iXLen %2, iXLen 0)525 526 ret <vscale x 1 x i64> %a527}528 529define <vscale x 2 x i64> @intrinsic_vid_v_nxv2i64(iXLen %0) nounwind {530; CHECK-LABEL: intrinsic_vid_v_nxv2i64:531; CHECK: # %bb.0: # %entry532; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma533; CHECK-NEXT: vid.v v8534; CHECK-NEXT: ret535entry:536 %a = call <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64(537 <vscale x 2 x i64> poison,538 iXLen %0)539 540 ret <vscale x 2 x i64> %a541}542 543define <vscale x 2 x i64> @intrinsic_vid_mask_v_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {544; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i64:545; CHECK: # %bb.0: # %entry546; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu547; CHECK-NEXT: vid.v v8, v0.t548; CHECK-NEXT: ret549entry:550 %a = call <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64(551 <vscale x 2 x i64> %0,552 <vscale x 2 x i1> %1,553 iXLen %2, iXLen 0)554 555 ret <vscale x 2 x i64> %a556}557 558define <vscale x 4 x i64> @intrinsic_vid_v_nxv4i64(iXLen %0) nounwind {559; CHECK-LABEL: intrinsic_vid_v_nxv4i64:560; CHECK: # %bb.0: # %entry561; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma562; CHECK-NEXT: vid.v v8563; CHECK-NEXT: ret564entry:565 %a = call <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64(566 <vscale x 4 x i64> poison,567 iXLen %0)568 569 ret <vscale x 4 x i64> %a570}571 572define <vscale x 4 x i64> @intrinsic_vid_mask_v_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {573; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i64:574; CHECK: # %bb.0: # %entry575; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu576; CHECK-NEXT: vid.v v8, v0.t577; CHECK-NEXT: ret578entry:579 %a = call <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64(580 <vscale x 4 x i64> %0,581 <vscale x 4 x i1> %1,582 iXLen %2, iXLen 0)583 584 ret <vscale x 4 x i64> %a585}586 587define <vscale x 8 x i64> @intrinsic_vid_v_nxv8i64(iXLen %0) nounwind {588; CHECK-LABEL: intrinsic_vid_v_nxv8i64:589; CHECK: # %bb.0: # %entry590; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma591; CHECK-NEXT: vid.v v8592; CHECK-NEXT: ret593entry:594 %a = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(595 <vscale x 8 x i64> poison,596 iXLen %0)597 598 ret <vscale x 8 x i64> %a599}600 601define <vscale x 8 x i64> @intrinsic_vid_mask_v_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {602; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i64:603; CHECK: # %bb.0: # %entry604; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu605; CHECK-NEXT: vid.v v8, v0.t606; CHECK-NEXT: ret607entry:608 %a = call <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64(609 <vscale x 8 x i64> %0,610 <vscale x 8 x i1> %1,611 iXLen %2, iXLen 0)612 613 ret <vscale x 8 x i64> %a614}615