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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_viota_m_nxv1i8_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: viota.m v8, v012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(15 <vscale x 1 x i8> poison,16 <vscale x 1 x i1> %0,17 iXLen %1)18 19 ret <vscale x 1 x i8> %a20}21 22define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {23; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu26; CHECK-NEXT: viota.m v8, v0, v0.t27; CHECK-NEXT: ret28entry:29 %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(30 <vscale x 1 x i8> %0,31 <vscale x 1 x i1> %1,32 <vscale x 1 x i1> %1,33 iXLen %2, iXLen 0)34 35 ret <vscale x 1 x i8> %a36}37 38define <vscale x 2 x i8> @intrinsic_viota_m_nxv2i8_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {39; CHECK-LABEL: intrinsic_viota_m_nxv2i8_nxv2i1:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma42; CHECK-NEXT: viota.m v8, v043; CHECK-NEXT: ret44entry:45 %a = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(46 <vscale x 2 x i8> poison,47 <vscale x 2 x i1> %0,48 iXLen %1)49 50 ret <vscale x 2 x i8> %a51}52 53define <vscale x 2 x i8> @intrinsic_viota_mask_m_nxv2i8_nxv2i1(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {54; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu57; CHECK-NEXT: viota.m v8, v0, v0.t58; CHECK-NEXT: ret59entry:60 %a = call <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(61 <vscale x 2 x i8> %0,62 <vscale x 2 x i1> %1,63 <vscale x 2 x i1> %1,64 iXLen %2, iXLen 0)65 66 ret <vscale x 2 x i8> %a67}68 69define <vscale x 4 x i8> @intrinsic_viota_m_nxv4i8_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {70; CHECK-LABEL: intrinsic_viota_m_nxv4i8_nxv4i1:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma73; CHECK-NEXT: viota.m v8, v074; CHECK-NEXT: ret75entry:76 %a = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(77 <vscale x 4 x i8> poison,78 <vscale x 4 x i1> %0,79 iXLen %1)80 81 ret <vscale x 4 x i8> %a82}83 84define <vscale x 4 x i8> @intrinsic_viota_mask_m_nxv4i8_nxv4i1(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {85; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu88; CHECK-NEXT: viota.m v8, v0, v0.t89; CHECK-NEXT: ret90entry:91 %a = call <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(92 <vscale x 4 x i8> %0,93 <vscale x 4 x i1> %1,94 <vscale x 4 x i1> %1,95 iXLen %2, iXLen 0)96 97 ret <vscale x 4 x i8> %a98}99 100define <vscale x 8 x i8> @intrinsic_viota_m_nxv8i8_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {101; CHECK-LABEL: intrinsic_viota_m_nxv8i8_nxv8i1:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma104; CHECK-NEXT: viota.m v8, v0105; CHECK-NEXT: ret106entry:107 %a = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(108 <vscale x 8 x i8> poison,109 <vscale x 8 x i1> %0,110 iXLen %1)111 112 ret <vscale x 8 x i8> %a113}114 115define <vscale x 8 x i8> @intrinsic_viota_mask_m_nxv8i8_nxv8i1(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {116; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu119; CHECK-NEXT: viota.m v8, v0, v0.t120; CHECK-NEXT: ret121entry:122 %a = call <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(123 <vscale x 8 x i8> %0,124 <vscale x 8 x i1> %1,125 <vscale x 8 x i1> %1,126 iXLen %2, iXLen 0)127 128 ret <vscale x 8 x i8> %a129}130 131define <vscale x 16 x i8> @intrinsic_viota_m_nxv16i8_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {132; CHECK-LABEL: intrinsic_viota_m_nxv16i8_nxv16i1:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma135; CHECK-NEXT: viota.m v8, v0136; CHECK-NEXT: ret137entry:138 %a = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(139 <vscale x 16 x i8> poison,140 <vscale x 16 x i1> %0,141 iXLen %1)142 143 ret <vscale x 16 x i8> %a144}145 146define <vscale x 16 x i8> @intrinsic_viota_mask_m_nxv16i8_nxv16i1(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {147; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1:148; CHECK: # %bb.0: # %entry149; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu150; CHECK-NEXT: viota.m v8, v0, v0.t151; CHECK-NEXT: ret152entry:153 %a = call <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(154 <vscale x 16 x i8> %0,155 <vscale x 16 x i1> %1,156 <vscale x 16 x i1> %1,157 iXLen %2, iXLen 0)158 159 ret <vscale x 16 x i8> %a160}161 162define <vscale x 32 x i8> @intrinsic_viota_m_nxv32i8_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {163; CHECK-LABEL: intrinsic_viota_m_nxv32i8_nxv32i1:164; CHECK: # %bb.0: # %entry165; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma166; CHECK-NEXT: viota.m v8, v0167; CHECK-NEXT: ret168entry:169 %a = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(170 <vscale x 32 x i8> poison,171 <vscale x 32 x i1> %0,172 iXLen %1)173 174 ret <vscale x 32 x i8> %a175}176 177define <vscale x 32 x i8> @intrinsic_viota_mask_m_nxv32i8_nxv32i1(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {178; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu181; CHECK-NEXT: viota.m v8, v0, v0.t182; CHECK-NEXT: ret183entry:184 %a = call <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(185 <vscale x 32 x i8> %0,186 <vscale x 32 x i1> %1,187 <vscale x 32 x i1> %1,188 iXLen %2, iXLen 0)189 190 ret <vscale x 32 x i8> %a191}192 193define <vscale x 64 x i8> @intrinsic_viota_m_nxv64i8_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {194; CHECK-LABEL: intrinsic_viota_m_nxv64i8_nxv64i1:195; CHECK: # %bb.0: # %entry196; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma197; CHECK-NEXT: viota.m v8, v0198; CHECK-NEXT: ret199entry:200 %a = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(201 <vscale x 64 x i8> poison,202 <vscale x 64 x i1> %0,203 iXLen %1)204 205 ret <vscale x 64 x i8> %a206}207 208define <vscale x 64 x i8> @intrinsic_viota_mask_m_nxv64i8_nxv64i1(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {209; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1:210; CHECK: # %bb.0: # %entry211; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu212; CHECK-NEXT: viota.m v8, v0, v0.t213; CHECK-NEXT: ret214entry:215 %a = call <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(216 <vscale x 64 x i8> %0,217 <vscale x 64 x i1> %1,218 <vscale x 64 x i1> %1,219 iXLen %2, iXLen 0)220 221 ret <vscale x 64 x i8> %a222}223 224define <vscale x 1 x i16> @intrinsic_viota_m_nxv1i16_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {225; CHECK-LABEL: intrinsic_viota_m_nxv1i16_nxv1i1:226; CHECK: # %bb.0: # %entry227; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma228; CHECK-NEXT: viota.m v8, v0229; CHECK-NEXT: ret230entry:231 %a = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(232 <vscale x 1 x i16> poison,233 <vscale x 1 x i1> %0,234 iXLen %1)235 236 ret <vscale x 1 x i16> %a237}238 239define <vscale x 1 x i16> @intrinsic_viota_mask_m_nxv1i16_nxv1i1(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {240; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1:241; CHECK: # %bb.0: # %entry242; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu243; CHECK-NEXT: viota.m v8, v0, v0.t244; CHECK-NEXT: ret245entry:246 %a = call <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(247 <vscale x 1 x i16> %0,248 <vscale x 1 x i1> %1,249 <vscale x 1 x i1> %1,250 iXLen %2, iXLen 0)251 252 ret <vscale x 1 x i16> %a253}254 255define <vscale x 2 x i16> @intrinsic_viota_m_nxv2i16_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {256; CHECK-LABEL: intrinsic_viota_m_nxv2i16_nxv2i1:257; CHECK: # %bb.0: # %entry258; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma259; CHECK-NEXT: viota.m v8, v0260; CHECK-NEXT: ret261entry:262 %a = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(263 <vscale x 2 x i16> poison,264 <vscale x 2 x i1> %0,265 iXLen %1)266 267 ret <vscale x 2 x i16> %a268}269 270define <vscale x 2 x i16> @intrinsic_viota_mask_m_nxv2i16_nxv2i1(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {271; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1:272; CHECK: # %bb.0: # %entry273; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu274; CHECK-NEXT: viota.m v8, v0, v0.t275; CHECK-NEXT: ret276entry:277 %a = call <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(278 <vscale x 2 x i16> %0,279 <vscale x 2 x i1> %1,280 <vscale x 2 x i1> %1,281 iXLen %2, iXLen 0)282 283 ret <vscale x 2 x i16> %a284}285 286define <vscale x 4 x i16> @intrinsic_viota_m_nxv4i16_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {287; CHECK-LABEL: intrinsic_viota_m_nxv4i16_nxv4i1:288; CHECK: # %bb.0: # %entry289; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma290; CHECK-NEXT: viota.m v8, v0291; CHECK-NEXT: ret292entry:293 %a = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(294 <vscale x 4 x i16> poison,295 <vscale x 4 x i1> %0,296 iXLen %1)297 298 ret <vscale x 4 x i16> %a299}300 301define <vscale x 4 x i16> @intrinsic_viota_mask_m_nxv4i16_nxv4i1(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {302; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1:303; CHECK: # %bb.0: # %entry304; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu305; CHECK-NEXT: viota.m v8, v0, v0.t306; CHECK-NEXT: ret307entry:308 %a = call <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(309 <vscale x 4 x i16> %0,310 <vscale x 4 x i1> %1,311 <vscale x 4 x i1> %1,312 iXLen %2, iXLen 0)313 314 ret <vscale x 4 x i16> %a315}316 317define <vscale x 8 x i16> @intrinsic_viota_m_nxv8i16_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {318; CHECK-LABEL: intrinsic_viota_m_nxv8i16_nxv8i1:319; CHECK: # %bb.0: # %entry320; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma321; CHECK-NEXT: viota.m v8, v0322; CHECK-NEXT: ret323entry:324 %a = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(325 <vscale x 8 x i16> poison,326 <vscale x 8 x i1> %0,327 iXLen %1)328 329 ret <vscale x 8 x i16> %a330}331 332define <vscale x 8 x i16> @intrinsic_viota_mask_m_nxv8i16_nxv8i1(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {333; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1:334; CHECK: # %bb.0: # %entry335; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu336; CHECK-NEXT: viota.m v8, v0, v0.t337; CHECK-NEXT: ret338entry:339 %a = call <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(340 <vscale x 8 x i16> %0,341 <vscale x 8 x i1> %1,342 <vscale x 8 x i1> %1,343 iXLen %2, iXLen 0)344 345 ret <vscale x 8 x i16> %a346}347 348define <vscale x 16 x i16> @intrinsic_viota_m_nxv16i16_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {349; CHECK-LABEL: intrinsic_viota_m_nxv16i16_nxv16i1:350; CHECK: # %bb.0: # %entry351; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma352; CHECK-NEXT: viota.m v8, v0353; CHECK-NEXT: ret354entry:355 %a = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(356 <vscale x 16 x i16> poison,357 <vscale x 16 x i1> %0,358 iXLen %1)359 360 ret <vscale x 16 x i16> %a361}362 363define <vscale x 16 x i16> @intrinsic_viota_mask_m_nxv16i16_nxv16i1(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {364; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1:365; CHECK: # %bb.0: # %entry366; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu367; CHECK-NEXT: viota.m v8, v0, v0.t368; CHECK-NEXT: ret369entry:370 %a = call <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(371 <vscale x 16 x i16> %0,372 <vscale x 16 x i1> %1,373 <vscale x 16 x i1> %1,374 iXLen %2, iXLen 0)375 376 ret <vscale x 16 x i16> %a377}378 379define <vscale x 32 x i16> @intrinsic_viota_m_nxv32i16_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {380; CHECK-LABEL: intrinsic_viota_m_nxv32i16_nxv32i1:381; CHECK: # %bb.0: # %entry382; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma383; CHECK-NEXT: viota.m v8, v0384; CHECK-NEXT: ret385entry:386 %a = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(387 <vscale x 32 x i16> poison,388 <vscale x 32 x i1> %0,389 iXLen %1)390 391 ret <vscale x 32 x i16> %a392}393 394define <vscale x 32 x i16> @intrinsic_viota_mask_m_nxv32i16_nxv32i1(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {395; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i16_nxv32i1:396; CHECK: # %bb.0: # %entry397; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu398; CHECK-NEXT: viota.m v8, v0, v0.t399; CHECK-NEXT: ret400entry:401 %a = call <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(402 <vscale x 32 x i16> %0,403 <vscale x 32 x i1> %1,404 <vscale x 32 x i1> %1,405 iXLen %2, iXLen 0)406 407 ret <vscale x 32 x i16> %a408}409 410define <vscale x 1 x i32> @intrinsic_viota_m_nxv1i32_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {411; CHECK-LABEL: intrinsic_viota_m_nxv1i32_nxv1i1:412; CHECK: # %bb.0: # %entry413; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma414; CHECK-NEXT: viota.m v8, v0415; CHECK-NEXT: ret416entry:417 %a = call <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(418 <vscale x 1 x i32> poison,419 <vscale x 1 x i1> %0,420 iXLen %1)421 422 ret <vscale x 1 x i32> %a423}424 425define <vscale x 1 x i32> @intrinsic_viota_mask_m_nxv1i32_nxv1i1(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {426; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i32_nxv1i1:427; CHECK: # %bb.0: # %entry428; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu429; CHECK-NEXT: viota.m v8, v0, v0.t430; CHECK-NEXT: ret431entry:432 %a = call <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(433 <vscale x 1 x i32> %0,434 <vscale x 1 x i1> %1,435 <vscale x 1 x i1> %1,436 iXLen %2, iXLen 0)437 438 ret <vscale x 1 x i32> %a439}440 441define <vscale x 2 x i32> @intrinsic_viota_m_nxv2i32_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {442; CHECK-LABEL: intrinsic_viota_m_nxv2i32_nxv2i1:443; CHECK: # %bb.0: # %entry444; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma445; CHECK-NEXT: viota.m v8, v0446; CHECK-NEXT: ret447entry:448 %a = call <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(449 <vscale x 2 x i32> poison,450 <vscale x 2 x i1> %0,451 iXLen %1)452 453 ret <vscale x 2 x i32> %a454}455 456define <vscale x 2 x i32> @intrinsic_viota_mask_m_nxv2i32_nxv2i1(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {457; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i32_nxv2i1:458; CHECK: # %bb.0: # %entry459; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu460; CHECK-NEXT: viota.m v8, v0, v0.t461; CHECK-NEXT: ret462entry:463 %a = call <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(464 <vscale x 2 x i32> %0,465 <vscale x 2 x i1> %1,466 <vscale x 2 x i1> %1,467 iXLen %2, iXLen 0)468 469 ret <vscale x 2 x i32> %a470}471 472define <vscale x 4 x i32> @intrinsic_viota_m_nxv4i32_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {473; CHECK-LABEL: intrinsic_viota_m_nxv4i32_nxv4i1:474; CHECK: # %bb.0: # %entry475; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma476; CHECK-NEXT: viota.m v8, v0477; CHECK-NEXT: ret478entry:479 %a = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(480 <vscale x 4 x i32> poison,481 <vscale x 4 x i1> %0,482 iXLen %1)483 484 ret <vscale x 4 x i32> %a485}486 487define <vscale x 4 x i32> @intrinsic_viota_mask_m_nxv4i32_nxv4i1(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {488; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i32_nxv4i1:489; CHECK: # %bb.0: # %entry490; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu491; CHECK-NEXT: viota.m v8, v0, v0.t492; CHECK-NEXT: ret493entry:494 %a = call <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(495 <vscale x 4 x i32> %0,496 <vscale x 4 x i1> %1,497 <vscale x 4 x i1> %1,498 iXLen %2, iXLen 0)499 500 ret <vscale x 4 x i32> %a501}502 503define <vscale x 8 x i32> @intrinsic_viota_m_nxv8i32_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {504; CHECK-LABEL: intrinsic_viota_m_nxv8i32_nxv8i1:505; CHECK: # %bb.0: # %entry506; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma507; CHECK-NEXT: viota.m v8, v0508; CHECK-NEXT: ret509entry:510 %a = call <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(511 <vscale x 8 x i32> poison,512 <vscale x 8 x i1> %0,513 iXLen %1)514 515 ret <vscale x 8 x i32> %a516}517 518define <vscale x 8 x i32> @intrinsic_viota_mask_m_nxv8i32_nxv8i1(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {519; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i32_nxv8i1:520; CHECK: # %bb.0: # %entry521; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu522; CHECK-NEXT: viota.m v8, v0, v0.t523; CHECK-NEXT: ret524entry:525 %a = call <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(526 <vscale x 8 x i32> %0,527 <vscale x 8 x i1> %1,528 <vscale x 8 x i1> %1,529 iXLen %2, iXLen 0)530 531 ret <vscale x 8 x i32> %a532}533 534define <vscale x 16 x i32> @intrinsic_viota_m_nxv16i32_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {535; CHECK-LABEL: intrinsic_viota_m_nxv16i32_nxv16i1:536; CHECK: # %bb.0: # %entry537; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma538; CHECK-NEXT: viota.m v8, v0539; CHECK-NEXT: ret540entry:541 %a = call <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(542 <vscale x 16 x i32> poison,543 <vscale x 16 x i1> %0,544 iXLen %1)545 546 ret <vscale x 16 x i32> %a547}548 549define <vscale x 16 x i32> @intrinsic_viota_mask_m_nxv16i32_nxv16i1(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {550; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i32_nxv16i1:551; CHECK: # %bb.0: # %entry552; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu553; CHECK-NEXT: viota.m v8, v0, v0.t554; CHECK-NEXT: ret555entry:556 %a = call <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(557 <vscale x 16 x i32> %0,558 <vscale x 16 x i1> %1,559 <vscale x 16 x i1> %1,560 iXLen %2, iXLen 0)561 562 ret <vscale x 16 x i32> %a563}564 565define <vscale x 1 x i64> @intrinsic_viota_m_nxv1i64_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {566; CHECK-LABEL: intrinsic_viota_m_nxv1i64_nxv1i1:567; CHECK: # %bb.0: # %entry568; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma569; CHECK-NEXT: viota.m v8, v0570; CHECK-NEXT: ret571entry:572 %a = call <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64(573 <vscale x 1 x i64> poison,574 <vscale x 1 x i1> %0,575 iXLen %1)576 577 ret <vscale x 1 x i64> %a578}579 580define <vscale x 1 x i64> @intrinsic_viota_mask_m_nxv1i64_nxv1i1(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {581; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i64_nxv1i1:582; CHECK: # %bb.0: # %entry583; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu584; CHECK-NEXT: viota.m v8, v0, v0.t585; CHECK-NEXT: ret586entry:587 %a = call <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64(588 <vscale x 1 x i64> %0,589 <vscale x 1 x i1> %1,590 <vscale x 1 x i1> %1,591 iXLen %2, iXLen 0)592 593 ret <vscale x 1 x i64> %a594}595 596define <vscale x 2 x i64> @intrinsic_viota_m_nxv2i64_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {597; CHECK-LABEL: intrinsic_viota_m_nxv2i64_nxv2i1:598; CHECK: # %bb.0: # %entry599; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma600; CHECK-NEXT: viota.m v8, v0601; CHECK-NEXT: ret602entry:603 %a = call <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64(604 <vscale x 2 x i64> poison,605 <vscale x 2 x i1> %0,606 iXLen %1)607 608 ret <vscale x 2 x i64> %a609}610 611define <vscale x 2 x i64> @intrinsic_viota_mask_m_nxv2i64_nxv2i1(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {612; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i64_nxv2i1:613; CHECK: # %bb.0: # %entry614; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu615; CHECK-NEXT: viota.m v8, v0, v0.t616; CHECK-NEXT: ret617entry:618 %a = call <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64(619 <vscale x 2 x i64> %0,620 <vscale x 2 x i1> %1,621 <vscale x 2 x i1> %1,622 iXLen %2, iXLen 0)623 624 ret <vscale x 2 x i64> %a625}626 627define <vscale x 4 x i64> @intrinsic_viota_m_nxv4i64_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {628; CHECK-LABEL: intrinsic_viota_m_nxv4i64_nxv4i1:629; CHECK: # %bb.0: # %entry630; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma631; CHECK-NEXT: viota.m v8, v0632; CHECK-NEXT: ret633entry:634 %a = call <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64(635 <vscale x 4 x i64> poison,636 <vscale x 4 x i1> %0,637 iXLen %1)638 639 ret <vscale x 4 x i64> %a640}641 642define <vscale x 4 x i64> @intrinsic_viota_mask_m_nxv4i64_nxv4i1(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {643; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i64_nxv4i1:644; CHECK: # %bb.0: # %entry645; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu646; CHECK-NEXT: viota.m v8, v0, v0.t647; CHECK-NEXT: ret648entry:649 %a = call <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64(650 <vscale x 4 x i64> %0,651 <vscale x 4 x i1> %1,652 <vscale x 4 x i1> %1,653 iXLen %2, iXLen 0)654 655 ret <vscale x 4 x i64> %a656}657 658define <vscale x 8 x i64> @intrinsic_viota_m_nxv8i64_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {659; CHECK-LABEL: intrinsic_viota_m_nxv8i64_nxv8i1:660; CHECK: # %bb.0: # %entry661; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma662; CHECK-NEXT: viota.m v8, v0663; CHECK-NEXT: ret664entry:665 %a = call <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64(666 <vscale x 8 x i64> poison,667 <vscale x 8 x i1> %0,668 iXLen %1)669 670 ret <vscale x 8 x i64> %a671}672 673define <vscale x 8 x i64> @intrinsic_viota_mask_m_nxv8i64_nxv8i1(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {674; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i64_nxv8i1:675; CHECK: # %bb.0: # %entry676; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu677; CHECK-NEXT: viota.m v8, v0, v0.t678; CHECK-NEXT: ret679entry:680 %a = call <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64(681 <vscale x 8 x i64> %0,682 <vscale x 8 x i1> %1,683 <vscale x 8 x i1> %1,684 iXLen %2, iXLen 0)685 686 ret <vscale x 8 x i64> %a687}688