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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s3 4; Check that EVL tail folded loops from the loop vectorizer are able to have the5; vl of non-VP instructions reduced.6define void @evl_tail_folded(ptr %p, ptr %q) {7; CHECK-LABEL: evl_tail_folded:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: li a2, 010; CHECK-NEXT: csrr a3, vlenb11; CHECK-NEXT: srli a3, a3, 212; CHECK-NEXT: addi a4, a3, 102313; CHECK-NEXT: neg a5, a314; CHECK-NEXT: and a4, a4, a515; CHECK-NEXT: li a5, 102416; CHECK-NEXT: .LBB0_1: # %vector.body17; CHECK-NEXT: # =>This Inner Loop Header: Depth=118; CHECK-NEXT: sub a6, a5, a219; CHECK-NEXT: slli a7, a2, 320; CHECK-NEXT: vsetvli a6, a6, e64, m2, ta, ma21; CHECK-NEXT: add t0, a0, a722; CHECK-NEXT: vle64.v v8, (t0)23; CHECK-NEXT: sub a4, a4, a324; CHECK-NEXT: add a7, a1, a725; CHECK-NEXT: vadd.vi v8, v8, 126; CHECK-NEXT: vse64.v v8, (a7)27; CHECK-NEXT: add a2, a2, a628; CHECK-NEXT: bnez a4, .LBB0_129; CHECK-NEXT: # %bb.2: # %exit30; CHECK-NEXT: ret31entry:32 %0 = tail call i64 @llvm.vscale.i64()33 %1 = shl i64 %0, 134 %n.rnd.up = add i64 %1, 102335 %n.mod.vf = urem i64 %n.rnd.up, %136 %n.vec = sub i64 %n.rnd.up, %n.mod.vf37 %2 = tail call i64 @llvm.vscale.i64()38 %3 = shl i64 %2, 139 br label %vector.body40 41vector.body:42 %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]43 %evl.based.iv = phi i64 [ 0, %entry ], [ %index.evl.next, %vector.body ]44 %avl = sub i64 1024, %evl.based.iv45 %4 = tail call i32 @llvm.experimental.get.vector.length.i64(i64 %avl, i32 2, i1 true)46 %5 = getelementptr i64, ptr %p, i64 %evl.based.iv47 %vp.op.load = tail call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr %5, <vscale x 2 x i1> splat (i1 true), i32 %4)48 %6 = add <vscale x 2 x i64> %vp.op.load, splat (i64 1)49 %7 = getelementptr i64, ptr %q, i64 %evl.based.iv50 tail call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> %6, ptr %7, <vscale x 2 x i1> splat (i1 true), i32 %4)51 %8 = zext i32 %4 to i6452 %index.evl.next = add i64 %evl.based.iv, %853 %index.next = add i64 %index, %354 %9 = icmp eq i64 %index.next, %n.vec55 br i1 %9, label %exit, label %vector.body56 57exit:58 ret void59}60