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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb,+zvbc,+zvfbfwma -verify-machineinstrs | FileCheck %s3; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb,+zvbc,+zvfbfwma -verify-machineinstrs | FileCheck %s4 5; The purpose of this file is to check the behavior of specific instructions as it relates to the VL optimizer6 7define <vscale x 4 x i32> @vadd_vi(<vscale x 4 x i32> %a, iXLen %vl) {8; CHECK-LABEL: vadd_vi:9; CHECK:       # %bb.0:10; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma11; CHECK-NEXT:    vadd.vi v10, v8, 512; CHECK-NEXT:    vadd.vv v8, v10, v813; CHECK-NEXT:    ret14  %1 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 5, iXLen -1)15  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)16  ret <vscale x 4 x i32> %217}18 19define <vscale x 4 x i32> @vadd_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {20; CHECK-LABEL: vadd_vv:21; CHECK:       # %bb.0:22; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma23; CHECK-NEXT:    vadd.vv v8, v8, v1024; CHECK-NEXT:    vadd.vv v8, v8, v1025; CHECK-NEXT:    ret26  %1 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)27  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)28  ret <vscale x 4 x i32> %229}30 31define <vscale x 4 x i32> @vadd_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {32; CHECK-LABEL: vadd_vx:33; CHECK:       # %bb.0:34; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma35; CHECK-NEXT:    vadd.vx v10, v8, a036; CHECK-NEXT:    vadd.vv v8, v10, v837; CHECK-NEXT:    ret38  %1 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)39  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)40  ret <vscale x 4 x i32> %241}42 43define <vscale x 4 x i32> @vsub_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {44; CHECK-LABEL: vsub_vv:45; CHECK:       # %bb.0:46; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma47; CHECK-NEXT:    vsub.vv v8, v8, v1048; CHECK-NEXT:    vadd.vv v8, v8, v1049; CHECK-NEXT:    ret50  %1 = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)51  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)52  ret <vscale x 4 x i32> %253}54 55define <vscale x 4 x i32> @vsub_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {56; CHECK-LABEL: vsub_vx:57; CHECK:       # %bb.0:58; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma59; CHECK-NEXT:    vsub.vx v10, v8, a060; CHECK-NEXT:    vadd.vv v8, v10, v861; CHECK-NEXT:    ret62  %1 = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)63  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)64  ret <vscale x 4 x i32> %265}66 67define <vscale x 4 x i32> @vrsub_vi(<vscale x 4 x i32> %a, iXLen %vl) {68; CHECK-LABEL: vrsub_vi:69; CHECK:       # %bb.0:70; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma71; CHECK-NEXT:    vrsub.vi v10, v8, 572; CHECK-NEXT:    vadd.vv v8, v10, v873; CHECK-NEXT:    ret74  %1 = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 5, iXLen -1)75  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)76  ret <vscale x 4 x i32> %277}78 79define <vscale x 4 x i32> @vrsub_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {80; CHECK-LABEL: vrsub_vx:81; CHECK:       # %bb.0:82; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma83; CHECK-NEXT:    vrsub.vx v10, v8, a084; CHECK-NEXT:    vadd.vv v8, v10, v885; CHECK-NEXT:    ret86  %1 = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)87  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)88  ret <vscale x 4 x i32> %289}90 91define <vscale x 4 x i32> @vand_vi(<vscale x 4 x i32> %a, iXLen %vl) {92; CHECK-LABEL: vand_vi:93; CHECK:       # %bb.0:94; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma95; CHECK-NEXT:    vand.vi v10, v8, 596; CHECK-NEXT:    vadd.vv v8, v10, v897; CHECK-NEXT:    ret98  %1 = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 5, iXLen -1)99  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)100  ret <vscale x 4 x i32> %2101}102 103define <vscale x 4 x i32> @vand_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {104; CHECK-LABEL: vand_vv:105; CHECK:       # %bb.0:106; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma107; CHECK-NEXT:    vand.vv v8, v8, v10108; CHECK-NEXT:    vadd.vv v8, v8, v10109; CHECK-NEXT:    ret110  %1 = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)111  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)112  ret <vscale x 4 x i32> %2113}114 115define <vscale x 4 x i32> @vand_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {116; CHECK-LABEL: vand_vx:117; CHECK:       # %bb.0:118; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma119; CHECK-NEXT:    vand.vx v10, v8, a0120; CHECK-NEXT:    vadd.vv v8, v10, v8121; CHECK-NEXT:    ret122  %1 = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)123  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)124  ret <vscale x 4 x i32> %2125}126 127define <vscale x 4 x i32> @vor_vi(<vscale x 4 x i32> %a, iXLen %vl) {128; CHECK-LABEL: vor_vi:129; CHECK:       # %bb.0:130; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma131; CHECK-NEXT:    vor.vi v10, v8, 5132; CHECK-NEXT:    vadd.vv v8, v10, v8133; CHECK-NEXT:    ret134  %1 = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 5, iXLen -1)135  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)136  ret <vscale x 4 x i32> %2137}138 139define <vscale x 4 x i32> @vor_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {140; CHECK-LABEL: vor_vv:141; CHECK:       # %bb.0:142; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma143; CHECK-NEXT:    vor.vv v8, v8, v10144; CHECK-NEXT:    vadd.vv v8, v8, v10145; CHECK-NEXT:    ret146  %1 = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)147  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)148  ret <vscale x 4 x i32> %2149}150 151define <vscale x 4 x i32> @vor_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {152; CHECK-LABEL: vor_vx:153; CHECK:       # %bb.0:154; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma155; CHECK-NEXT:    vor.vx v10, v8, a0156; CHECK-NEXT:    vadd.vv v8, v10, v8157; CHECK-NEXT:    ret158  %1 = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)159  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)160  ret <vscale x 4 x i32> %2161}162 163define <vscale x 4 x i32> @vxor_vi(<vscale x 4 x i32> %a, iXLen %vl) {164; CHECK-LABEL: vxor_vi:165; CHECK:       # %bb.0:166; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma167; CHECK-NEXT:    vxor.vi v10, v8, 5168; CHECK-NEXT:    vadd.vv v8, v10, v8169; CHECK-NEXT:    ret170  %1 = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 5, iXLen -1)171  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)172  ret <vscale x 4 x i32> %2173}174 175define <vscale x 4 x i32> @vxor_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {176; CHECK-LABEL: vxor_vv:177; CHECK:       # %bb.0:178; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma179; CHECK-NEXT:    vxor.vv v8, v8, v10180; CHECK-NEXT:    vadd.vv v8, v8, v10181; CHECK-NEXT:    ret182  %1 = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)183  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)184  ret <vscale x 4 x i32> %2185}186 187define <vscale x 4 x i32> @vxor_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {188; CHECK-LABEL: vxor_vx:189; CHECK:       # %bb.0:190; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma191; CHECK-NEXT:    vxor.vx v10, v8, a0192; CHECK-NEXT:    vadd.vv v8, v10, v8193; CHECK-NEXT:    ret194  %1 = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)195  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)196  ret <vscale x 4 x i32> %2197}198 199define <vscale x 4 x i32> @vsll_vi(<vscale x 4 x i32> %a, iXLen %vl) {200; CHECK-LABEL: vsll_vi:201; CHECK:       # %bb.0:202; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma203; CHECK-NEXT:    vsll.vi v10, v8, 5204; CHECK-NEXT:    vadd.vv v8, v10, v8205; CHECK-NEXT:    ret206  %1 = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)207  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)208  ret <vscale x 4 x i32> %2209}210 211define <vscale x 4 x i32> @vsll_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {212; CHECK-LABEL: vsll_vv:213; CHECK:       # %bb.0:214; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma215; CHECK-NEXT:    vsll.vv v8, v8, v10216; CHECK-NEXT:    vadd.vv v8, v8, v10217; CHECK-NEXT:    ret218  %1 = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)219  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)220  ret <vscale x 4 x i32> %2221}222 223define <vscale x 4 x i32> @vsll_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {224; CHECK-LABEL: vsll_vx:225; CHECK:       # %bb.0:226; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma227; CHECK-NEXT:    vsll.vx v10, v8, a0228; CHECK-NEXT:    vadd.vv v8, v10, v8229; CHECK-NEXT:    ret230  %1 = call <vscale x 4 x i32> @llvm.riscv.vsll.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)231  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)232  ret <vscale x 4 x i32> %2233}234 235define <vscale x 4 x i64> @vwaddu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {236; CHECK-LABEL: vwaddu_vv:237; CHECK:       # %bb.0:238; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma239; CHECK-NEXT:    vwaddu.vv v12, v8, v10240; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma241; CHECK-NEXT:    vadd.vv v8, v12, v12242; CHECK-NEXT:    ret243  %1 = call <vscale x 4 x i64> @llvm.riscv.vwaddu.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)244  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)245  ret <vscale x 4 x i64> %2246}247 248define <vscale x 4 x i32> @vsrl_vi(<vscale x 4 x i32> %a, iXLen %vl) {249; CHECK-LABEL: vsrl_vi:250; CHECK:       # %bb.0:251; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma252; CHECK-NEXT:    vsrl.vi v10, v8, 5253; CHECK-NEXT:    vadd.vv v8, v10, v8254; CHECK-NEXT:    ret255  %1 = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)256  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)257  ret <vscale x 4 x i32> %2258}259 260define <vscale x 4 x i32> @vsrl_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {261; CHECK-LABEL: vsrl_vv:262; CHECK:       # %bb.0:263; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma264; CHECK-NEXT:    vsrl.vv v8, v8, v10265; CHECK-NEXT:    vadd.vv v8, v8, v10266; CHECK-NEXT:    ret267  %1 = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)268  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)269  ret <vscale x 4 x i32> %2270}271 272define <vscale x 4 x i32> @vsrl_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {273; CHECK-LABEL: vsrl_vx:274; CHECK:       # %bb.0:275; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma276; CHECK-NEXT:    vsrl.vx v10, v8, a0277; CHECK-NEXT:    vadd.vv v8, v10, v8278; CHECK-NEXT:    ret279  %1 = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)280  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)281  ret <vscale x 4 x i32> %2282}283 284define <vscale x 4 x i32> @vsra_vi(<vscale x 4 x i32> %a, iXLen %vl) {285; CHECK-LABEL: vsra_vi:286; CHECK:       # %bb.0:287; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma288; CHECK-NEXT:    vsra.vi v10, v8, 5289; CHECK-NEXT:    vadd.vv v8, v10, v8290; CHECK-NEXT:    ret291  %1 = call <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)292  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)293  ret <vscale x 4 x i32> %2294}295 296define <vscale x 4 x i32> @vsra_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {297; CHECK-LABEL: vsra_vv:298; CHECK:       # %bb.0:299; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma300; CHECK-NEXT:    vsra.vv v8, v8, v10301; CHECK-NEXT:    vadd.vv v8, v8, v10302; CHECK-NEXT:    ret303  %1 = call <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)304  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)305  ret <vscale x 4 x i32> %2306}307 308define <vscale x 4 x i32> @vsra_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {309; CHECK-LABEL: vsra_vx:310; CHECK:       # %bb.0:311; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma312; CHECK-NEXT:    vsra.vx v10, v8, a0313; CHECK-NEXT:    vadd.vv v8, v10, v8314; CHECK-NEXT:    ret315  %1 = call <vscale x 4 x i32> @llvm.riscv.vsra.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)316  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)317  ret <vscale x 4 x i32> %2318}319 320define <vscale x 4 x i64> @vwaddu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {321; CHECK-LABEL: vwaddu_vx:322; CHECK:       # %bb.0:323; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma324; CHECK-NEXT:    vwaddu.vx v12, v8, a0325; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma326; CHECK-NEXT:    vadd.vv v8, v12, v12327; CHECK-NEXT:    ret328  %1 = call <vscale x 4 x i64> @llvm.riscv.vwaddu.nxv4i64.nxv4i32.i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)329  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)330  ret <vscale x 4 x i64> %2331}332 333define <vscale x 4 x i64> @vwsubu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {334; CHECK-LABEL: vwsubu_vv:335; CHECK:       # %bb.0:336; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma337; CHECK-NEXT:    vwsubu.vv v12, v8, v10338; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma339; CHECK-NEXT:    vadd.vv v8, v12, v12340; CHECK-NEXT:    ret341  %1 = call <vscale x 4 x i64> @llvm.riscv.vwsubu.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)342  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)343  ret <vscale x 4 x i64> %2344}345 346define <vscale x 4 x i64> @vwsubu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {347; CHECK-LABEL: vwsubu_vx:348; CHECK:       # %bb.0:349; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma350; CHECK-NEXT:    vwsubu.vx v12, v8, a0351; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma352; CHECK-NEXT:    vadd.vv v8, v12, v12353; CHECK-NEXT:    ret354  %1 = call <vscale x 4 x i64> @llvm.riscv.vwsubu.nxv4i64.nxv4i32.i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)355  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)356  ret <vscale x 4 x i64> %2357}358 359define <vscale x 4 x i64> @vwadd_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {360; CHECK-LABEL: vwadd_vv:361; CHECK:       # %bb.0:362; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma363; CHECK-NEXT:    vwadd.vv v12, v8, v10364; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma365; CHECK-NEXT:    vadd.vv v8, v12, v12366; CHECK-NEXT:    ret367  %1 = call <vscale x 4 x i64> @llvm.riscv.vwadd.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)368  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)369  ret <vscale x 4 x i64> %2370}371 372define <vscale x 4 x i64> @vwadd_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {373; CHECK-LABEL: vwadd_vx:374; CHECK:       # %bb.0:375; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma376; CHECK-NEXT:    vwadd.vx v12, v8, a0377; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma378; CHECK-NEXT:    vadd.vv v8, v12, v12379; CHECK-NEXT:    ret380  %1 = call <vscale x 4 x i64> @llvm.riscv.vwadd.nxv4i64.nxv4i32.i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)381  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)382  ret <vscale x 4 x i64> %2383}384 385define <vscale x 4 x i64> @vwsub_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {386; CHECK-LABEL: vwsub_vv:387; CHECK:       # %bb.0:388; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma389; CHECK-NEXT:    vwsub.vv v12, v8, v10390; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma391; CHECK-NEXT:    vadd.vv v8, v12, v12392; CHECK-NEXT:    ret393  %1 = call <vscale x 4 x i64> @llvm.riscv.vwsub.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)394  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)395  ret <vscale x 4 x i64> %2396}397 398define <vscale x 4 x i64> @vwsub_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {399; CHECK-LABEL: vwsub_vx:400; CHECK:       # %bb.0:401; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma402; CHECK-NEXT:    vwsub.vx v12, v8, a0403; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma404; CHECK-NEXT:    vadd.vv v8, v12, v12405; CHECK-NEXT:    ret406  %1 = call <vscale x 4 x i64> @llvm.riscv.vwsub.nxv4i64.nxv4i32.i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)407  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)408  ret <vscale x 4 x i64> %2409}410 411define <vscale x 4 x i64> @vwaddu_wv(<vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen %vl) {412; CHECK-LABEL: vwaddu_wv:413; CHECK:       # %bb.0:414; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma415; CHECK-NEXT:    vwaddu.wv v8, v8, v12416; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma417; CHECK-NEXT:    vadd.vv v8, v8, v8418; CHECK-NEXT:    ret419  %1 = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen -1)420  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)421  ret <vscale x 4 x i64> %2422}423 424define <vscale x 4 x i64> @vwaddu_wx(<vscale x 4 x i64> %a, i32 %b, iXLen %vl) {425; CHECK-LABEL: vwaddu_wx:426; CHECK:       # %bb.0:427; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma428; CHECK-NEXT:    vwaddu.wx v8, v8, a0429; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma430; CHECK-NEXT:    vadd.vv v8, v8, v8431; CHECK-NEXT:    ret432  %1 = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.xv4i64.nxv4i32.i32(<vscale x 4 x i64> poison, <vscale x 4 x i64> %a, i32 %b, iXLen -1)433  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)434  ret <vscale x 4 x i64> %2435}436 437define <vscale x 4 x i64> @vwsubu_wv(<vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen %vl) {438; CHECK-LABEL: vwsubu_wv:439; CHECK:       # %bb.0:440; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma441; CHECK-NEXT:    vwsubu.wv v8, v8, v12442; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma443; CHECK-NEXT:    vadd.vv v8, v8, v8444; CHECK-NEXT:    ret445  %1 = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen -1)446  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)447  ret <vscale x 4 x i64> %2448}449 450define <vscale x 4 x i64> @vwsubu_wx(<vscale x 4 x i64> %a, i32 %b, iXLen %vl) {451; CHECK-LABEL: vwsubu_wx:452; CHECK:       # %bb.0:453; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma454; CHECK-NEXT:    vwsubu.wx v8, v8, a0455; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma456; CHECK-NEXT:    vadd.vv v8, v8, v8457; CHECK-NEXT:    ret458  %1 = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32.i32(<vscale x 4 x i64> poison, <vscale x 4 x i64> %a, i32 %b, iXLen -1)459  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)460  ret <vscale x 4 x i64> %2461}462 463define <vscale x 4 x i64> @vwadd_wv(<vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen %vl) {464; CHECK-LABEL: vwadd_wv:465; CHECK:       # %bb.0:466; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma467; CHECK-NEXT:    vwadd.wv v8, v8, v12468; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma469; CHECK-NEXT:    vadd.vv v8, v8, v8470; CHECK-NEXT:    ret471  %1 = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen -1)472  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)473  ret <vscale x 4 x i64> %2474}475 476define <vscale x 4 x i64> @vwadd_wx(<vscale x 4 x i64> %a, i32 %b, iXLen %vl) {477; CHECK-LABEL: vwadd_wx:478; CHECK:       # %bb.0:479; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma480; CHECK-NEXT:    vwadd.wx v8, v8, a0481; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma482; CHECK-NEXT:    vadd.vv v8, v8, v8483; CHECK-NEXT:    ret484  %1 = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.nxv4i32.i32(<vscale x 4 x i64> poison, <vscale x 4 x i64> %a, i32 %b, iXLen -1)485  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)486  ret <vscale x 4 x i64> %2487}488 489define <vscale x 4 x i64> @vwsub_wv(<vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen %vl) {490; CHECK-LABEL: vwsub_wv:491; CHECK:       # %bb.0:492; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma493; CHECK-NEXT:    vwsub.wv v8, v8, v12494; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma495; CHECK-NEXT:    vadd.vv v8, v8, v8496; CHECK-NEXT:    ret497  %1 = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen -1)498  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)499  ret <vscale x 4 x i64> %2500}501 502define <vscale x 4 x i64> @vwsub_wx(<vscale x 4 x i64> %a, i32 %b, iXLen %vl) {503; CHECK-LABEL: vwsub_wx:504; CHECK:       # %bb.0:505; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma506; CHECK-NEXT:    vwsub.wx v8, v8, a0507; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma508; CHECK-NEXT:    vadd.vv v8, v8, v8509; CHECK-NEXT:    ret510  %1 = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.nxv4i32.i32(<vscale x 4 x i64> poison, <vscale x 4 x i64> %a, i32 %b, iXLen -1)511  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)512  ret <vscale x 4 x i64> %2513}514 515define <vscale x 4 x i32> @vsext_vf2(<vscale x 4 x i16> %a, <vscale x 4 x i32> %b, iXLen %vl) {516; CHECK-LABEL: vsext_vf2:517; CHECK:       # %bb.0:518; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma519; CHECK-NEXT:    vsext.vf2 v12, v8520; CHECK-NEXT:    vadd.vv v8, v12, v10521; CHECK-NEXT:    ret522  %1 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16(<vscale x 4 x i32> poison, <vscale x 4 x i16> %a, iXLen -1)523  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)524  ret <vscale x 4 x i32> %2525}526 527define <vscale x 4 x i32> @vsext_vf4(<vscale x 4 x i8> %a, <vscale x 4 x i32> %b, iXLen %vl) {528; CHECK-LABEL: vsext_vf4:529; CHECK:       # %bb.0:530; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma531; CHECK-NEXT:    vsext.vf4 v12, v8532; CHECK-NEXT:    vadd.vv v8, v12, v10533; CHECK-NEXT:    ret534  %1 = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8(<vscale x 4 x i32> poison, <vscale x 4 x i8> %a, iXLen -1)535  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)536  ret <vscale x 4 x i32> %2537}538 539define <vscale x 4 x i64> @vsext_vf8(<vscale x 4 x i8> %a, <vscale x 4 x i64> %b, iXLen %vl) {540; CHECK-LABEL: vsext_vf8:541; CHECK:       # %bb.0:542; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma543; CHECK-NEXT:    vsext.vf8 v16, v8544; CHECK-NEXT:    vadd.vv v8, v16, v12545; CHECK-NEXT:    ret546  %1 = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i32.nxv4i8(<vscale x 4 x i64> poison, <vscale x 4 x i8> %a, iXLen -1)547  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %b, iXLen %vl)548  ret <vscale x 4 x i64> %2549}550 551define <vscale x 4 x i32> @vzext_vf2(<vscale x 4 x i16> %a, <vscale x 4 x i32> %b, iXLen %vl) {552; CHECK-LABEL: vzext_vf2:553; CHECK:       # %bb.0:554; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma555; CHECK-NEXT:    vzext.vf2 v12, v8556; CHECK-NEXT:    vadd.vv v8, v12, v10557; CHECK-NEXT:    ret558  %1 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16(<vscale x 4 x i32> poison, <vscale x 4 x i16> %a, iXLen -1)559  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)560  ret <vscale x 4 x i32> %2561}562 563define <vscale x 4 x i32> @vzext_vf4(<vscale x 4 x i8> %a, <vscale x 4 x i32> %b, iXLen %vl) {564; CHECK-LABEL: vzext_vf4:565; CHECK:       # %bb.0:566; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma567; CHECK-NEXT:    vzext.vf4 v12, v8568; CHECK-NEXT:    vadd.vv v8, v12, v10569; CHECK-NEXT:    ret570  %1 = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8(<vscale x 4 x i32> poison, <vscale x 4 x i8> %a, iXLen -1)571  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)572  ret <vscale x 4 x i32> %2573}574 575define <vscale x 4 x i64> @vzext_vf8(<vscale x 4 x i8> %a, <vscale x 4 x i64> %b, iXLen %vl) {576; CHECK-LABEL: vzext_vf8:577; CHECK:       # %bb.0:578; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma579; CHECK-NEXT:    vzext.vf8 v16, v8580; CHECK-NEXT:    vadd.vv v8, v16, v12581; CHECK-NEXT:    ret582  %1 = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i32.nxv4i8(<vscale x 4 x i64> poison, <vscale x 4 x i8> %a, iXLen -1)583  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %b, iXLen %vl)584  ret <vscale x 4 x i64> %2585}586 587define <vscale x 4 x i1> @vmadc_vi(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, iXLen %vl) {588; CHECK-LABEL: vmadc_vi:589; CHECK:       # %bb.0:590; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma591; CHECK-NEXT:    vmadc.vi v10, v8, 5592; CHECK-NEXT:    vmand.mm v0, v10, v0593; CHECK-NEXT:    ret594  %1 = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i32.i32(<vscale x 4 x i32> %a, i32 5, iXLen -1)595  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)596  ret <vscale x 4 x i1> %2597}598 599define <vscale x 4 x i1> @vmadc_vx(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {600; CHECK-LABEL: vmadc_vx:601; CHECK:       # %bb.0:602; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma603; CHECK-NEXT:    vmadc.vx v10, v8, a0604; CHECK-NEXT:    vmand.mm v0, v10, v0605; CHECK-NEXT:    ret606  %1 = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, iXLen -1)607  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)608  ret <vscale x 4 x i1> %2609}610 611define <vscale x 4 x i1> @vmadc_vv(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, <vscale x 4 x i32> %c, iXLen %vl) {612; CHECK-LABEL: vmadc_vv:613; CHECK:       # %bb.0:614; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma615; CHECK-NEXT:    vmadc.vv v12, v8, v10616; CHECK-NEXT:    vmand.mm v0, v12, v0617; CHECK-NEXT:    ret618  %1 = call <vscale x 4 x i1> @llvm.riscv.vmadc.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %c, iXLen -1)619  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)620  ret <vscale x 4 x i1> %2621}622 623define <vscale x 4 x i1> @vmadc_vim(<vscale x 4 x i32> %a, <vscale x 4 x i1> %mask, <vscale x 4 x i1> %b, iXLen %vl) {624; CHECK-LABEL: vmadc_vim:625; CHECK:       # %bb.0:626; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma627; CHECK-NEXT:    vmadc.vim v11, v8, 5, v0628; CHECK-NEXT:    vmand.mm v0, v11, v10629; CHECK-NEXT:    ret630  %1 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.i32(<vscale x 4 x i32> %a, i32 5, <vscale x 4 x i1> %mask, iXLen -1)631  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)632  ret <vscale x 4 x i1> %2633}634 635define <vscale x 4 x i1> @vmadc_vxm(<vscale x 4 x i32> %a, <vscale x 4 x i1> %mask, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {636; CHECK-LABEL: vmadc_vxm:637; CHECK:       # %bb.0:638; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma639; CHECK-NEXT:    vmadc.vxm v11, v8, a0, v0640; CHECK-NEXT:    vmand.mm v0, v11, v10641; CHECK-NEXT:    ret642  %1 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, <vscale x 4 x i1> %mask, iXLen -1)643  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)644  ret <vscale x 4 x i1> %2645}646 647define <vscale x 4 x i1> @vmadc_vvm(<vscale x 4 x i32> %a, <vscale x 4 x i1> %mask, <vscale x 4 x i1> %b, <vscale x 4 x i32> %c, iXLen %vl) {648; CHECK-LABEL: vmadc_vvm:649; CHECK:       # %bb.0:650; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma651; CHECK-NEXT:    vmadc.vvm v11, v8, v12, v0652; CHECK-NEXT:    vmand.mm v0, v11, v10653; CHECK-NEXT:    ret654  %1 = call <vscale x 4 x i1> @llvm.riscv.vmadc.carry.in.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %c, <vscale x 4 x i1> %mask, iXLen -1)655  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)656  ret <vscale x 4 x i1> %2657}658 659define <vscale x 4 x i1> @vmsbc_vvm(<vscale x 4 x i32> %a, <vscale x 4 x i1> %mask, <vscale x 4 x i1> %b, <vscale x 4 x i32> %c, iXLen %vl) {660; CHECK-LABEL: vmsbc_vvm:661; CHECK:       # %bb.0:662; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma663; CHECK-NEXT:    vmsbc.vvm v11, v8, v12, v0664; CHECK-NEXT:    vmand.mm v0, v11, v10665; CHECK-NEXT:    ret666  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %c, <vscale x 4 x i1> %mask, iXLen -1)667  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)668  ret <vscale x 4 x i1> %2669}670 671define <vscale x 4 x i1> @vmsbc_vxm(<vscale x 4 x i32> %a, <vscale x 4 x i1> %mask, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {672; CHECK-LABEL: vmsbc_vxm:673; CHECK:       # %bb.0:674; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma675; CHECK-NEXT:    vmsbc.vxm v11, v8, a0, v0676; CHECK-NEXT:    vmand.mm v0, v11, v10677; CHECK-NEXT:    ret678  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.borrow.in.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, <vscale x 4 x i1> %mask, iXLen -1)679  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)680  ret <vscale x 4 x i1> %2681}682 683define <vscale x 4 x i1> @vmsbc_vx(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {684; CHECK-LABEL: vmsbc_vx:685; CHECK:       # %bb.0:686; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma687; CHECK-NEXT:    vmsbc.vx v10, v8, a0688; CHECK-NEXT:    vmand.mm v0, v10, v0689; CHECK-NEXT:    ret690  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, iXLen -1)691  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)692  ret <vscale x 4 x i1> %2693}694 695define <vscale x 4 x i1> @vmsbc_vv(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, <vscale x 4 x i32> %c, iXLen %vl) {696; CHECK-LABEL: vmsbc_vv:697; CHECK:       # %bb.0:698; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma699; CHECK-NEXT:    vmsbc.vv v12, v8, v10700; CHECK-NEXT:    vmand.mm v0, v12, v0701; CHECK-NEXT:    ret702  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %c, iXLen -1)703  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)704  ret <vscale x 4 x i1> %2705}706 707define <vscale x 4 x i16> @vnsrl_wi(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, iXLen %vl) {708; CHECK-LABEL: vnsrl_wi:709; CHECK:       # %bb.0:710; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma711; CHECK-NEXT:    vnsrl.wi v11, v8, 5712; CHECK-NEXT:    vadd.vv v8, v11, v10713; CHECK-NEXT:    ret714  %1 = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(<vscale x 4 x i16> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)715  %2 = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> %1, <vscale x 4 x i16> %b, iXLen %vl)716  ret <vscale x 4 x i16> %2717}718 719define <vscale x 4 x i16> @vnsrl_wx(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, iXLen %c, iXLen %vl) {720; CHECK-LABEL: vnsrl_wx:721; CHECK:       # %bb.0:722; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma723; CHECK-NEXT:    vnsrl.wx v11, v8, a0724; CHECK-NEXT:    vadd.vv v8, v11, v10725; CHECK-NEXT:    ret726  %1 = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(<vscale x 4 x i16> poison, <vscale x 4 x i32> %a, iXLen %c, iXLen -1)727  %2 = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> %1, <vscale x 4 x i16> %b, iXLen %vl)728  ret <vscale x 4 x i16> %2729}730 731define <vscale x 4 x i16> @vnsrl_wv(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, iXLen %vl) {732; CHECK-LABEL: vnsrl_wv:733; CHECK:       # %bb.0:734; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma735; CHECK-NEXT:    vnsrl.wv v12, v8, v11736; CHECK-NEXT:    vadd.vv v8, v12, v10737; CHECK-NEXT:    ret738  %1 = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i32> %a, <vscale x 4 x i16> %c, iXLen -1)739  %2 = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> %1, <vscale x 4 x i16> %b, iXLen %vl)740  ret <vscale x 4 x i16> %2741}742 743define <vscale x 4 x i16> @vnsra_wi(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, iXLen %vl) {744; CHECK-LABEL: vnsra_wi:745; CHECK:       # %bb.0:746; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma747; CHECK-NEXT:    vnsra.wi v11, v8, 5748; CHECK-NEXT:    vadd.vv v8, v11, v10749; CHECK-NEXT:    ret750  %1 = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(<vscale x 4 x i16> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)751  %2 = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> %1, <vscale x 4 x i16> %b, iXLen %vl)752  ret <vscale x 4 x i16> %2753}754 755define <vscale x 4 x i16> @vnsra_wx(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, iXLen %c, iXLen %vl) {756; CHECK-LABEL: vnsra_wx:757; CHECK:       # %bb.0:758; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma759; CHECK-NEXT:    vnsra.wx v11, v8, a0760; CHECK-NEXT:    vadd.vv v8, v11, v10761; CHECK-NEXT:    ret762  %1 = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(<vscale x 4 x i16> poison, <vscale x 4 x i32> %a, iXLen %c, iXLen -1)763  %2 = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> %1, <vscale x 4 x i16> %b, iXLen %vl)764  ret <vscale x 4 x i16> %2765}766 767define <vscale x 4 x i16> @vnsra_wv(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, iXLen %vl) {768; CHECK-LABEL: vnsra_wv:769; CHECK:       # %bb.0:770; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma771; CHECK-NEXT:    vnsra.wv v12, v8, v11772; CHECK-NEXT:    vadd.vv v8, v12, v10773; CHECK-NEXT:    ret774  %1 = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i32> %a, <vscale x 4 x i16> %c, iXLen -1)775  %2 = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> %1, <vscale x 4 x i16> %b, iXLen %vl)776  ret <vscale x 4 x i16> %2777}778 779define <vscale x 4 x i1> @vmseq_vi(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, iXLen %vl) {780; CHECK-LABEL: vmseq_vi:781; CHECK:       # %bb.0:782; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma783; CHECK-NEXT:    vmseq.vi v10, v8, 5784; CHECK-NEXT:    vmand.mm v0, v10, v0785; CHECK-NEXT:    ret786  %1 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32(<vscale x 4 x i32> %a, i32 5, iXLen -1)787  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)788  ret <vscale x 4 x i1> %2789}790 791define <vscale x 4 x i1> @vmseq_vx(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {792; CHECK-LABEL: vmseq_vx:793; CHECK:       # %bb.0:794; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma795; CHECK-NEXT:    vmseq.vx v10, v8, a0796; CHECK-NEXT:    vmand.mm v0, v10, v0797; CHECK-NEXT:    ret798  %1 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, iXLen -1)799  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)800  ret <vscale x 4 x i1> %2801}802 803define <vscale x 4 x i1> @vmseq_vv(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, <vscale x 4 x i32> %c, iXLen %vl) {804; CHECK-LABEL: vmseq_vv:805; CHECK:       # %bb.0:806; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma807; CHECK-NEXT:    vmseq.vv v12, v8, v10808; CHECK-NEXT:    vmand.mm v0, v12, v0809; CHECK-NEXT:    ret810  %1 = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %c, iXLen -1)811  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)812  ret <vscale x 4 x i1> %2813}814 815define <vscale x 4 x i1> @vmsne_vi(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, iXLen %vl) {816; CHECK-LABEL: vmsne_vi:817; CHECK:       # %bb.0:818; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma819; CHECK-NEXT:    vmsne.vi v10, v8, 5820; CHECK-NEXT:    vmand.mm v0, v10, v0821; CHECK-NEXT:    ret822  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32(<vscale x 4 x i32> %a, i32 5, iXLen -1)823  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)824  ret <vscale x 4 x i1> %2825}826 827define <vscale x 4 x i1> @vmsne_vx(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {828; CHECK-LABEL: vmsne_vx:829; CHECK:       # %bb.0:830; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma831; CHECK-NEXT:    vmsne.vx v10, v8, a0832; CHECK-NEXT:    vmand.mm v0, v10, v0833; CHECK-NEXT:    ret834  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, iXLen -1)835  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)836  ret <vscale x 4 x i1> %2837}838 839define <vscale x 4 x i1> @vmsne_vv(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, <vscale x 4 x i32> %c, iXLen %vl) {840; CHECK-LABEL: vmsne_vv:841; CHECK:       # %bb.0:842; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma843; CHECK-NEXT:    vmsne.vv v12, v8, v10844; CHECK-NEXT:    vmand.mm v0, v12, v0845; CHECK-NEXT:    ret846  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %c, iXLen -1)847  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)848  ret <vscale x 4 x i1> %2849}850 851define <vscale x 4 x i1> @vmsltu_vx(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {852; CHECK-LABEL: vmsltu_vx:853; CHECK:       # %bb.0:854; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma855; CHECK-NEXT:    vmsltu.vx v10, v8, a0856; CHECK-NEXT:    vmand.mm v0, v10, v0857; CHECK-NEXT:    ret858  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, iXLen -1)859  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)860  ret <vscale x 4 x i1> %2861}862 863define <vscale x 4 x i1> @vmsltu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, <vscale x 4 x i32> %c, iXLen %vl) {864; CHECK-LABEL: vmsltu_vv:865; CHECK:       # %bb.0:866; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma867; CHECK-NEXT:    vmsltu.vv v12, v8, v10868; CHECK-NEXT:    vmand.mm v0, v12, v0869; CHECK-NEXT:    ret870  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %c, iXLen -1)871  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)872  ret <vscale x 4 x i1> %2873}874 875define <vscale x 4 x i1> @vmslt_vx(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {876; CHECK-LABEL: vmslt_vx:877; CHECK:       # %bb.0:878; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma879; CHECK-NEXT:    vmslt.vx v10, v8, a0880; CHECK-NEXT:    vmand.mm v0, v10, v0881; CHECK-NEXT:    ret882  %1 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, iXLen -1)883  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)884  ret <vscale x 4 x i1> %2885}886 887define <vscale x 4 x i1> @vmslt_vv(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, <vscale x 4 x i32> %c, iXLen %vl) {888; CHECK-LABEL: vmslt_vv:889; CHECK:       # %bb.0:890; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma891; CHECK-NEXT:    vmslt.vv v12, v8, v10892; CHECK-NEXT:    vmand.mm v0, v12, v0893; CHECK-NEXT:    ret894  %1 = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %c, iXLen -1)895  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)896  ret <vscale x 4 x i1> %2897}898 899define <vscale x 4 x i1> @vmsleu_vi(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, iXLen %vl) {900; CHECK-LABEL: vmsleu_vi:901; CHECK:       # %bb.0:902; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma903; CHECK-NEXT:    vmsleu.vi v10, v8, 5904; CHECK-NEXT:    vmand.mm v0, v10, v0905; CHECK-NEXT:    ret906  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32(<vscale x 4 x i32> %a, i32 5, iXLen -1)907  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)908  ret <vscale x 4 x i1> %2909}910 911define <vscale x 4 x i1> @vmsleu_vx(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {912; CHECK-LABEL: vmsleu_vx:913; CHECK:       # %bb.0:914; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma915; CHECK-NEXT:    vmsleu.vx v10, v8, a0916; CHECK-NEXT:    vmand.mm v0, v10, v0917; CHECK-NEXT:    ret918  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, iXLen -1)919  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)920  ret <vscale x 4 x i1> %2921}922 923define <vscale x 4 x i1> @vmsleu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, <vscale x 4 x i32> %c, iXLen %vl) {924; CHECK-LABEL: vmsleu_vv:925; CHECK:       # %bb.0:926; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma927; CHECK-NEXT:    vmsleu.vv v12, v8, v10928; CHECK-NEXT:    vmand.mm v0, v12, v0929; CHECK-NEXT:    ret930  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %c, iXLen -1)931  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)932  ret <vscale x 4 x i1> %2933}934 935define <vscale x 4 x i1> @vmsle_vi(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, iXLen %vl) {936; CHECK-LABEL: vmsle_vi:937; CHECK:       # %bb.0:938; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma939; CHECK-NEXT:    vmsle.vi v10, v8, 5940; CHECK-NEXT:    vmand.mm v0, v10, v0941; CHECK-NEXT:    ret942  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32(<vscale x 4 x i32> %a, i32 5, iXLen -1)943  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)944  ret <vscale x 4 x i1> %2945}946 947define <vscale x 4 x i1> @vmsle_vx(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {948; CHECK-LABEL: vmsle_vx:949; CHECK:       # %bb.0:950; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma951; CHECK-NEXT:    vmsle.vx v10, v8, a0952; CHECK-NEXT:    vmand.mm v0, v10, v0953; CHECK-NEXT:    ret954  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, iXLen -1)955  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)956  ret <vscale x 4 x i1> %2957}958 959define <vscale x 4 x i1> @vmsle_vv(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, <vscale x 4 x i32> %c, iXLen %vl) {960; CHECK-LABEL: vmsle_vv:961; CHECK:       # %bb.0:962; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma963; CHECK-NEXT:    vmsle.vv v12, v8, v10964; CHECK-NEXT:    vmand.mm v0, v12, v0965; CHECK-NEXT:    ret966  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %c, iXLen -1)967  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)968  ret <vscale x 4 x i1> %2969}970 971define <vscale x 4 x i1> @vmsgtu_vi(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, iXLen %vl) {972; CHECK-LABEL: vmsgtu_vi:973; CHECK:       # %bb.0:974; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma975; CHECK-NEXT:    vmsgtu.vi v10, v8, 5976; CHECK-NEXT:    vmand.mm v0, v10, v0977; CHECK-NEXT:    ret978  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(<vscale x 4 x i32> %a, i32 5, iXLen -1)979  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)980  ret <vscale x 4 x i1> %2981}982 983define <vscale x 4 x i1> @vmsgtu_vx(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {984; CHECK-LABEL: vmsgtu_vx:985; CHECK:       # %bb.0:986; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma987; CHECK-NEXT:    vmsgtu.vx v10, v8, a0988; CHECK-NEXT:    vmand.mm v0, v10, v0989; CHECK-NEXT:    ret990  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, iXLen -1)991  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)992  ret <vscale x 4 x i1> %2993}994 995define <vscale x 4 x i1> @vmsgt_vi(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, iXLen %vl) {996; CHECK-LABEL: vmsgt_vi:997; CHECK:       # %bb.0:998; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma999; CHECK-NEXT:    vmsgt.vi v10, v8, 51000; CHECK-NEXT:    vmand.mm v0, v10, v01001; CHECK-NEXT:    ret1002  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32(<vscale x 4 x i32> %a, i32 5, iXLen -1)1003  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)1004  ret <vscale x 4 x i1> %21005}1006 1007define <vscale x 4 x i1> @vmsgt_vx(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b, i32 %c, iXLen %vl) {1008; CHECK-LABEL: vmsgt_vx:1009; CHECK:       # %bb.0:1010; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1011; CHECK-NEXT:    vmsgt.vx v10, v8, a01012; CHECK-NEXT:    vmand.mm v0, v10, v01013; CHECK-NEXT:    ret1014  %1 = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %c, iXLen -1)1015  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)1016  ret <vscale x 4 x i1> %21017}1018 1019define <vscale x 4 x i32> @vminu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1020; CHECK-LABEL: vminu_vv:1021; CHECK:       # %bb.0:1022; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1023; CHECK-NEXT:    vminu.vv v8, v8, v101024; CHECK-NEXT:    vadd.vv v8, v8, v101025; CHECK-NEXT:    ret1026  %1 = call <vscale x 4 x i32> @llvm.riscv.vminu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1027  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1028  ret <vscale x 4 x i32> %21029}1030 1031define <vscale x 4 x i32> @vminu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1032; CHECK-LABEL: vminu_vx:1033; CHECK:       # %bb.0:1034; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1035; CHECK-NEXT:    vminu.vx v10, v8, a01036; CHECK-NEXT:    vadd.vv v8, v10, v81037; CHECK-NEXT:    ret1038  %1 = call <vscale x 4 x i32> @llvm.riscv.vminu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1039  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1040  ret <vscale x 4 x i32> %21041}1042 1043define <vscale x 4 x i32> @vmin_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1044; CHECK-LABEL: vmin_vv:1045; CHECK:       # %bb.0:1046; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1047; CHECK-NEXT:    vmin.vv v8, v8, v101048; CHECK-NEXT:    vadd.vv v8, v8, v101049; CHECK-NEXT:    ret1050  %1 = call <vscale x 4 x i32> @llvm.riscv.vmin.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1051  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1052  ret <vscale x 4 x i32> %21053}1054 1055define <vscale x 4 x i32> @vmin_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1056; CHECK-LABEL: vmin_vx:1057; CHECK:       # %bb.0:1058; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1059; CHECK-NEXT:    vmin.vx v10, v8, a01060; CHECK-NEXT:    vadd.vv v8, v10, v81061; CHECK-NEXT:    ret1062  %1 = call <vscale x 4 x i32> @llvm.riscv.vmin.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1063  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1064  ret <vscale x 4 x i32> %21065}1066 1067define <vscale x 4 x i32> @vmaxu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1068; CHECK-LABEL: vmaxu_vv:1069; CHECK:       # %bb.0:1070; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1071; CHECK-NEXT:    vmaxu.vv v8, v8, v101072; CHECK-NEXT:    vadd.vv v8, v8, v101073; CHECK-NEXT:    ret1074  %1 = call <vscale x 4 x i32> @llvm.riscv.vmaxu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1075  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1076  ret <vscale x 4 x i32> %21077}1078 1079define <vscale x 4 x i32> @vmaxu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1080; CHECK-LABEL: vmaxu_vx:1081; CHECK:       # %bb.0:1082; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1083; CHECK-NEXT:    vmaxu.vx v10, v8, a01084; CHECK-NEXT:    vadd.vv v8, v10, v81085; CHECK-NEXT:    ret1086  %1 = call <vscale x 4 x i32> @llvm.riscv.vmaxu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1087  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1088  ret <vscale x 4 x i32> %21089}1090 1091define <vscale x 4 x i32> @vmax_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1092; CHECK-LABEL: vmax_vv:1093; CHECK:       # %bb.0:1094; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1095; CHECK-NEXT:    vmax.vv v8, v8, v101096; CHECK-NEXT:    vadd.vv v8, v8, v101097; CHECK-NEXT:    ret1098  %1 = call <vscale x 4 x i32> @llvm.riscv.vmax.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1099  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1100  ret <vscale x 4 x i32> %21101}1102 1103define <vscale x 4 x i32> @vmax_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1104; CHECK-LABEL: vmax_vx:1105; CHECK:       # %bb.0:1106; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1107; CHECK-NEXT:    vmax.vx v10, v8, a01108; CHECK-NEXT:    vadd.vv v8, v10, v81109; CHECK-NEXT:    ret1110  %1 = call <vscale x 4 x i32> @llvm.riscv.vmax.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1111  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1112  ret <vscale x 4 x i32> %21113}1114 1115define <vscale x 4 x i32> @vmul_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1116; CHECK-LABEL: vmul_vv:1117; CHECK:       # %bb.0:1118; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1119; CHECK-NEXT:    vmul.vv v8, v8, v101120; CHECK-NEXT:    vadd.vv v8, v8, v101121; CHECK-NEXT:    ret1122  %1 = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1123  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1124  ret <vscale x 4 x i32> %21125}1126 1127define <vscale x 4 x i32> @vmul_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1128; CHECK-LABEL: vmul_vx:1129; CHECK:       # %bb.0:1130; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1131; CHECK-NEXT:    vmul.vx v10, v8, a01132; CHECK-NEXT:    vadd.vv v8, v10, v81133; CHECK-NEXT:    ret1134  %1 = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1135  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1136  ret <vscale x 4 x i32> %21137}1138 1139define <vscale x 4 x i32> @vmulh_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1140; CHECK-LABEL: vmulh_vv:1141; CHECK:       # %bb.0:1142; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1143; CHECK-NEXT:    vmulh.vv v8, v8, v101144; CHECK-NEXT:    vadd.vv v8, v8, v101145; CHECK-NEXT:    ret1146  %1 = call <vscale x 4 x i32> @llvm.riscv.vmulh.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1147  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1148  ret <vscale x 4 x i32> %21149}1150 1151define <vscale x 4 x i32> @vmulh_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1152; CHECK-LABEL: vmulh_vx:1153; CHECK:       # %bb.0:1154; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1155; CHECK-NEXT:    vmulh.vx v10, v8, a01156; CHECK-NEXT:    vadd.vv v8, v10, v81157; CHECK-NEXT:    ret1158  %1 = call <vscale x 4 x i32> @llvm.riscv.vmulh.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1159  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1160  ret <vscale x 4 x i32> %21161}1162 1163define <vscale x 4 x i32> @vmulhu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1164; CHECK-LABEL: vmulhu_vv:1165; CHECK:       # %bb.0:1166; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1167; CHECK-NEXT:    vmulhu.vv v8, v8, v101168; CHECK-NEXT:    vadd.vv v8, v8, v101169; CHECK-NEXT:    ret1170  %1 = call <vscale x 4 x i32> @llvm.riscv.vmulhu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1171  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1172  ret <vscale x 4 x i32> %21173}1174 1175define <vscale x 4 x i32> @vmulhu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1176; CHECK-LABEL: vmulhu_vx:1177; CHECK:       # %bb.0:1178; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1179; CHECK-NEXT:    vmulhu.vx v10, v8, a01180; CHECK-NEXT:    vadd.vv v8, v10, v81181; CHECK-NEXT:    ret1182  %1 = call <vscale x 4 x i32> @llvm.riscv.vmulhu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1183  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1184  ret <vscale x 4 x i32> %21185}1186 1187define <vscale x 4 x i32> @vmulhsu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1188; CHECK-LABEL: vmulhsu_vv:1189; CHECK:       # %bb.0:1190; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1191; CHECK-NEXT:    vmulhsu.vv v8, v8, v101192; CHECK-NEXT:    vadd.vv v8, v8, v101193; CHECK-NEXT:    ret1194  %1 = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1195  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1196  ret <vscale x 4 x i32> %21197}1198 1199define <vscale x 4 x i32> @vmulhsu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1200; CHECK-LABEL: vmulhsu_vx:1201; CHECK:       # %bb.0:1202; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1203; CHECK-NEXT:    vmulhsu.vx v10, v8, a01204; CHECK-NEXT:    vadd.vv v8, v10, v81205; CHECK-NEXT:    ret1206  %1 = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1207  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1208  ret <vscale x 4 x i32> %21209}1210 1211define <vscale x 4 x i32> @vdivu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1212; CHECK-LABEL: vdivu_vv:1213; CHECK:       # %bb.0:1214; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1215; CHECK-NEXT:    vdivu.vv v8, v8, v101216; CHECK-NEXT:    vadd.vv v8, v8, v101217; CHECK-NEXT:    ret1218  %1 = call <vscale x 4 x i32> @llvm.riscv.vdivu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1219  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1220  ret <vscale x 4 x i32> %21221}1222 1223define <vscale x 4 x i32> @vdivu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1224; CHECK-LABEL: vdivu_vx:1225; CHECK:       # %bb.0:1226; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1227; CHECK-NEXT:    vdivu.vx v10, v8, a01228; CHECK-NEXT:    vadd.vv v8, v10, v81229; CHECK-NEXT:    ret1230  %1 = call <vscale x 4 x i32> @llvm.riscv.vdivu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1231  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1232  ret <vscale x 4 x i32> %21233}1234 1235define <vscale x 4 x i32> @vdiv_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1236; CHECK-LABEL: vdiv_vv:1237; CHECK:       # %bb.0:1238; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1239; CHECK-NEXT:    vdiv.vv v8, v8, v101240; CHECK-NEXT:    vadd.vv v8, v8, v101241; CHECK-NEXT:    ret1242  %1 = call <vscale x 4 x i32> @llvm.riscv.vdiv.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1243  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1244  ret <vscale x 4 x i32> %21245}1246 1247define <vscale x 4 x i32> @vdiv_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1248; CHECK-LABEL: vdiv_vx:1249; CHECK:       # %bb.0:1250; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1251; CHECK-NEXT:    vdiv.vx v10, v8, a01252; CHECK-NEXT:    vadd.vv v8, v10, v81253; CHECK-NEXT:    ret1254  %1 = call <vscale x 4 x i32> @llvm.riscv.vdiv.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1255  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1256  ret <vscale x 4 x i32> %21257}1258 1259define <vscale x 4 x i32> @vremu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1260; CHECK-LABEL: vremu_vv:1261; CHECK:       # %bb.0:1262; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1263; CHECK-NEXT:    vremu.vv v8, v8, v101264; CHECK-NEXT:    vadd.vv v8, v8, v101265; CHECK-NEXT:    ret1266  %1 = call <vscale x 4 x i32> @llvm.riscv.vremu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1267  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1268  ret <vscale x 4 x i32> %21269}1270 1271define <vscale x 4 x i32> @vremu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1272; CHECK-LABEL: vremu_vx:1273; CHECK:       # %bb.0:1274; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1275; CHECK-NEXT:    vremu.vx v10, v8, a01276; CHECK-NEXT:    vadd.vv v8, v10, v81277; CHECK-NEXT:    ret1278  %1 = call <vscale x 4 x i32> @llvm.riscv.vremu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1279  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1280  ret <vscale x 4 x i32> %21281}1282 1283define <vscale x 4 x i32> @vrem_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1284; CHECK-LABEL: vrem_vv:1285; CHECK:       # %bb.0:1286; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1287; CHECK-NEXT:    vrem.vv v8, v8, v101288; CHECK-NEXT:    vadd.vv v8, v8, v101289; CHECK-NEXT:    ret1290  %1 = call <vscale x 4 x i32> @llvm.riscv.vrem.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1291  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1292  ret <vscale x 4 x i32> %21293}1294 1295define <vscale x 4 x i32> @vrem_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1296; CHECK-LABEL: vrem_vx:1297; CHECK:       # %bb.0:1298; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1299; CHECK-NEXT:    vrem.vx v10, v8, a01300; CHECK-NEXT:    vadd.vv v8, v10, v81301; CHECK-NEXT:    ret1302  %1 = call <vscale x 4 x i32> @llvm.riscv.vrem.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1303  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1304  ret <vscale x 4 x i32> %21305}1306 1307define <vscale x 4 x i64> @vwmul_vv(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, iXLen %vl) {1308; CHECK-LABEL: vwmul_vv:1309; CHECK:       # %bb.0:1310; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1311; CHECK-NEXT:    vwmul.vv v12, v8, v91312; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1313; CHECK-NEXT:    vwmul.vv v8, v12, v121314; CHECK-NEXT:    ret1315  %1 = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b, iXLen -1)1316  %2 = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1317  ret <vscale x 4 x i64> %21318}1319 1320define <vscale x 4 x i64> @vwmul_vx(<vscale x 4 x i16> %a, i16 %b, i32 %c, iXLen %vl) {1321; CHECK-LABEL: vwmul_vx:1322; CHECK:       # %bb.0:1323; CHECK-NEXT:    vsetvli zero, a2, e16, m1, ta, ma1324; CHECK-NEXT:    vwmul.vx v12, v8, a01325; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1326; CHECK-NEXT:    vwmul.vx v8, v12, a11327; CHECK-NEXT:    ret1328  %1 = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16(<vscale x 4 x i32> poison, <vscale x 4 x i16> %a, i16 %b, iXLen -1)1329  %2 = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i64.i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %1, i32 %c, iXLen %vl)1330  ret <vscale x 4 x i64> %21331}1332 1333define <vscale x 4 x i64> @vwmulsu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1334; CHECK-LABEL: vwmulsu_vv:1335; CHECK:       # %bb.0:1336; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1337; CHECK-NEXT:    vwmulsu.vv v12, v8, v101338; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma1339; CHECK-NEXT:    vadd.vv v8, v12, v121340; CHECK-NEXT:    ret1341  %1 = call <vscale x 4 x i64> @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1342  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)1343  ret <vscale x 4 x i64> %21344}1345 1346define <vscale x 4 x i64> @vwmulsu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1347; CHECK-LABEL: vwmulsu_vx:1348; CHECK:       # %bb.0:1349; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1350; CHECK-NEXT:    vwmulsu.vx v12, v8, a01351; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma1352; CHECK-NEXT:    vadd.vv v8, v12, v121353; CHECK-NEXT:    ret1354  %1 = call <vscale x 4 x i64> @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1355  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)1356  ret <vscale x 4 x i64> %21357}1358 1359define <vscale x 4 x i64> @vwmulu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1360; CHECK-LABEL: vwmulu_vv:1361; CHECK:       # %bb.0:1362; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1363; CHECK-NEXT:    vwmulu.vv v12, v8, v101364; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma1365; CHECK-NEXT:    vadd.vv v8, v12, v121366; CHECK-NEXT:    ret1367  %1 = call <vscale x 4 x i64> @llvm.riscv.vwmulu.nxv4i64.nxv4i32.nxv4i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1368  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)1369  ret <vscale x 4 x i64> %21370}1371 1372define <vscale x 4 x i64> @vwmulu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1373; CHECK-LABEL: vwmulu_vx:1374; CHECK:       # %bb.0:1375; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1376; CHECK-NEXT:    vwmulu.vx v12, v8, a01377; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma1378; CHECK-NEXT:    vadd.vv v8, v12, v121379; CHECK-NEXT:    ret1380  %1 = call <vscale x 4 x i64> @llvm.riscv.vwmulu.nxv4i64.nxv4i32.i32(<vscale x 4 x i64> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1381  %2 = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %1, <vscale x 4 x i64> %1, iXLen %vl)1382  ret <vscale x 4 x i64> %21383}1384 1385define <vscale x 4 x i32> @vwmacc_vv(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, <vscale x 4 x i32> %d, iXLen %vl) {1386; CHECK-LABEL: vwmacc_vv:1387; CHECK:       # %bb.0:1388; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma1389; CHECK-NEXT:    vwmacc.vv v8, v10, v111390; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1391; CHECK-NEXT:    vadd.vv v8, v8, v121392; CHECK-NEXT:    ret1393  %1 = call <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.nxv4i16(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, iXLen -1, iXLen 0)1394  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %d, iXLen %vl)1395  ret <vscale x 4 x i32> %21396}1397 1398define <vscale x 4 x i32> @vmacc_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1399; CHECK-LABEL: vmacc_vv:1400; CHECK:       # %bb.0:1401; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma1402; CHECK-NEXT:    vmacc.vv v8, v8, v101403; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1404; CHECK-NEXT:    vadd.vv v8, v8, v101405; CHECK-NEXT:    ret1406  %1 = call <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1, iXLen 0)1407  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1408  ret <vscale x 4 x i32> %21409}1410 1411define <vscale x 4 x i32> @vmacc_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1412; CHECK-LABEL: vmacc_vx:1413; CHECK:       # %bb.0:1414; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma1415; CHECK-NEXT:    vmv2r.v v10, v81416; CHECK-NEXT:    vmacc.vx v10, a0, v81417; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1418; CHECK-NEXT:    vadd.vv v8, v10, v81419; CHECK-NEXT:    ret1420  %1 = call <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.i32(<vscale x 4 x i32> %a, i32 %b, <vscale x 4 x i32> %a, iXLen -1, iXLen 0)1421  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1422  ret <vscale x 4 x i32> %21423}1424 1425define <vscale x 4 x i32> @vmadd_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1426; CHECK-LABEL: vmadd_vv:1427; CHECK:       # %bb.0:1428; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma1429; CHECK-NEXT:    vmadd.vv v8, v8, v101430; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1431; CHECK-NEXT:    vadd.vv v8, v8, v101432; CHECK-NEXT:    ret1433  %1 = call <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1, iXLen 0)1434  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1435  ret <vscale x 4 x i32> %21436}1437 1438define <vscale x 4 x i32> @vmadd_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1439; CHECK-LABEL: vmadd_vx:1440; CHECK:       # %bb.0:1441; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma1442; CHECK-NEXT:    vmv2r.v v10, v81443; CHECK-NEXT:    vmadd.vx v10, a0, v81444; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1445; CHECK-NEXT:    vadd.vv v8, v10, v81446; CHECK-NEXT:    ret1447  %1 = call <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, i32 %b, <vscale x 4 x i32> %a, iXLen -1, iXLen 0)1448  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1449  ret <vscale x 4 x i32> %21450}1451 1452define <vscale x 4 x i32> @vnmsac_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1453; CHECK-LABEL: vnmsac_vv:1454; CHECK:       # %bb.0:1455; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma1456; CHECK-NEXT:    vnmsac.vv v8, v8, v101457; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1458; CHECK-NEXT:    vadd.vv v8, v8, v101459; CHECK-NEXT:    ret1460  %1 = call <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1, iXLen 0)1461  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1462  ret <vscale x 4 x i32> %21463}1464 1465define <vscale x 4 x i32> @vnmsac_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1466; CHECK-LABEL: vnmsac_vx:1467; CHECK:       # %bb.0:1468; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma1469; CHECK-NEXT:    vmv2r.v v10, v81470; CHECK-NEXT:    vnmsac.vx v10, a0, v81471; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1472; CHECK-NEXT:    vadd.vv v8, v10, v81473; CHECK-NEXT:    ret1474  %1 = call <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, i32 %b, <vscale x 4 x i32> %a, iXLen -1, iXLen 0)1475  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1476  ret <vscale x 4 x i32> %21477}1478 1479define <vscale x 4 x i32> @vnmsub_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1480; CHECK-LABEL: vnmsub_vv:1481; CHECK:       # %bb.0:1482; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma1483; CHECK-NEXT:    vnmsub.vv v8, v8, v101484; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1485; CHECK-NEXT:    vadd.vv v8, v8, v101486; CHECK-NEXT:    ret1487  %1 = call <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1, iXLen 0)1488  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1489  ret <vscale x 4 x i32> %21490}1491 1492define <vscale x 4 x i32> @vnmsub_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1493; CHECK-LABEL: vnmsub_vx:1494; CHECK:       # %bb.0:1495; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma1496; CHECK-NEXT:    vmv2r.v v10, v81497; CHECK-NEXT:    vnmsub.vx v10, a0, v81498; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1499; CHECK-NEXT:    vadd.vv v8, v10, v81500; CHECK-NEXT:    ret1501  %1 = call <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, i32 %b, <vscale x 4 x i32> %a, iXLen -1, iXLen 0)1502  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1503  ret <vscale x 4 x i32> %21504}1505 1506define <vscale x 4 x i32> @vwmacc_vx(<vscale x 4 x i32> %a, i16 %b, <vscale x 4 x i16> %c, iXLen %vl) {1507; CHECK-LABEL: vwmacc_vx:1508; CHECK:       # %bb.0:1509; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma1510; CHECK-NEXT:    vwmacc.vx v8, a0, v101511; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1512; CHECK-NEXT:    vadd.vv v8, v8, v81513; CHECK-NEXT:    ret1514  %1 = call <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.i16(<vscale x 4 x i32> %a, i16 %b, <vscale x 4 x i16> %c, iXLen -1, iXLen 0)1515  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1516  ret <vscale x 4 x i32> %21517}1518 1519define <vscale x 4 x i32> @vwmaccu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, <vscale x 4 x i32> %d, iXLen %vl) {1520; CHECK-LABEL: vwmaccu_vv:1521; CHECK:       # %bb.0:1522; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma1523; CHECK-NEXT:    vwmaccu.vv v8, v10, v111524; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1525; CHECK-NEXT:    vadd.vv v8, v8, v121526; CHECK-NEXT:    ret1527  %1 = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.nxv4i16(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, iXLen -1, iXLen 0)1528  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %d, iXLen %vl)1529  ret <vscale x 4 x i32> %21530}1531 1532define <vscale x 4 x i32> @vwmaccu_vx(<vscale x 4 x i32> %a, i16 %b, <vscale x 4 x i16> %c, <vscale x 4 x i32> %d, i32 %e, iXLen %vl) {1533; CHECK-LABEL: vwmaccu_vx:1534; CHECK:       # %bb.0:1535; CHECK-NEXT:    vsetvli zero, a2, e16, m1, tu, ma1536; CHECK-NEXT:    vwmaccu.vx v8, a0, v101537; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1538; CHECK-NEXT:    vadd.vv v8, v8, v121539; CHECK-NEXT:    ret1540  %1 = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.i16(<vscale x 4 x i32> %a, i16 %b, <vscale x 4 x i16> %c, iXLen -1, iXLen 0)1541  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %d, iXLen %vl)1542  ret <vscale x 4 x i32> %21543}1544 1545define <vscale x 4 x i32> @vwmaccsu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, iXLen %vl) {1546; CHECK-LABEL: vwmaccsu_vv:1547; CHECK:       # %bb.0:1548; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma1549; CHECK-NEXT:    vwmaccsu.vv v8, v10, v111550; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1551; CHECK-NEXT:    vadd.vv v8, v8, v81552; CHECK-NEXT:    ret1553  %1 = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.nxv4i16(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, iXLen -1, iXLen 0)1554  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1555  ret <vscale x 4 x i32> %21556}1557 1558define <vscale x 4 x i32> @vwmaccsu_vx(<vscale x 4 x i32> %a, i16 %b, <vscale x 4 x i16> %c, iXLen %vl) {1559; CHECK-LABEL: vwmaccsu_vx:1560; CHECK:       # %bb.0:1561; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma1562; CHECK-NEXT:    vwmaccsu.vx v8, a0, v101563; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1564; CHECK-NEXT:    vadd.vv v8, v8, v81565; CHECK-NEXT:    ret1566  %1 = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.i16(<vscale x 4 x i32> %a, i16 %b, <vscale x 4 x i16> %c, iXLen -1, iXLen 0)1567  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1568  ret <vscale x 4 x i32> %21569}1570 1571define <vscale x 4 x i32> @vwmaccus_vx(<vscale x 4 x i32> %a, i16 %b, <vscale x 4 x i16> %c, iXLen %vl) {1572; CHECK-LABEL: vwmaccus_vx:1573; CHECK:       # %bb.0:1574; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma1575; CHECK-NEXT:    vwmaccus.vx v8, a0, v101576; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1577; CHECK-NEXT:    vadd.vv v8, v8, v81578; CHECK-NEXT:    ret1579  %1 = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.nxv4i32.i16(<vscale x 4 x i32> %a, i16 %b, <vscale x 4 x i16> %c, iXLen -1, iXLen 0)1580  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1581  ret <vscale x 4 x i32> %21582}1583 1584define <vscale x 4 x i32> @vsaddu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1585; CHECK-LABEL: vsaddu_vv:1586; CHECK:       # %bb.0:1587; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1588; CHECK-NEXT:    vsaddu.vv v10, v8, v101589; CHECK-NEXT:    vadd.vv v8, v10, v81590; CHECK-NEXT:    ret1591  %1 = call <vscale x 4 x i32> @llvm.riscv.vsaddu(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1592  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1593  ret <vscale x 4 x i32> %21594}1595 1596define <vscale x 4 x i32> @vsaddu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1597; CHECK-LABEL: vsaddu_vx:1598; CHECK:       # %bb.0:1599; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1600; CHECK-NEXT:    vsaddu.vx v10, v8, a01601; CHECK-NEXT:    vadd.vv v8, v10, v81602; CHECK-NEXT:    ret1603  %1 = call <vscale x 4 x i32> @llvm.riscv.vsaddu(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1604  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1605  ret <vscale x 4 x i32> %21606}1607 1608define <vscale x 4 x i32> @vsaddu_vi(<vscale x 4 x i32> %a, iXLen %vl) {1609; CHECK-LABEL: vsaddu_vi:1610; CHECK:       # %bb.0:1611; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1612; CHECK-NEXT:    vsaddu.vi v10, v8, 51613; CHECK-NEXT:    vadd.vv v8, v10, v81614; CHECK-NEXT:    ret1615  %1 = call <vscale x 4 x i32> @llvm.riscv.vsaddu(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 5, iXLen -1)1616  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1617  ret <vscale x 4 x i32> %21618}1619 1620define <vscale x 4 x i32> @vsadd_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1621; CHECK-LABEL: vsadd_vv:1622; CHECK:       # %bb.0:1623; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1624; CHECK-NEXT:    vsadd.vv v10, v8, v101625; CHECK-NEXT:    vadd.vv v8, v10, v81626; CHECK-NEXT:    ret1627  %1 = call <vscale x 4 x i32> @llvm.riscv.vsadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1628  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1629  ret <vscale x 4 x i32> %21630}1631 1632define <vscale x 4 x i32> @vsadd_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1633; CHECK-LABEL: vsadd_vx:1634; CHECK:       # %bb.0:1635; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1636; CHECK-NEXT:    vsadd.vx v10, v8, a01637; CHECK-NEXT:    vadd.vv v8, v10, v81638; CHECK-NEXT:    ret1639  %1 = call <vscale x 4 x i32> @llvm.riscv.vsadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1640  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1641  ret <vscale x 4 x i32> %21642}1643 1644define <vscale x 4 x i32> @vsadd_vi(<vscale x 4 x i32> %a, iXLen %vl) {1645; CHECK-LABEL: vsadd_vi:1646; CHECK:       # %bb.0:1647; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1648; CHECK-NEXT:    vsadd.vi v10, v8, 51649; CHECK-NEXT:    vadd.vv v8, v10, v81650; CHECK-NEXT:    ret1651  %1 = call <vscale x 4 x i32> @llvm.riscv.vsadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 5, iXLen -1)1652  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1653  ret <vscale x 4 x i32> %21654}1655 1656define <vscale x 4 x i32> @vssubu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1657; CHECK-LABEL: vssubu_vv:1658; CHECK:       # %bb.0:1659; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1660; CHECK-NEXT:    vssubu.vv v10, v8, v101661; CHECK-NEXT:    vadd.vv v8, v10, v81662; CHECK-NEXT:    ret1663  %1 = call <vscale x 4 x i32> @llvm.riscv.vssubu(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1664  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1665  ret <vscale x 4 x i32> %21666}1667 1668define <vscale x 4 x i32> @vssubu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1669; CHECK-LABEL: vssubu_vx:1670; CHECK:       # %bb.0:1671; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1672; CHECK-NEXT:    vssubu.vx v10, v8, a01673; CHECK-NEXT:    vadd.vv v8, v10, v81674; CHECK-NEXT:    ret1675  %1 = call <vscale x 4 x i32> @llvm.riscv.vssubu(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1676  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1677  ret <vscale x 4 x i32> %21678}1679 1680define <vscale x 4 x i32> @vssub_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1681; CHECK-LABEL: vssub_vv:1682; CHECK:       # %bb.0:1683; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1684; CHECK-NEXT:    vssub.vv v10, v8, v101685; CHECK-NEXT:    vadd.vv v8, v10, v81686; CHECK-NEXT:    ret1687  %1 = call <vscale x 4 x i32> @llvm.riscv.vssub(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)1688  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1689  ret <vscale x 4 x i32> %21690}1691 1692define <vscale x 4 x i32> @vssub_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1693; CHECK-LABEL: vssub_vx:1694; CHECK:       # %bb.0:1695; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1696; CHECK-NEXT:    vssub.vx v10, v8, a01697; CHECK-NEXT:    vadd.vv v8, v10, v81698; CHECK-NEXT:    ret1699  %1 = call <vscale x 4 x i32> @llvm.riscv.vssub(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)1700  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1701  ret <vscale x 4 x i32> %21702}1703 1704define <vscale x 4 x i32> @vsmul_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1705; CHECK-LABEL: vsmul_vv:1706; CHECK:       # %bb.0:1707; CHECK-NEXT:    csrwi vxrm, 01708; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1709; CHECK-NEXT:    vsmul.vv v8, v8, v101710; CHECK-NEXT:    vadd.vv v8, v8, v101711; CHECK-NEXT:    ret1712  %1 = call <vscale x 4 x i32> @llvm.riscv.vsmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 0, iXLen -1)1713  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1714  ret <vscale x 4 x i32> %21715}1716 1717define <vscale x 4 x i32> @vsmul_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {1718; CHECK-LABEL: vsmul_vx:1719; CHECK:       # %bb.0:1720; CHECK-NEXT:    csrwi vxrm, 01721; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1722; CHECK-NEXT:    vsmul.vx v10, v8, a01723; CHECK-NEXT:    vadd.vv v8, v10, v81724; CHECK-NEXT:    ret1725  %1 = call <vscale x 4 x i32> @llvm.riscv.vsmul.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen 0, iXLen -1)1726  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1727  ret <vscale x 4 x i32> %21728}1729 1730define <vscale x 4 x i32> @vssrl_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1731; CHECK-LABEL: vssrl_vv:1732; CHECK:       # %bb.0:1733; CHECK-NEXT:    csrwi vxrm, 01734; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1735; CHECK-NEXT:    vssrl.vv v8, v8, v101736; CHECK-NEXT:    vadd.vv v8, v8, v101737; CHECK-NEXT:    ret1738  %1 = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 0, iXLen -1)1739  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1740  ret <vscale x 4 x i32> %21741}1742 1743define <vscale x 4 x i32> @vssrl_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {1744; CHECK-LABEL: vssrl_vx:1745; CHECK:       # %bb.0:1746; CHECK-NEXT:    csrwi vxrm, 01747; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1748; CHECK-NEXT:    vssrl.vx v10, v8, a01749; CHECK-NEXT:    vadd.vv v8, v10, v81750; CHECK-NEXT:    ret1751  %1 = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen 0, iXLen -1)1752  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1753  ret <vscale x 4 x i32> %21754}1755 1756define <vscale x 4 x i32> @vssrl_vi(<vscale x 4 x i32> %a, iXLen %vl) {1757; CHECK-LABEL: vssrl_vi:1758; CHECK:       # %bb.0:1759; CHECK-NEXT:    csrwi vxrm, 01760; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1761; CHECK-NEXT:    vssrl.vi v10, v8, 51762; CHECK-NEXT:    vadd.vv v8, v10, v81763; CHECK-NEXT:    ret1764  %1 = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen 0, iXLen -1)1765  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1766  ret <vscale x 4 x i32> %21767}1768 1769define <vscale x 4 x i32> @vssra_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {1770; CHECK-LABEL: vssra_vv:1771; CHECK:       # %bb.0:1772; CHECK-NEXT:    csrwi vxrm, 01773; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1774; CHECK-NEXT:    vssra.vv v8, v8, v101775; CHECK-NEXT:    vadd.vv v8, v8, v101776; CHECK-NEXT:    ret1777  %1 = call <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 0, iXLen -1)1778  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)1779  ret <vscale x 4 x i32> %21780}1781 1782define <vscale x 4 x i32> @vssra_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {1783; CHECK-LABEL: vssra_vx:1784; CHECK:       # %bb.0:1785; CHECK-NEXT:    csrwi vxrm, 01786; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1787; CHECK-NEXT:    vssra.vx v10, v8, a01788; CHECK-NEXT:    vadd.vv v8, v10, v81789; CHECK-NEXT:    ret1790  %1 = call <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen 0, iXLen -1)1791  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1792  ret <vscale x 4 x i32> %21793}1794 1795define <vscale x 4 x i32> @vssra_vi(<vscale x 4 x i32> %a, iXLen %vl) {1796; CHECK-LABEL: vssra_vi:1797; CHECK:       # %bb.0:1798; CHECK-NEXT:    csrwi vxrm, 01799; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1800; CHECK-NEXT:    vssra.vi v10, v8, 51801; CHECK-NEXT:    vadd.vv v8, v10, v81802; CHECK-NEXT:    ret1803  %1 = call <vscale x 4 x i32> @llvm.riscv.vssra.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen 0, iXLen -1)1804  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1805  ret <vscale x 4 x i32> %21806}1807 1808define <vscale x 4 x i32> @vnclipu_vv(<vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen %vl) {1809; CHECK-LABEL: vnclipu_vv:1810; CHECK:       # %bb.0:1811; CHECK-NEXT:    csrwi vxrm, 01812; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1813; CHECK-NEXT:    vnclipu.wv v14, v8, v121814; CHECK-NEXT:    vadd.vv v8, v14, v141815; CHECK-NEXT:    ret1816  %1 = call <vscale x 4 x i32> @llvm.riscv.vnclipu(<vscale x 4 x i32> poison, <vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen 0, iXLen -1)1817  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1818  ret <vscale x 4 x i32> %21819}1820 1821define <vscale x 4 x i32> @vnclipu_vx(<vscale x 4 x i64> %a, iXLen %b, iXLen %vl) {1822; CHECK-LABEL: vnclipu_vx:1823; CHECK:       # %bb.0:1824; CHECK-NEXT:    csrwi vxrm, 01825; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1826; CHECK-NEXT:    vnclipu.wx v12, v8, a01827; CHECK-NEXT:    vadd.vv v8, v12, v121828; CHECK-NEXT:    ret1829  %1 = call <vscale x 4 x i32> @llvm.riscv.vnclipu(<vscale x 4 x i32> poison, <vscale x 4 x i64> %a, iXLen %b, iXLen 0, iXLen -1)1830  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1831  ret <vscale x 4 x i32> %21832}1833 1834define <vscale x 4 x i32> @vnclipu_vi(<vscale x 4 x i64> %a, iXLen %vl) {1835; CHECK-LABEL: vnclipu_vi:1836; CHECK:       # %bb.0:1837; CHECK-NEXT:    csrwi vxrm, 01838; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1839; CHECK-NEXT:    vnclipu.wi v12, v8, 51840; CHECK-NEXT:    vadd.vv v8, v12, v121841; CHECK-NEXT:    ret1842  %1 = call <vscale x 4 x i32> @llvm.riscv.vnclipu(<vscale x 4 x i32> poison, <vscale x 4 x i64> %a, iXLen 5, iXLen 0, iXLen -1)1843  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1844  ret <vscale x 4 x i32> %21845}1846 1847define <vscale x 4 x i32> @vnclip_vv(<vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen %vl) {1848; CHECK-LABEL: vnclip_vv:1849; CHECK:       # %bb.0:1850; CHECK-NEXT:    csrwi vxrm, 01851; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1852; CHECK-NEXT:    vnclip.wv v14, v8, v121853; CHECK-NEXT:    vadd.vv v8, v14, v141854; CHECK-NEXT:    ret1855  %1 = call <vscale x 4 x i32> @llvm.riscv.vnclip(<vscale x 4 x i32> poison, <vscale x 4 x i64> %a, <vscale x 4 x i32> %b, iXLen 0, iXLen -1)1856  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1857  ret <vscale x 4 x i32> %21858}1859 1860define <vscale x 4 x i32> @vnclip_vx(<vscale x 4 x i64> %a, iXLen %b, iXLen %vl) {1861; CHECK-LABEL: vnclip_vx:1862; CHECK:       # %bb.0:1863; CHECK-NEXT:    csrwi vxrm, 01864; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1865; CHECK-NEXT:    vnclip.wx v12, v8, a01866; CHECK-NEXT:    vadd.vv v8, v12, v121867; CHECK-NEXT:    ret1868  %1 = call <vscale x 4 x i32> @llvm.riscv.vnclip(<vscale x 4 x i32> poison, <vscale x 4 x i64> %a, iXLen %b, iXLen 0, iXLen -1)1869  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1870  ret <vscale x 4 x i32> %21871}1872 1873define <vscale x 4 x i32> @vnclip_vi(<vscale x 4 x i64> %a, iXLen %vl) {1874; CHECK-LABEL: vnclip_vi:1875; CHECK:       # %bb.0:1876; CHECK-NEXT:    csrwi vxrm, 01877; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1878; CHECK-NEXT:    vnclip.wi v12, v8, 51879; CHECK-NEXT:    vadd.vv v8, v12, v121880; CHECK-NEXT:    ret1881  %1 = call <vscale x 4 x i32> @llvm.riscv.vnclip(<vscale x 4 x i32> poison, <vscale x 4 x i64> %a, iXLen 5, iXLen 0, iXLen -1)1882  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1883  ret <vscale x 4 x i32> %21884}1885 1886define <vscale x 4 x i32> @vmv_v_i(<vscale x 4 x i32> %a, i32 %x, iXLen %vl) {1887; CHECK-LABEL: vmv_v_i:1888; CHECK:       # %bb.0:1889; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1890; CHECK-NEXT:    vmv.v.i v10, 51891; CHECK-NEXT:    vadd.vv v8, v10, v81892; CHECK-NEXT:    ret1893  %1 = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(<vscale x 4 x i32> poison, i32 5, iXLen -1)1894  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1895  ret <vscale x 4 x i32> %21896}1897 1898define <vscale x 4 x i32> @vmv_v_x(<vscale x 4 x i32> %a, i32 %x, iXLen %vl) {1899; CHECK-LABEL: vmv_v_x:1900; CHECK:       # %bb.0:1901; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1902; CHECK-NEXT:    vmv.v.x v10, a01903; CHECK-NEXT:    vadd.vv v8, v10, v81904; CHECK-NEXT:    ret1905  %1 = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(<vscale x 4 x i32> poison, i32 %x, iXLen -1)1906  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)1907  ret <vscale x 4 x i32> %21908}1909 1910; The vmv.v.v is optimized away if we use a vadd as the user.1911define <vscale x 1 x i8> @vmv_v_v(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, iXLen %vl) {1912; CHECK-LABEL: vmv_v_v:1913; CHECK:       # %bb.0:1914; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma1915; CHECK-NEXT:    vmv.v.v v8, v91916; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma1917; CHECK-NEXT:    vmerge.vvm v8, v8, v10, v01918; CHECK-NEXT:    ret1919  %2 = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, iXLen -1)1920  %3 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(<vscale x 1 x i8> poison, <vscale x 1 x i8> %2, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, iXLen %vl)1921  ret <vscale x 1 x i8> %31922}1923 1924define <vscale x 4 x i32> @vwsll_vi(<vscale x 4 x i16> %a, iXLen %vl) {1925; CHECK-LABEL: vwsll_vi:1926; CHECK:       # %bb.0:1927; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1928; CHECK-NEXT:    vwsll.vi v10, v8, 11929; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1930; CHECK-NEXT:    vadd.vv v8, v10, v101931; CHECK-NEXT:    ret1932  %1 = call <vscale x 4 x i32> @llvm.riscv.vwsll.nxv4i32.nxv4i16(<vscale x 4 x i32> poison, <vscale x 4 x i16> %a, iXLen 1, iXLen -1)1933  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1934  ret <vscale x 4 x i32> %21935}1936 1937define <vscale x 4 x i32> @vwsll_vx(<vscale x 4 x i16> %a, iXLen %b, iXLen %vl) {1938; CHECK-LABEL: vwsll_vx:1939; CHECK:       # %bb.0:1940; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1941; CHECK-NEXT:    vwsll.vx v10, v8, a01942; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1943; CHECK-NEXT:    vadd.vv v8, v10, v101944; CHECK-NEXT:    ret1945  %1 = call <vscale x 4 x i32> @llvm.riscv.vwsll.nxv4i32.nxv4i16(<vscale x 4 x i32> poison, <vscale x 4 x i16> %a, iXLen %b, iXLen -1)1946  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1947  ret <vscale x 4 x i32> %21948}1949 1950define <vscale x 4 x i32> @vwsll_vv(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, iXLen %vl) {1951; CHECK-LABEL: vwsll_vv:1952; CHECK:       # %bb.0:1953; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1954; CHECK-NEXT:    vwsll.vv v10, v8, v91955; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma1956; CHECK-NEXT:    vadd.vv v8, v10, v101957; CHECK-NEXT:    ret1958  %1 = call <vscale x 4 x i32> @llvm.riscv.vwsll.nxv4i32.nxv4i16(<vscale x 4 x i32> poison, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b, iXLen -1)1959  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)1960  ret <vscale x 4 x i32> %21961}1962 1963define <vscale x 1 x i32> @vmand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {1964; CHECK-LABEL: vmand_mm:1965; CHECK:       # %bb.0:1966; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1967; CHECK-NEXT:    vmand.mm v8, v0, v81968; CHECK-NEXT:    vmand.mm v0, v0, v81969; CHECK-NEXT:    vmv1r.v v8, v91970; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu1971; CHECK-NEXT:    vadd.vv v8, v9, v9, v0.t1972; CHECK-NEXT:    ret1973  %1 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)1974  %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)1975  %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)1976  ret <vscale x 1 x i32> %31977}1978 1979define <vscale x 1 x i32> @vmnand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {1980; CHECK-LABEL: vmnand_mm:1981; CHECK:       # %bb.0:1982; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1983; CHECK-NEXT:    vmnand.mm v8, v0, v81984; CHECK-NEXT:    vmand.mm v0, v0, v81985; CHECK-NEXT:    vmv1r.v v8, v91986; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu1987; CHECK-NEXT:    vadd.vv v8, v9, v9, v0.t1988; CHECK-NEXT:    ret1989  %1 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)1990  %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)1991  %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)1992  ret <vscale x 1 x i32> %31993}1994 1995define <vscale x 1 x i32> @vmandn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {1996; CHECK-LABEL: vmandn_mm:1997; CHECK:       # %bb.0:1998; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1999; CHECK-NEXT:    vmandn.mm v8, v0, v82000; CHECK-NEXT:    vmand.mm v0, v0, v82001; CHECK-NEXT:    vmv1r.v v8, v92002; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu2003; CHECK-NEXT:    vadd.vv v8, v9, v9, v0.t2004; CHECK-NEXT:    ret2005  %1 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)2006  %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)2007  %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)2008  ret <vscale x 1 x i32> %32009}2010 2011define <vscale x 1 x i32> @vmxor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {2012; CHECK-LABEL: vmxor_mm:2013; CHECK:       # %bb.0:2014; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma2015; CHECK-NEXT:    vmxor.mm v8, v0, v82016; CHECK-NEXT:    vmand.mm v0, v0, v82017; CHECK-NEXT:    vmv1r.v v8, v92018; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu2019; CHECK-NEXT:    vadd.vv v8, v9, v9, v0.t2020; CHECK-NEXT:    ret2021  %1 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)2022  %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)2023  %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)2024  ret <vscale x 1 x i32> %32025}2026 2027define <vscale x 1 x i32> @vmor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {2028; CHECK-LABEL: vmor_mm:2029; CHECK:       # %bb.0:2030; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma2031; CHECK-NEXT:    vmor.mm v8, v0, v82032; CHECK-NEXT:    vmand.mm v0, v0, v82033; CHECK-NEXT:    vmv1r.v v8, v92034; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu2035; CHECK-NEXT:    vadd.vv v8, v9, v9, v0.t2036; CHECK-NEXT:    ret2037  %1 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)2038  %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)2039  %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)2040  ret <vscale x 1 x i32> %32041}2042 2043 2044define <vscale x 1 x i32> @vmnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {2045; CHECK-LABEL: vmnor_mm:2046; CHECK:       # %bb.0:2047; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma2048; CHECK-NEXT:    vmnor.mm v8, v0, v82049; CHECK-NEXT:    vmand.mm v0, v0, v82050; CHECK-NEXT:    vmv1r.v v8, v92051; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu2052; CHECK-NEXT:    vadd.vv v8, v9, v9, v0.t2053; CHECK-NEXT:    ret2054  %1 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)2055  %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)2056  %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)2057  ret <vscale x 1 x i32> %32058}2059 2060define <vscale x 1 x i32> @vmorn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {2061; CHECK-LABEL: vmorn_mm:2062; CHECK:       # %bb.0:2063; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma2064; CHECK-NEXT:    vmorn.mm v8, v0, v82065; CHECK-NEXT:    vmand.mm v0, v0, v82066; CHECK-NEXT:    vmv1r.v v8, v92067; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu2068; CHECK-NEXT:    vadd.vv v8, v9, v9, v0.t2069; CHECK-NEXT:    ret2070  %1 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)2071  %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)2072  %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)2073  ret <vscale x 1 x i32> %32074}2075 2076define <vscale x 1 x i32> @vmxnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {2077; CHECK-LABEL: vmxnor_mm:2078; CHECK:       # %bb.0:2079; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma2080; CHECK-NEXT:    vmxnor.mm v8, v0, v82081; CHECK-NEXT:    vmand.mm v0, v0, v82082; CHECK-NEXT:    vmv1r.v v8, v92083; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu2084; CHECK-NEXT:    vadd.vv v8, v9, v9, v0.t2085; CHECK-NEXT:    ret2086  %1 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)2087  %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)2088  %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)2089  ret <vscale x 1 x i32> %32090}2091 2092define <vscale x 1 x i32> @vmsbf_m(<vscale x 1 x i1> %a, <vscale x 1 x i32> %c, iXLen %vl) {2093; CHECK-LABEL: vmsbf_m:2094; CHECK:       # %bb.0:2095; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma2096; CHECK-NEXT:    vmsbf.m v9, v02097; CHECK-NEXT:    vmand.mm v0, v0, v92098; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu2099; CHECK-NEXT:    vadd.vv v8, v8, v8, v0.t2100; CHECK-NEXT:    ret2101  %1 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(<vscale x 1 x i1> %a, iXLen -1)2102  %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)2103  %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)2104  ret <vscale x 1 x i32> %32105}2106 2107define <vscale x 1 x i32> @vmsif_m(<vscale x 1 x i1> %a, <vscale x 1 x i32> %c, iXLen %vl) {2108; CHECK-LABEL: vmsif_m:2109; CHECK:       # %bb.0:2110; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma2111; CHECK-NEXT:    vmsif.m v9, v02112; CHECK-NEXT:    vmand.mm v0, v0, v92113; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu2114; CHECK-NEXT:    vadd.vv v8, v8, v8, v0.t2115; CHECK-NEXT:    ret2116  %1 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(<vscale x 1 x i1> %a, iXLen -1)2117  %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)2118  %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)2119  ret <vscale x 1 x i32> %32120}2121 2122define <vscale x 1 x i32> @vmsof_m(<vscale x 1 x i1> %a, <vscale x 1 x i32> %c, iXLen %vl) {2123; CHECK-LABEL: vmsof_m:2124; CHECK:       # %bb.0:2125; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma2126; CHECK-NEXT:    vmsof.m v9, v02127; CHECK-NEXT:    vmand.mm v0, v0, v92128; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, mu2129; CHECK-NEXT:    vadd.vv v8, v8, v8, v0.t2130; CHECK-NEXT:    ret2131  %1 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(<vscale x 1 x i1> %a, iXLen -1)2132  %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)2133  %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)2134  ret <vscale x 1 x i32> %32135}2136 2137define <vscale x 4 x i32> @viota_m(<vscale x 4 x i1> %a, <vscale x 4 x i32> %c, iXLen %vl) {2138; CHECK-LABEL: viota_m:2139; CHECK:       # %bb.0:2140; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2141; CHECK-NEXT:    viota.m v10, v02142; CHECK-NEXT:    vadd.vv v8, v10, v82143; CHECK-NEXT:    ret2144  %1 = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %a, iXLen -1)2145  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %c, iXLen %vl)2146  ret <vscale x 4 x i32> %22147}2148 2149define <vscale x 4 x i32> @vid.v(<vscale x 4 x i32> %c, iXLen %vl) {2150; CHECK-LABEL: vid.v:2151; CHECK:       # %bb.0:2152; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2153; CHECK-NEXT:    vid.v v102154; CHECK-NEXT:    vadd.vv v8, v10, v82155; CHECK-NEXT:    ret2156  %1 = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(<vscale x 4 x i32> poison, iXLen -1)2157  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %c, iXLen %vl)2158  ret <vscale x 4 x i32> %22159}2160 2161define <vscale x 4 x i32> @vslideup_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {2162; CHECK-LABEL: vslideup_vx:2163; CHECK:       # %bb.0:2164; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2165; CHECK-NEXT:    vslideup.vx v10, v8, a02166; CHECK-NEXT:    vadd.vv v8, v10, v102167; CHECK-NEXT:    ret2168  %1 = call <vscale x 4 x i32> @llvm.riscv.vslideup(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1, iXLen 3)2169  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)2170  ret <vscale x 4 x i32> %22171}2172 2173define <vscale x 4 x i32> @vslideup_vi(<vscale x 4 x i32> %a, iXLen %vl) {2174; CHECK-LABEL: vslideup_vi:2175; CHECK:       # %bb.0:2176; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2177; CHECK-NEXT:    vslideup.vi v10, v8, 22178; CHECK-NEXT:    vadd.vv v8, v10, v102179; CHECK-NEXT:    ret2180  %1 = call <vscale x 4 x i32> @llvm.riscv.vslideup(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 2, iXLen -1, iXLen 3)2181  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)2182  ret <vscale x 4 x i32> %22183}2184 2185define <vscale x 4 x i32> @vslidedown_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {2186; CHECK-LABEL: vslidedown_vx:2187; CHECK:       # %bb.0:2188; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2189; CHECK-NEXT:    vslidedown.vx v8, v8, a02190; CHECK-NEXT:    vadd.vv v8, v8, v82191; CHECK-NEXT:    ret2192  %1 = call <vscale x 4 x i32> @llvm.riscv.vslidedown(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1, iXLen 3)2193  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)2194  ret <vscale x 4 x i32> %22195}2196 2197define <vscale x 4 x i32> @vslidedown_vi(<vscale x 4 x i32> %a, iXLen %vl) {2198; CHECK-LABEL: vslidedown_vi:2199; CHECK:       # %bb.0:2200; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2201; CHECK-NEXT:    vslidedown.vi v8, v8, 22202; CHECK-NEXT:    vadd.vv v8, v8, v82203; CHECK-NEXT:    ret2204  %1 = call <vscale x 4 x i32> @llvm.riscv.vslidedown(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 2, iXLen -1, iXLen 3)2205  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)2206  ret <vscale x 4 x i32> %22207}2208 2209define <vscale x 4 x i32> @vslide1up_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {2210; CHECK-LABEL: vslide1up_vx:2211; CHECK:       # %bb.0:2212; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2213; CHECK-NEXT:    vslide1up.vx v10, v8, a02214; CHECK-NEXT:    vadd.vv v8, v10, v102215; CHECK-NEXT:    ret2216  %1 = call <vscale x 4 x i32> @llvm.riscv.vslide1up(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)2217  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)2218  ret <vscale x 4 x i32> %22219}2220 2221define <vscale x 4 x float> @vfslide1up_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2222; CHECK-LABEL: vfslide1up_vf:2223; CHECK:       # %bb.0:2224; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2225; CHECK-NEXT:    vfslide1up.vf v10, v8, fa02226; CHECK-NEXT:    vfadd.vv v8, v10, v102227; CHECK-NEXT:    ret2228  %1 = call <vscale x 4 x float> @llvm.riscv.vfslide1up(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen -1)2229  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %1, iXLen 7, iXLen %vl)2230  ret <vscale x 4 x float> %22231}2232 2233; Negative test – not safe to reduce vl2234 2235define <vscale x 4 x i32> @vslide1down_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {2236; CHECK-LABEL: vslide1down_vx:2237; CHECK:       # %bb.0:2238; CHECK-NEXT:    vsetvli a2, zero, e32, m2, ta, ma2239; CHECK-NEXT:    vslide1down.vx v8, v8, a02240; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2241; CHECK-NEXT:    vadd.vv v8, v8, v82242; CHECK-NEXT:    ret2243  %1 = call <vscale x 4 x i32> @llvm.riscv.vslide1down(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)2244  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)2245  ret <vscale x 4 x i32> %22246}2247 2248; Negative test – not safe to reduce vl2249 2250define <vscale x 4 x float> @vfslide1down_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2251; CHECK-LABEL: vfslide1down_vf:2252; CHECK:       # %bb.0:2253; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma2254; CHECK-NEXT:    vfslide1down.vf v8, v8, fa02255; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2256; CHECK-NEXT:    vfadd.vv v8, v8, v82257; CHECK-NEXT:    ret2258  %1 = call <vscale x 4 x float> @llvm.riscv.vfslide1down(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen -1)2259  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %1, iXLen 7, iXLen %vl)2260  ret <vscale x 4 x float> %22261}2262 2263define <vscale x 4 x float> @vfadd_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2264; CHECK-LABEL: vfadd_vv:2265; CHECK:       # %bb.0:2266; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2267; CHECK-NEXT:    vfadd.vv v8, v8, v102268; CHECK-NEXT:    vfadd.vv v8, v8, v102269; CHECK-NEXT:    ret2270  %1 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen 7, iXLen -1)2271  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %b, iXLen 7, iXLen %vl)2272  ret <vscale x 4 x float> %22273}2274 2275define <vscale x 4 x float> @vfadd_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2276; CHECK-LABEL: vfadd_vf:2277; CHECK:       # %bb.0:2278; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2279; CHECK-NEXT:    vfadd.vf v10, v8, fa02280; CHECK-NEXT:    vfadd.vv v8, v10, v82281; CHECK-NEXT:    ret2282  %1 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)2283  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2284  ret <vscale x 4 x float> %22285}2286 2287define <vscale x 4 x float> @vfsub_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2288; CHECK-LABEL: vfsub_vv:2289; CHECK:       # %bb.0:2290; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2291; CHECK-NEXT:    vfsub.vv v8, v8, v102292; CHECK-NEXT:    vfadd.vv v8, v8, v102293; CHECK-NEXT:    ret2294  %1 = call <vscale x 4 x float> @llvm.riscv.vfsub.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen 7, iXLen -1)2295  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %b, iXLen 7, iXLen %vl)2296  ret <vscale x 4 x float> %22297}2298 2299define <vscale x 4 x float> @vfsub_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2300; CHECK-LABEL: vfsub_vf:2301; CHECK:       # %bb.0:2302; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2303; CHECK-NEXT:    vfsub.vf v10, v8, fa02304; CHECK-NEXT:    vfadd.vv v8, v10, v82305; CHECK-NEXT:    ret2306  %1 = call <vscale x 4 x float> @llvm.riscv.vfsub.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)2307  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2308  ret <vscale x 4 x float> %22309}2310 2311define <vscale x 4 x float> @vfrsub_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2312; CHECK-LABEL: vfrsub_vf:2313; CHECK:       # %bb.0:2314; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2315; CHECK-NEXT:    vfrsub.vf v10, v8, fa02316; CHECK-NEXT:    vfadd.vv v8, v10, v82317; CHECK-NEXT:    ret2318  %1 = call <vscale x 4 x float> @llvm.riscv.vfrsub.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)2319  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2320  ret <vscale x 4 x float> %22321}2322 2323define <vscale x 4 x double> @vfwadd_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2324; CHECK-LABEL: vfwadd_vv:2325; CHECK:       # %bb.0:2326; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2327; CHECK-NEXT:    vfwadd.vv v12, v8, v102328; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma2329; CHECK-NEXT:    vfadd.vv v8, v12, v122330; CHECK-NEXT:    ret2331  %1 = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32(<vscale x 4 x double> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen 7, iXLen -1)2332  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %1, iXLen 7, iXLen %vl)2333  ret <vscale x 4 x double> %22334}2335 2336define <vscale x 4 x double> @vfwadd_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2337; CHECK-LABEL: vfwadd_vf:2338; CHECK:       # %bb.0:2339; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2340; CHECK-NEXT:    vfwadd.vf v12, v8, fa02341; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma2342; CHECK-NEXT:    vfadd.vv v8, v12, v122343; CHECK-NEXT:    ret2344  %1 = call <vscale x 4 x double> @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32(<vscale x 4 x double> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)2345  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %1, iXLen 7, iXLen %vl)2346  ret <vscale x 4 x double> %22347}2348 2349define <vscale x 4 x double> @vfwsub_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2350; CHECK-LABEL: vfwsub_vv:2351; CHECK:       # %bb.0:2352; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2353; CHECK-NEXT:    vfwsub.vv v12, v8, v102354; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma2355; CHECK-NEXT:    vfadd.vv v8, v12, v122356; CHECK-NEXT:    ret2357  %1 = call <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f64.nxv4f32.nxv4f32(<vscale x 4 x double> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen 7, iXLen -1)2358  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %1, iXLen 7, iXLen %vl)2359  ret <vscale x 4 x double> %22360}2361 2362define <vscale x 4 x double> @vfwsub_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2363; CHECK-LABEL: vfwsub_vf:2364; CHECK:       # %bb.0:2365; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2366; CHECK-NEXT:    vfwsub.vf v12, v8, fa02367; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma2368; CHECK-NEXT:    vfadd.vv v8, v12, v122369; CHECK-NEXT:    ret2370  %1 = call <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f64.nxv4f32.f32(<vscale x 4 x double> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)2371  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %1, iXLen 7, iXLen %vl)2372  ret <vscale x 4 x double> %22373}2374 2375define <vscale x 4 x double> @vfwadd_wv(<vscale x 4 x double> %a, <vscale x 4 x float> %b, iXLen %vl) {2376; CHECK-LABEL: vfwadd_wv:2377; CHECK:       # %bb.0:2378; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2379; CHECK-NEXT:    vfwadd.wv v8, v8, v122380; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma2381; CHECK-NEXT:    vfadd.vv v8, v8, v82382; CHECK-NEXT:    ret2383  %1 = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32.nxv4f32(<vscale x 4 x double> poison, <vscale x 4 x double> %a, <vscale x 4 x float> %b, iXLen 7, iXLen -1)2384  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %1, iXLen 7, iXLen %vl)2385  ret <vscale x 4 x double> %22386}2387 2388define <vscale x 4 x double> @vfwadd_wf(<vscale x 4 x double> %a, float %b, iXLen %vl) {2389; CHECK-LABEL: vfwadd_wf:2390; CHECK:       # %bb.0:2391; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2392; CHECK-NEXT:    vfwadd.wf v8, v8, fa02393; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma2394; CHECK-NEXT:    vfadd.vv v8, v8, v82395; CHECK-NEXT:    ret2396  %1 = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32.f32(<vscale x 4 x double> poison, <vscale x 4 x double> %a, float %b, iXLen 7, iXLen -1)2397  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %1, iXLen 7, iXLen %vl)2398  ret <vscale x 4 x double> %22399}2400 2401define <vscale x 4 x double> @vfwsub_wv(<vscale x 4 x double> %a, <vscale x 4 x float> %b, iXLen %vl) {2402; CHECK-LABEL: vfwsub_wv:2403; CHECK:       # %bb.0:2404; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2405; CHECK-NEXT:    vfwsub.wv v8, v8, v122406; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma2407; CHECK-NEXT:    vfadd.vv v8, v8, v82408; CHECK-NEXT:    ret2409  %1 = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32.nxv4f32(<vscale x 4 x double> poison, <vscale x 4 x double> %a, <vscale x 4 x float> %b, iXLen 7, iXLen -1)2410  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %1, iXLen 7, iXLen %vl)2411  ret <vscale x 4 x double> %22412}2413 2414define <vscale x 4 x double> @vfwsub_wf(<vscale x 4 x double> %a, float %b, iXLen %vl) {2415; CHECK-LABEL: vfwsub_wf:2416; CHECK:       # %bb.0:2417; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2418; CHECK-NEXT:    vfwsub.wf v8, v8, fa02419; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma2420; CHECK-NEXT:    vfadd.vv v8, v8, v82421; CHECK-NEXT:    ret2422  %1 = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32.f32(<vscale x 4 x double> poison, <vscale x 4 x double> %a, float %b, iXLen 7, iXLen -1)2423  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %1, iXLen 7, iXLen %vl)2424  ret <vscale x 4 x double> %22425}2426 2427define <vscale x 4 x float> @vfmul_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2428; CHECK-LABEL: vfmul_vv:2429; CHECK:       # %bb.0:2430; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2431; CHECK-NEXT:    vfmul.vv v8, v8, v102432; CHECK-NEXT:    vfadd.vv v8, v8, v102433; CHECK-NEXT:    ret2434  %1 = call <vscale x 4 x float> @llvm.riscv.vfmul.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen 7, iXLen -1)2435  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %b, iXLen 7, iXLen %vl)2436  ret <vscale x 4 x float> %22437}2438 2439define <vscale x 4 x float> @vfmul_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2440; CHECK-LABEL: vfmul_vf:2441; CHECK:       # %bb.0:2442; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2443; CHECK-NEXT:    vfmul.vf v10, v8, fa02444; CHECK-NEXT:    vfadd.vv v8, v10, v82445; CHECK-NEXT:    ret2446  %1 = call <vscale x 4 x float> @llvm.riscv.vfmul.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)2447  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2448  ret <vscale x 4 x float> %22449}2450 2451define <vscale x 4 x float> @vfdiv_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2452; CHECK-LABEL: vfdiv_vv:2453; CHECK:       # %bb.0:2454; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2455; CHECK-NEXT:    vfdiv.vv v8, v8, v102456; CHECK-NEXT:    vfadd.vv v8, v8, v102457; CHECK-NEXT:    ret2458  %1 = call <vscale x 4 x float> @llvm.riscv.vfdiv.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen 7, iXLen -1)2459  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %b, iXLen 7, iXLen %vl)2460  ret <vscale x 4 x float> %22461}2462 2463define <vscale x 4 x float> @vfdiv_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2464; CHECK-LABEL: vfdiv_vf:2465; CHECK:       # %bb.0:2466; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2467; CHECK-NEXT:    vfdiv.vf v10, v8, fa02468; CHECK-NEXT:    vfadd.vv v8, v10, v82469; CHECK-NEXT:    ret2470  %1 = call <vscale x 4 x float> @llvm.riscv.vfdiv.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)2471  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2472  ret <vscale x 4 x float> %22473}2474 2475define <vscale x 4 x float> @vfrdiv_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2476; CHECK-LABEL: vfrdiv_vf:2477; CHECK:       # %bb.0:2478; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2479; CHECK-NEXT:    vfrdiv.vf v10, v8, fa02480; CHECK-NEXT:    vfadd.vv v8, v10, v82481; CHECK-NEXT:    ret2482  %1 = call <vscale x 4 x float> @llvm.riscv.vfrdiv.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)2483  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2484  ret <vscale x 4 x float> %22485}2486 2487define <vscale x 4 x double> @vfwmul_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2488; CHECK-LABEL: vfwmul_vv:2489; CHECK:       # %bb.0:2490; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2491; CHECK-NEXT:    vfwmul.vv v12, v8, v102492; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma2493; CHECK-NEXT:    vfadd.vv v8, v12, v122494; CHECK-NEXT:    ret2495  %1 = call <vscale x 4 x double> @llvm.riscv.vfwmul.nxv4f64.nxv4f32.nxv4f32(<vscale x 4 x double> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen 7, iXLen -1)2496  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %1, iXLen 7, iXLen %vl)2497  ret <vscale x 4 x double> %22498}2499 2500define <vscale x 4 x double> @vfwmul_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2501; CHECK-LABEL: vfwmul_vf:2502; CHECK:       # %bb.0:2503; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2504; CHECK-NEXT:    vfwmul.vf v12, v8, fa02505; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma2506; CHECK-NEXT:    vfadd.vv v8, v12, v122507; CHECK-NEXT:    ret2508  %1 = call <vscale x 4 x double> @llvm.riscv.vfwmul.nxv4f64.nxv4f32.f32(<vscale x 4 x double> poison, <vscale x 4 x float> %a, float %b, iXLen 7, iXLen -1)2509  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %1, iXLen 7, iXLen %vl)2510  ret <vscale x 4 x double> %22511}2512 2513define <vscale x 4 x i1> @vmfeq_vf(<vscale x 4 x float> %a, <vscale x 4 x i1> %b, float%c, iXLen %vl) {2514; CHECK-LABEL: vmfeq_vf:2515; CHECK:       # %bb.0:2516; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2517; CHECK-NEXT:    vmfeq.vf v10, v8, fa02518; CHECK-NEXT:    vmand.mm v0, v10, v02519; CHECK-NEXT:    ret2520  %1 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(<vscale x 4 x float> %a, float %c, iXLen -1)2521  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)2522  ret <vscale x 4 x i1> %22523}2524 2525define <vscale x 4 x i1> @vmfeq_vv(<vscale x 4 x float> %a, <vscale x 4 x i1> %b, <vscale x 4 x float> %c, iXLen %vl) {2526; CHECK-LABEL: vmfeq_vv:2527; CHECK:       # %bb.0:2528; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2529; CHECK-NEXT:    vmfeq.vv v12, v8, v102530; CHECK-NEXT:    vmand.mm v0, v12, v02531; CHECK-NEXT:    ret2532  %1 = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %c, iXLen -1)2533  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)2534  ret <vscale x 4 x i1> %22535}2536 2537define <vscale x 4 x i1> @vmfne_vf(<vscale x 4 x float> %a, <vscale x 4 x i1> %b, float%c, iXLen %vl) {2538; CHECK-LABEL: vmfne_vf:2539; CHECK:       # %bb.0:2540; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2541; CHECK-NEXT:    vmfne.vf v10, v8, fa02542; CHECK-NEXT:    vmand.mm v0, v10, v02543; CHECK-NEXT:    ret2544  %1 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(<vscale x 4 x float> %a, float %c, iXLen -1)2545  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)2546  ret <vscale x 4 x i1> %22547}2548 2549define <vscale x 4 x i1> @vmfne_vv(<vscale x 4 x float> %a, <vscale x 4 x i1> %b, <vscale x 4 x float> %c, iXLen %vl) {2550; CHECK-LABEL: vmfne_vv:2551; CHECK:       # %bb.0:2552; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2553; CHECK-NEXT:    vmfne.vv v12, v8, v102554; CHECK-NEXT:    vmand.mm v0, v12, v02555; CHECK-NEXT:    ret2556  %1 = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %c, iXLen -1)2557  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)2558  ret <vscale x 4 x i1> %22559}2560 2561define <vscale x 4 x i1> @vmflt_vf(<vscale x 4 x float> %a, <vscale x 4 x i1> %b, float%c, iXLen %vl) {2562; CHECK-LABEL: vmflt_vf:2563; CHECK:       # %bb.0:2564; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2565; CHECK-NEXT:    vmflt.vf v10, v8, fa02566; CHECK-NEXT:    vmand.mm v0, v10, v02567; CHECK-NEXT:    ret2568  %1 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(<vscale x 4 x float> %a, float %c, iXLen -1)2569  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)2570  ret <vscale x 4 x i1> %22571}2572 2573define <vscale x 4 x i1> @vmflt_vv(<vscale x 4 x float> %a, <vscale x 4 x i1> %b, <vscale x 4 x float> %c, iXLen %vl) {2574; CHECK-LABEL: vmflt_vv:2575; CHECK:       # %bb.0:2576; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2577; CHECK-NEXT:    vmflt.vv v12, v8, v102578; CHECK-NEXT:    vmand.mm v0, v12, v02579; CHECK-NEXT:    ret2580  %1 = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %c, iXLen -1)2581  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)2582  ret <vscale x 4 x i1> %22583}2584 2585define <vscale x 4 x i1> @vmfle_vf(<vscale x 4 x float> %a, <vscale x 4 x i1> %b, float%c, iXLen %vl) {2586; CHECK-LABEL: vmfle_vf:2587; CHECK:       # %bb.0:2588; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2589; CHECK-NEXT:    vmfle.vf v10, v8, fa02590; CHECK-NEXT:    vmand.mm v0, v10, v02591; CHECK-NEXT:    ret2592  %1 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(<vscale x 4 x float> %a, float %c, iXLen -1)2593  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)2594  ret <vscale x 4 x i1> %22595}2596 2597define <vscale x 4 x i1> @vmfle_vv(<vscale x 4 x float> %a, <vscale x 4 x i1> %b, <vscale x 4 x float> %c, iXLen %vl) {2598; CHECK-LABEL: vmfle_vv:2599; CHECK:       # %bb.0:2600; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2601; CHECK-NEXT:    vmfle.vv v12, v8, v102602; CHECK-NEXT:    vmand.mm v0, v12, v02603; CHECK-NEXT:    ret2604  %1 = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %c, iXLen -1)2605  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)2606  ret <vscale x 4 x i1> %22607}2608 2609define <vscale x 4 x i1> @vmfgt_vf(<vscale x 4 x float> %a, <vscale x 4 x i1> %b, float%c, iXLen %vl) {2610; CHECK-LABEL: vmfgt_vf:2611; CHECK:       # %bb.0:2612; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2613; CHECK-NEXT:    vmfgt.vf v10, v8, fa02614; CHECK-NEXT:    vmand.mm v0, v10, v02615; CHECK-NEXT:    ret2616  %1 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(<vscale x 4 x float> %a, float %c, iXLen -1)2617  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)2618  ret <vscale x 4 x i1> %22619}2620 2621define <vscale x 4 x i1> @vmfgt_vv(<vscale x 4 x float> %a, <vscale x 4 x i1> %b, <vscale x 4 x float> %c, iXLen %vl) {2622; CHECK-LABEL: vmfgt_vv:2623; CHECK:       # %bb.0:2624; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2625; CHECK-NEXT:    vmflt.vv v12, v10, v82626; CHECK-NEXT:    vmand.mm v0, v12, v02627; CHECK-NEXT:    ret2628  %1 = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %c, iXLen -1)2629  %2 = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %b, iXLen %vl)2630  ret <vscale x 4 x i1> %22631}2632 2633define <vscale x 4 x i32> @vmerge_vvm(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %c, iXLen %vl) {2634; CHECK-LABEL: vmerge_vvm:2635; CHECK:       # %bb.0:2636; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2637; CHECK-NEXT:    vmerge.vvm v8, v8, v10, v02638; CHECK-NEXT:    vadd.vv v8, v8, v102639; CHECK-NEXT:    ret2640  %1 = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %c, iXLen -1)2641  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)2642  ret <vscale x 4 x i32> %22643}2644 2645define <vscale x 4 x i32> @vmerge_vxm(<vscale x 4 x i32> %a, i32 %b, <vscale x 4 x i1> %c, iXLen %vl) {2646; CHECK-LABEL: vmerge_vxm:2647; CHECK:       # %bb.0:2648; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2649; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v02650; CHECK-NEXT:    vadd.vv v8, v8, v82651; CHECK-NEXT:    ret2652  %1 = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, <vscale x 4 x i1> %c, iXLen -1)2653  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)2654  ret <vscale x 4 x i32> %22655}2656 2657define <vscale x 4 x i32> @vmerge_vim(<vscale x 4 x i32> %a, <vscale x 4 x i1> %c, iXLen %vl) {2658; CHECK-LABEL: vmerge_vim:2659; CHECK:       # %bb.0:2660; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2661; CHECK-NEXT:    vmerge.vim v8, v8, 9, v02662; CHECK-NEXT:    vadd.vv v8, v8, v82663; CHECK-NEXT:    ret2664  %1 = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 9, <vscale x 4 x i1> %c, iXLen -1)2665  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)2666  ret <vscale x 4 x i32> %22667}2668 2669define <vscale x 4 x i32> @vadc_vvm(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %c, iXLen %vl) {2670; CHECK-LABEL: vadc_vvm:2671; CHECK:       # %bb.0:2672; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2673; CHECK-NEXT:    vadc.vvm v8, v8, v10, v02674; CHECK-NEXT:    vadd.vv v8, v8, v102675; CHECK-NEXT:    ret2676  %1 = call <vscale x 4 x i32> @llvm.riscv.vadc.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %c, iXLen -1)2677  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)2678  ret <vscale x 4 x i32> %22679}2680 2681define <vscale x 4 x i32> @vadc_vxm(<vscale x 4 x i32> %a, i32 %b, <vscale x 4 x i1> %c, iXLen %vl) {2682; CHECK-LABEL: vadc_vxm:2683; CHECK:       # %bb.0:2684; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2685; CHECK-NEXT:    vadc.vxm v8, v8, a0, v02686; CHECK-NEXT:    vadd.vv v8, v8, v82687; CHECK-NEXT:    ret2688  %1 = call <vscale x 4 x i32> @llvm.riscv.vadc.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, <vscale x 4 x i1> %c, iXLen -1)2689  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)2690  ret <vscale x 4 x i32> %22691}2692 2693define <vscale x 4 x i32> @vadc_vim(<vscale x 4 x i32> %a, <vscale x 4 x i1> %c, iXLen %vl) {2694; CHECK-LABEL: vadc_vim:2695; CHECK:       # %bb.0:2696; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2697; CHECK-NEXT:    vadc.vim v8, v8, 9, v02698; CHECK-NEXT:    vadd.vv v8, v8, v82699; CHECK-NEXT:    ret2700  %1 = call <vscale x 4 x i32> @llvm.riscv.vadc.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 9, <vscale x 4 x i1> %c, iXLen -1)2701  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %1, iXLen %vl)2702  ret <vscale x 4 x i32> %22703}2704 2705define <vscale x 4 x i32> @vaadd_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {2706; CHECK-LABEL: vaadd_vv:2707; CHECK:       # %bb.0:2708; CHECK-NEXT:    csrwi vxrm, 02709; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2710; CHECK-NEXT:    vaadd.vv v8, v8, v102711; CHECK-NEXT:    vadd.vv v8, v8, v102712; CHECK-NEXT:    ret2713  %1 = call <vscale x 4 x i32> @llvm.riscv.vaadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 0, iXLen -1)2714  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)2715  ret <vscale x 4 x i32> %22716}2717 2718define <vscale x 4 x i32> @vaadd_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {2719; CHECK-LABEL: vaadd_vx:2720; CHECK:       # %bb.0:2721; CHECK-NEXT:    csrwi vxrm, 02722; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2723; CHECK-NEXT:    vaadd.vx v10, v8, a02724; CHECK-NEXT:    vadd.vv v8, v10, v82725; CHECK-NEXT:    ret2726  %1 = call <vscale x 4 x i32> @llvm.riscv.vaadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen 0, iXLen -1)2727  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)2728  ret <vscale x 4 x i32> %22729}2730 2731define <vscale x 4 x i32> @vasub_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {2732; CHECK-LABEL: vasub_vv:2733; CHECK:       # %bb.0:2734; CHECK-NEXT:    csrwi vxrm, 02735; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2736; CHECK-NEXT:    vasub.vv v8, v8, v102737; CHECK-NEXT:    vadd.vv v8, v8, v102738; CHECK-NEXT:    ret2739  %1 = call <vscale x 4 x i32> @llvm.riscv.vasub.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 0, iXLen -1)2740  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)2741  ret <vscale x 4 x i32> %22742}2743 2744define <vscale x 4 x i32> @vasub_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {2745; CHECK-LABEL: vasub_vx:2746; CHECK:       # %bb.0:2747; CHECK-NEXT:    csrwi vxrm, 02748; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2749; CHECK-NEXT:    vasub.vx v10, v8, a02750; CHECK-NEXT:    vadd.vv v8, v10, v82751; CHECK-NEXT:    ret2752  %1 = call <vscale x 4 x i32> @llvm.riscv.vasub.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen 0, iXLen -1)2753  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)2754  ret <vscale x 4 x i32> %22755}2756 2757define <vscale x 4 x i32> @vaaddu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {2758; CHECK-LABEL: vaaddu_vv:2759; CHECK:       # %bb.0:2760; CHECK-NEXT:    csrwi vxrm, 02761; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2762; CHECK-NEXT:    vaaddu.vv v8, v8, v102763; CHECK-NEXT:    vadd.vv v8, v8, v102764; CHECK-NEXT:    ret2765  %1 = call <vscale x 4 x i32> @llvm.riscv.vaaddu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 0, iXLen -1)2766  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)2767  ret <vscale x 4 x i32> %22768}2769 2770define <vscale x 4 x i32> @vaaddu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {2771; CHECK-LABEL: vaaddu_vx:2772; CHECK:       # %bb.0:2773; CHECK-NEXT:    csrwi vxrm, 02774; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2775; CHECK-NEXT:    vaaddu.vx v10, v8, a02776; CHECK-NEXT:    vadd.vv v8, v10, v82777; CHECK-NEXT:    ret2778  %1 = call <vscale x 4 x i32> @llvm.riscv.vaaddu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen 0, iXLen -1)2779  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)2780  ret <vscale x 4 x i32> %22781}2782 2783define <vscale x 4 x i32> @vasubu_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {2784; CHECK-LABEL: vasubu_vv:2785; CHECK:       # %bb.0:2786; CHECK-NEXT:    csrwi vxrm, 02787; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2788; CHECK-NEXT:    vasubu.vv v8, v8, v102789; CHECK-NEXT:    vadd.vv v8, v8, v102790; CHECK-NEXT:    ret2791  %1 = call <vscale x 4 x i32> @llvm.riscv.vasubu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 0, iXLen -1)2792  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)2793  ret <vscale x 4 x i32> %22794}2795 2796define <vscale x 4 x i32> @vasubu_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {2797; CHECK-LABEL: vasubu_vx:2798; CHECK:       # %bb.0:2799; CHECK-NEXT:    csrwi vxrm, 02800; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2801; CHECK-NEXT:    vasubu.vx v10, v8, a02802; CHECK-NEXT:    vadd.vv v8, v10, v82803; CHECK-NEXT:    ret2804  %1 = call <vscale x 4 x i32> @llvm.riscv.vasubu.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen 0, iXLen -1)2805  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)2806  ret <vscale x 4 x i32> %22807}2808 2809define <vscale x 4 x float> @vfmax_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2810; CHECK-LABEL: vfmax_vv:2811; CHECK:       # %bb.0:2812; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2813; CHECK-NEXT:    vfmax.vv v8, v8, v102814; CHECK-NEXT:    vfadd.vv v8, v8, v102815; CHECK-NEXT:    ret2816  %1 = call <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen -1)2817  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %b, iXLen 7, iXLen %vl)2818  ret <vscale x 4 x float> %22819}2820 2821define <vscale x 4 x float> @vfmax_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2822; CHECK-LABEL: vfmax_vf:2823; CHECK:       # %bb.0:2824; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2825; CHECK-NEXT:    vfmax.vf v10, v8, fa02826; CHECK-NEXT:    vfadd.vv v8, v10, v82827; CHECK-NEXT:    ret2828  %1 = call <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen -1)2829  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2830  ret <vscale x 4 x float> %22831}2832 2833define <vscale x 4 x float> @vfmin_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2834; CHECK-LABEL: vfmin_vv:2835; CHECK:       # %bb.0:2836; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2837; CHECK-NEXT:    vfmin.vv v8, v8, v102838; CHECK-NEXT:    vfadd.vv v8, v8, v102839; CHECK-NEXT:    ret2840  %1 = call <vscale x 4 x float> @llvm.riscv.vfmin.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen -1)2841  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %b, iXLen 7, iXLen %vl)2842  ret <vscale x 4 x float> %22843}2844 2845define <vscale x 4 x float> @vfmin_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2846; CHECK-LABEL: vfmin_vf:2847; CHECK:       # %bb.0:2848; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2849; CHECK-NEXT:    vfmin.vf v10, v8, fa02850; CHECK-NEXT:    vfadd.vv v8, v10, v82851; CHECK-NEXT:    ret2852  %1 = call <vscale x 4 x float> @llvm.riscv.vfmin.nxv4f32.f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen -1)2853  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2854  ret <vscale x 4 x float> %22855}2856 2857define <vscale x 4 x float> @vfsgnj_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2858; CHECK-LABEL: vfsgnj_vv:2859; CHECK:       # %bb.0:2860; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2861; CHECK-NEXT:    vfsgnj.vv v8, v8, v102862; CHECK-NEXT:    vfadd.vv v8, v8, v102863; CHECK-NEXT:    ret2864  %1 = call <vscale x 4 x float> @llvm.riscv.vfsgnj.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen -1)2865  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %b, iXLen 7, iXLen %vl)2866  ret <vscale x 4 x float> %22867}2868 2869define <vscale x 4 x float> @vfsgnj_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2870; CHECK-LABEL: vfsgnj_vf:2871; CHECK:       # %bb.0:2872; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2873; CHECK-NEXT:    vfsgnj.vf v10, v8, fa02874; CHECK-NEXT:    vfadd.vv v8, v10, v82875; CHECK-NEXT:    ret2876  %1 = call <vscale x 4 x float> @llvm.riscv.vfsgnj.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen -1)2877  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2878  ret <vscale x 4 x float> %22879}2880 2881define <vscale x 4 x float> @vfsgnjn_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2882; CHECK-LABEL: vfsgnjn_vv:2883; CHECK:       # %bb.0:2884; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2885; CHECK-NEXT:    vfsgnjn.vv v8, v8, v102886; CHECK-NEXT:    vfadd.vv v8, v8, v102887; CHECK-NEXT:    ret2888  %1 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen -1)2889  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %b, iXLen 7, iXLen %vl)2890  ret <vscale x 4 x float> %22891}2892 2893define <vscale x 4 x float> @vfsgnjn_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2894; CHECK-LABEL: vfsgnjn_vf:2895; CHECK:       # %bb.0:2896; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2897; CHECK-NEXT:    vfsgnjn.vf v10, v8, fa02898; CHECK-NEXT:    vfadd.vv v8, v10, v82899; CHECK-NEXT:    ret2900  %1 = call <vscale x 4 x float> @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen -1)2901  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2902  ret <vscale x 4 x float> %22903}2904 2905define <vscale x 4 x float> @vfsgnjx_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) {2906; CHECK-LABEL: vfsgnjx_vv:2907; CHECK:       # %bb.0:2908; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2909; CHECK-NEXT:    vfsgnjx.vv v8, v8, v102910; CHECK-NEXT:    vfadd.vv v8, v8, v102911; CHECK-NEXT:    ret2912  %1 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen -1)2913  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %b, iXLen 7, iXLen %vl)2914  ret <vscale x 4 x float> %22915}2916 2917define <vscale x 4 x float> @vfsgnjx_vf(<vscale x 4 x float> %a, float %b, iXLen %vl) {2918; CHECK-LABEL: vfsgnjx_vf:2919; CHECK:       # %bb.0:2920; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2921; CHECK-NEXT:    vfsgnjx.vf v10, v8, fa02922; CHECK-NEXT:    vfadd.vv v8, v10, v82923; CHECK-NEXT:    ret2924  %1 = call <vscale x 4 x float> @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, iXLen -1)2925  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2926  ret <vscale x 4 x float> %22927}2928 2929define <vscale x 4 x float> @vfmerge_vf(<vscale x 4 x float> %a, float %b, <vscale x 4 x i1> %c, iXLen %vl) {2930; CHECK-LABEL: vfmerge_vf:2931; CHECK:       # %bb.0:2932; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2933; CHECK-NEXT:    vfmerge.vfm v10, v8, fa0, v02934; CHECK-NEXT:    vfadd.vv v8, v10, v82935; CHECK-NEXT:    ret2936  %1 = call <vscale x 4 x float> @llvm.riscv.vfmerge(<vscale x 4 x float> poison, <vscale x 4 x float> %a, float %b, <vscale x 4 x i1> %c, iXLen -1)2937  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2938  ret <vscale x 4 x float> %22939}2940 2941define <vscale x 4 x float> @vfmv_v_f(<vscale x 4 x float> %a, float %b, iXLen %vl) {2942; CHECK-LABEL: vfmv_v_f:2943; CHECK:       # %bb.0:2944; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2945; CHECK-NEXT:    vfmv.v.f v10, fa02946; CHECK-NEXT:    vfadd.vv v8, v10, v82947; CHECK-NEXT:    ret2948  %1 = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f(<vscale x 4 x float> poison, float %b, iXLen -1)2949  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %a, iXLen 7, iXLen %vl)2950  ret <vscale x 4 x float> %22951}2952 2953define <vscale x 4 x float> @vfmacc_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen %vl) {2954; CHECK-LABEL: vfmacc_vv:2955; CHECK:       # %bb.0:2956; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2957; CHECK-NEXT:    vfmacc.vv v8, v12, v102958; CHECK-NEXT:    vfadd.vv v8, v8, v122959; CHECK-NEXT:    ret2960  %1 = call <vscale x 4 x float> @llvm.riscv.vfmacc(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)2961  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)2962  ret <vscale x 4 x float> %22963}2964 2965define <vscale x 4 x float> @vfmacc_vf(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen %vl) {2966; CHECK-LABEL: vfmacc_vf:2967; CHECK:       # %bb.0:2968; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2969; CHECK-NEXT:    vfmacc.vf v8, fa0, v102970; CHECK-NEXT:    vfadd.vv v8, v8, v102971; CHECK-NEXT:    ret2972  %1 = call <vscale x 4 x float> @llvm.riscv.vfmacc(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)2973  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)2974  ret <vscale x 4 x float> %22975}2976 2977define <vscale x 4 x float> @vfnmacc_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen %vl) {2978; CHECK-LABEL: vfnmacc_vv:2979; CHECK:       # %bb.0:2980; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2981; CHECK-NEXT:    vfnmacc.vv v8, v12, v102982; CHECK-NEXT:    vfadd.vv v8, v8, v122983; CHECK-NEXT:    ret2984  %1 = call <vscale x 4 x float> @llvm.riscv.vfnmacc(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)2985  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)2986  ret <vscale x 4 x float> %22987}2988 2989define <vscale x 4 x float> @vfnmacc_vf(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen %vl) {2990; CHECK-LABEL: vfnmacc_vf:2991; CHECK:       # %bb.0:2992; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2993; CHECK-NEXT:    vfnmacc.vf v8, fa0, v102994; CHECK-NEXT:    vfadd.vv v8, v8, v102995; CHECK-NEXT:    ret2996  %1 = call <vscale x 4 x float> @llvm.riscv.vfnmacc(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)2997  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)2998  ret <vscale x 4 x float> %22999}3000 3001define <vscale x 4 x float> @vfmsac_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen %vl) {3002; CHECK-LABEL: vfmsac_vv:3003; CHECK:       # %bb.0:3004; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3005; CHECK-NEXT:    vfmsac.vv v8, v12, v103006; CHECK-NEXT:    vfadd.vv v8, v8, v123007; CHECK-NEXT:    ret3008  %1 = call <vscale x 4 x float> @llvm.riscv.vfmsac(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3009  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3010  ret <vscale x 4 x float> %23011}3012 3013define <vscale x 4 x float> @vfmsac_vf(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen %vl) {3014; CHECK-LABEL: vfmsac_vf:3015; CHECK:       # %bb.0:3016; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3017; CHECK-NEXT:    vfmsac.vf v8, fa0, v103018; CHECK-NEXT:    vfadd.vv v8, v8, v103019; CHECK-NEXT:    ret3020  %1 = call <vscale x 4 x float> @llvm.riscv.vfmsac(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3021  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3022  ret <vscale x 4 x float> %23023}3024 3025define <vscale x 4 x float> @vfnmsac_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen %vl) {3026; CHECK-LABEL: vfnmsac_vv:3027; CHECK:       # %bb.0:3028; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3029; CHECK-NEXT:    vfnmsac.vv v8, v12, v103030; CHECK-NEXT:    vfadd.vv v8, v8, v123031; CHECK-NEXT:    ret3032  %1 = call <vscale x 4 x float> @llvm.riscv.vfnmsac(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3033  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3034  ret <vscale x 4 x float> %23035}3036 3037define <vscale x 4 x float> @vfnmsac_vf(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen %vl) {3038; CHECK-LABEL: vfnmsac_vf:3039; CHECK:       # %bb.0:3040; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3041; CHECK-NEXT:    vfnmsac.vf v8, fa0, v103042; CHECK-NEXT:    vfadd.vv v8, v8, v103043; CHECK-NEXT:    ret3044  %1 = call <vscale x 4 x float> @llvm.riscv.vfnmsac(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3045  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3046  ret <vscale x 4 x float> %23047}3048 3049define <vscale x 4 x float> @vfmadd_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen %vl) {3050; CHECK-LABEL: vfmadd_vv:3051; CHECK:       # %bb.0:3052; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3053; CHECK-NEXT:    vfmadd.vv v8, v10, v123054; CHECK-NEXT:    vfadd.vv v8, v8, v123055; CHECK-NEXT:    ret3056  %1 = call <vscale x 4 x float> @llvm.riscv.vfmadd(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3057  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3058  ret <vscale x 4 x float> %23059}3060 3061define <vscale x 4 x float> @vfmadd_vf(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen %vl) {3062; CHECK-LABEL: vfmadd_vf:3063; CHECK:       # %bb.0:3064; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3065; CHECK-NEXT:    vfmadd.vf v8, fa0, v103066; CHECK-NEXT:    vfadd.vv v8, v8, v103067; CHECK-NEXT:    ret3068  %1 = call <vscale x 4 x float> @llvm.riscv.vfmadd(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3069  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3070  ret <vscale x 4 x float> %23071}3072 3073define <vscale x 4 x float> @vfnmadd_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen %vl) {3074; CHECK-LABEL: vfnmadd_vv:3075; CHECK:       # %bb.0:3076; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3077; CHECK-NEXT:    vfnmadd.vv v8, v10, v123078; CHECK-NEXT:    vfadd.vv v8, v8, v123079; CHECK-NEXT:    ret3080  %1 = call <vscale x 4 x float> @llvm.riscv.vfnmadd(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3081  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3082  ret <vscale x 4 x float> %23083}3084 3085define <vscale x 4 x float> @vfnmadd_vf(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen %vl) {3086; CHECK-LABEL: vfnmadd_vf:3087; CHECK:       # %bb.0:3088; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3089; CHECK-NEXT:    vfnmadd.vf v8, fa0, v103090; CHECK-NEXT:    vfadd.vv v8, v8, v103091; CHECK-NEXT:    ret3092  %1 = call <vscale x 4 x float> @llvm.riscv.vfnmadd(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3093  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3094  ret <vscale x 4 x float> %23095}3096 3097define <vscale x 4 x float> @vfmsub_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen %vl) {3098; CHECK-LABEL: vfmsub_vv:3099; CHECK:       # %bb.0:3100; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3101; CHECK-NEXT:    vfmsub.vv v8, v10, v123102; CHECK-NEXT:    vfadd.vv v8, v8, v123103; CHECK-NEXT:    ret3104  %1 = call <vscale x 4 x float> @llvm.riscv.vfmsub(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3105  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3106  ret <vscale x 4 x float> %23107}3108 3109define <vscale x 4 x float> @vfmsub_vf(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen %vl) {3110; CHECK-LABEL: vfmsub_vf:3111; CHECK:       # %bb.0:3112; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3113; CHECK-NEXT:    vfmsub.vf v8, fa0, v103114; CHECK-NEXT:    vfadd.vv v8, v8, v103115; CHECK-NEXT:    ret3116  %1 = call <vscale x 4 x float> @llvm.riscv.vfmsub(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3117  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3118  ret <vscale x 4 x float> %23119}3120 3121define <vscale x 4 x float> @vfnmsub_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen %vl) {3122; CHECK-LABEL: vfnmsub_vv:3123; CHECK:       # %bb.0:3124; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3125; CHECK-NEXT:    vfnmsub.vv v8, v10, v123126; CHECK-NEXT:    vfadd.vv v8, v8, v123127; CHECK-NEXT:    ret3128  %1 = call <vscale x 4 x float> @llvm.riscv.vfnmsub(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3129  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3130  ret <vscale x 4 x float> %23131}3132 3133define <vscale x 4 x float> @vfnmsub_vf(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen %vl) {3134; CHECK-LABEL: vfnmsub_vf:3135; CHECK:       # %bb.0:3136; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3137; CHECK-NEXT:    vfnmsub.vf v8, fa0, v103138; CHECK-NEXT:    vfadd.vv v8, v8, v103139; CHECK-NEXT:    ret3140  %1 = call <vscale x 4 x float> @llvm.riscv.vfnmsub(<vscale x 4 x float> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 3)3141  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %c, iXLen 7, iXLen %vl)3142  ret <vscale x 4 x float> %23143}3144 3145define <vscale x 4 x double> @vfwmacc_vv(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, <vscale x 4 x double> %d, iXLen %vl) {3146; CHECK-LABEL: vfwmacc_vv:3147; CHECK:       # %bb.0:3148; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma3149; CHECK-NEXT:    vfwmacc.vv v8, v12, v143150; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3151; CHECK-NEXT:    vfadd.vv v8, v8, v163152; CHECK-NEXT:    ret3153  %1 = call <vscale x 4 x double> @llvm.riscv.vfwmacc(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)3154  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %d, iXLen 7, iXLen %vl)3155  ret <vscale x 4 x double> %23156}3157 3158define <vscale x 4 x double> @vfwmacc_vf(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, <vscale x 4 x double> %d, iXLen %vl) {3159; CHECK-LABEL: vfwmacc_vf:3160; CHECK:       # %bb.0:3161; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma3162; CHECK-NEXT:    vfwmacc.vf v8, fa0, v123163; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3164; CHECK-NEXT:    vfadd.vv v8, v8, v163165; CHECK-NEXT:    ret3166  %1 = call <vscale x 4 x double> @llvm.riscv.vfwmacc(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)3167  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %d, iXLen 7, iXLen %vl)3168  ret <vscale x 4 x double> %23169}3170 3171define <vscale x 4 x double> @vfwnmacc_vv(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, <vscale x 4 x double> %d, iXLen %vl) {3172; CHECK-LABEL: vfwnmacc_vv:3173; CHECK:       # %bb.0:3174; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma3175; CHECK-NEXT:    vfwnmacc.vv v8, v12, v143176; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3177; CHECK-NEXT:    vfadd.vv v8, v8, v163178; CHECK-NEXT:    ret3179  %1 = call <vscale x 4 x double> @llvm.riscv.vfwnmacc(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)3180  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %d, iXLen 7, iXLen %vl)3181  ret <vscale x 4 x double> %23182}3183 3184define <vscale x 4 x double> @vfwnmacc_vf(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, <vscale x 4 x double> %d, iXLen %vl) {3185; CHECK-LABEL: vfwnmacc_vf:3186; CHECK:       # %bb.0:3187; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma3188; CHECK-NEXT:    vfwnmacc.vf v8, fa0, v123189; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3190; CHECK-NEXT:    vfadd.vv v8, v8, v163191; CHECK-NEXT:    ret3192  %1 = call <vscale x 4 x double> @llvm.riscv.vfwnmacc(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)3193  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %d, iXLen 7, iXLen %vl)3194  ret <vscale x 4 x double> %23195}3196 3197define <vscale x 4 x double> @vfwmsac_vv(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, <vscale x 4 x double> %d, iXLen %vl) {3198; CHECK-LABEL: vfwmsac_vv:3199; CHECK:       # %bb.0:3200; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma3201; CHECK-NEXT:    vfwmsac.vv v8, v12, v143202; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3203; CHECK-NEXT:    vfadd.vv v8, v8, v163204; CHECK-NEXT:    ret3205  %1 = call <vscale x 4 x double> @llvm.riscv.vfwmsac(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)3206  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %d, iXLen 7, iXLen %vl)3207  ret <vscale x 4 x double> %23208}3209 3210define <vscale x 4 x double> @vfwmsac_vf(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, <vscale x 4 x double> %d, iXLen %vl) {3211; CHECK-LABEL: vfwmsac_vf:3212; CHECK:       # %bb.0:3213; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma3214; CHECK-NEXT:    vfwmsac.vf v8, fa0, v123215; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3216; CHECK-NEXT:    vfadd.vv v8, v8, v163217; CHECK-NEXT:    ret3218  %1 = call <vscale x 4 x double> @llvm.riscv.vfwmsac(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)3219  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %d, iXLen 7, iXLen %vl)3220  ret <vscale x 4 x double> %23221}3222 3223define <vscale x 4 x double> @vfwnmsac_vv(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, <vscale x 4 x double> %d, iXLen %vl) {3224; CHECK-LABEL: vfwnmsac_vv:3225; CHECK:       # %bb.0:3226; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma3227; CHECK-NEXT:    vfwnmsac.vv v8, v12, v143228; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3229; CHECK-NEXT:    vfadd.vv v8, v8, v163230; CHECK-NEXT:    ret3231  %1 = call <vscale x 4 x double> @llvm.riscv.vfwnmsac(<vscale x 4 x double> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)3232  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %d, iXLen 7, iXLen %vl)3233  ret <vscale x 4 x double> %23234}3235 3236define <vscale x 4 x double> @vfwnmsac_vf(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, <vscale x 4 x double> %d, iXLen %vl) {3237; CHECK-LABEL: vfwnmsac_vf:3238; CHECK:       # %bb.0:3239; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma3240; CHECK-NEXT:    vfwnmsac.vf v8, fa0, v123241; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma3242; CHECK-NEXT:    vfadd.vv v8, v8, v163243; CHECK-NEXT:    ret3244  %1 = call <vscale x 4 x double> @llvm.riscv.vfwnmsac(<vscale x 4 x double> %a, float %b, <vscale x 4 x float> %c, iXLen 7, iXLen -1, iXLen 0)3245  %2 = call <vscale x 4 x double> @llvm.riscv.vfadd(<vscale x 4 x double> poison, <vscale x 4 x double> %1, <vscale x 4 x double> %d, iXLen 7, iXLen %vl)3246  ret <vscale x 4 x double> %23247}3248 3249define <vscale x 4 x float> @vfwmaccbf16_vv(<vscale x 4 x float> %a, <vscale x 4 x bfloat> %b, <vscale x 4 x bfloat> %c, <vscale x 4 x float> %d, iXLen %vl) {3250; CHECK-LABEL: vfwmaccbf16_vv:3251; CHECK:       # %bb.0:3252; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma3253; CHECK-NEXT:    vfwmaccbf16.vv v8, v10, v113254; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma3255; CHECK-NEXT:    vfadd.vv v8, v8, v123256; CHECK-NEXT:    ret3257  %1 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16(<vscale x 4 x float> %a, <vscale x 4 x bfloat> %b, <vscale x 4 x bfloat> %c, iXLen 7, iXLen -1, iXLen 0)3258  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %d, iXLen 7, iXLen %vl)3259  ret <vscale x 4 x float> %23260}3261 3262define <vscale x 4 x i32> @vsbc_vvm(<vscale x 4 x i32> %a, <vscale x 4 x i1> %mask, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, iXLen %vl) {3263; CHECK-LABEL: vsbc_vvm:3264; CHECK:       # %bb.0:3265; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3266; CHECK-NEXT:    vsbc.vvm v8, v8, v10, v03267; CHECK-NEXT:    vadd.vv v8, v8, v123268; CHECK-NEXT:    ret3269  %1 = call <vscale x 4 x i32> @llvm.riscv.vsbc.nxv4i32.nxv4i32.nxv4i1(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %mask, iXLen -1)3270  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %c, iXLen %vl)3271  ret <vscale x 4 x i32> %23272}3273 3274define <vscale x 4 x i32> @vsbc_vxm(<vscale x 4 x i32> %a, <vscale x 4 x i1> %mask, <vscale x 4 x i32> %b, i32 %c, iXLen %vl) {3275; CHECK-LABEL: vsbc_vxm:3276; CHECK:       # %bb.0:3277; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma3278; CHECK-NEXT:    vsbc.vxm v8, v8, a0, v03279; CHECK-NEXT:    vadd.vv v8, v8, v103280; CHECK-NEXT:    ret3281  %1 = call <vscale x 4 x i32> @llvm.riscv.vsbc.nxv4i32.i32.nxv4i1(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %c, <vscale x 4 x i1> %mask, iXLen -1)3282  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)3283  ret <vscale x 4 x i32> %23284}3285 3286define <vscale x 4 x i32> @vfclass_v(<vscale x 4 x float> %a, <vscale x 4 x i32> %b, iXLen %vl) {3287; CHECK-LABEL: vfclass_v:3288; CHECK:       # %bb.0:3289; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3290; CHECK-NEXT:    vfclass.v v8, v83291; CHECK-NEXT:    vadd.vv v8, v8, v103292; CHECK-NEXT:    ret3293  %1 = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x float> %a, iXLen -1)3294  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)3295  ret <vscale x 4 x i32> %23296}3297 3298define <vscale x 4 x i32> @vrgather_vi(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {3299; CHECK-LABEL: vrgather_vi:3300; CHECK:       # %bb.0:3301; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3302; CHECK-NEXT:    vrgather.vi v12, v8, 53303; CHECK-NEXT:    vadd.vv v8, v12, v103304; CHECK-NEXT:    ret3305  %1 = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)3306  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)3307  ret <vscale x 4 x i32> %23308}3309 3310define <vscale x 4 x i32> @vrgather_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %idx, <vscale x 4 x i32> %b, iXLen %vl) {3311; CHECK-LABEL: vrgather_vv:3312; CHECK:       # %bb.0:3313; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3314; CHECK-NEXT:    vrgather.vv v12, v8, v103315; CHECK-NEXT:    vadd.vv v8, v12, v83316; CHECK-NEXT:    ret3317  %1 = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %idx, iXLen -1)3318  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3319  ret <vscale x 4 x i32> %23320}3321 3322define <vscale x 4 x i32> @vrgather_vx(<vscale x 4 x i32> %a, iXLen %idx, <vscale x 4 x i32> %b, iXLen %vl) {3323; CHECK-LABEL: vrgather_vx:3324; CHECK:       # %bb.0:3325; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma3326; CHECK-NEXT:    vrgather.vx v12, v8, a03327; CHECK-NEXT:    vadd.vv v8, v12, v103328; CHECK-NEXT:    ret3329  %1 = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %idx, iXLen -1)3330  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %b, iXLen %vl)3331  ret <vscale x 4 x i32> %23332}3333 3334define <vscale x 4 x i32> @vrgatherei16_vv(<vscale x 4 x i32> %a, <vscale x 4 x i16> %idx, <vscale x 4 x i32> %b, iXLen %vl) {3335; CHECK-LABEL: vrgatherei16_vv:3336; CHECK:       # %bb.0:3337; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3338; CHECK-NEXT:    vrgatherei16.vv v12, v8, v103339; CHECK-NEXT:    vadd.vv v8, v12, v83340; CHECK-NEXT:    ret3341  %1 = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i16> %idx, iXLen -1)3342  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3343  ret <vscale x 4 x i32> %23344}3345 3346define <vscale x 4 x float> @vfwmaccbf16_vf(<vscale x 4 x float> %a, bfloat %b, <vscale x 4 x bfloat> %c, <vscale x 4 x float> %d, iXLen %vl) {3347; CHECK-LABEL: vfwmaccbf16_vf:3348; CHECK:       # %bb.0:3349; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma3350; CHECK-NEXT:    vfwmaccbf16.vf v8, fa0, v103351; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma3352; CHECK-NEXT:    vfadd.vv v8, v8, v123353; CHECK-NEXT:    ret3354  %1 = call <vscale x 4 x float> @llvm.riscv.vfwmaccbf16(<vscale x 4 x float> %a, bfloat %b, <vscale x 4 x bfloat> %c, iXLen 7, iXLen -1, iXLen 0)3355  %2 = call <vscale x 4 x float> @llvm.riscv.vfadd(<vscale x 4 x float> poison, <vscale x 4 x float> %1, <vscale x 4 x float> %d, iXLen 7, iXLen %vl)3356  ret <vscale x 4 x float> %23357}3358 3359define <vscale x 4 x double> @vfsqrt(<vscale x 4 x float> %a) {3360; CHECK-LABEL: vfsqrt:3361; CHECK:       # %bb.0:3362; CHECK-NEXT:    vsetivli zero, 6, e32, m2, ta, ma3363; CHECK-NEXT:    vmv2r.v v12, v83364; CHECK-NEXT:    fsrmi a0, 03365; CHECK-NEXT:    vfsqrt.v v14, v83366; CHECK-NEXT:    fsrm a03367; CHECK-NEXT:    vfwmacc.vv v8, v12, v143368; CHECK-NEXT:    ret3369  %1 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, iXLen 0, iXLen 7)3370  %2 = call <vscale x 4 x double> @llvm.riscv.vfwmacc(<vscale x 4 x double> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %1, iXLen 7, iXLen 6, iXLen 0)3371  ret <vscale x 4 x double> %23372}3373 3374define <vscale x 4 x double> @vfrsqrt7(<vscale x 4 x float> %a) {3375; CHECK-LABEL: vfrsqrt7:3376; CHECK:       # %bb.0:3377; CHECK-NEXT:    vsetivli zero, 6, e32, m2, ta, ma3378; CHECK-NEXT:    vmv2r.v v12, v83379; CHECK-NEXT:    vfrsqrt7.v v14, v83380; CHECK-NEXT:    vfwmacc.vv v8, v12, v143381; CHECK-NEXT:    ret3382  %1 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, iXLen 7)3383  %2 = call <vscale x 4 x double> @llvm.riscv.vfwmacc(<vscale x 4 x double> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %1, iXLen 7, iXLen 6, iXLen 0)3384  ret <vscale x 4 x double> %23385}3386 3387define <vscale x 4 x double> @vfrec7(<vscale x 4 x float> %a) {3388; CHECK-LABEL: vfrec7:3389; CHECK:       # %bb.0:3390; CHECK-NEXT:    vsetivli zero, 6, e32, m2, ta, ma3391; CHECK-NEXT:    vmv2r.v v12, v83392; CHECK-NEXT:    fsrmi a0, 03393; CHECK-NEXT:    vfrec7.v v14, v83394; CHECK-NEXT:    fsrm a03395; CHECK-NEXT:    vfwmacc.vv v8, v12, v143396; CHECK-NEXT:    ret3397  %1 = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, iXLen 0, iXLen 7)3398  %2 = call <vscale x 4 x double> @llvm.riscv.vfwmacc(<vscale x 4 x double> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %1, iXLen 7, iXLen 6, iXLen 0)3399  ret <vscale x 4 x double> %23400}3401 3402define <vscale x 4 x i32> @vandn_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {3403; CHECK-LABEL: vandn_vv:3404; CHECK:       # %bb.0:3405; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3406; CHECK-NEXT:    vandn.vv v10, v8, v103407; CHECK-NEXT:    vadd.vv v8, v10, v83408; CHECK-NEXT:    ret3409  %1 = call <vscale x 4 x i32> @llvm.riscv.vandn.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)3410  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3411  ret <vscale x 4 x i32> %23412}3413 3414define <vscale x 4 x i32> @vandn_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {3415; CHECK-LABEL: vandn_vx:3416; CHECK:       # %bb.0:3417; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma3418; CHECK-NEXT:    vandn.vx v10, v8, a03419; CHECK-NEXT:    vadd.vv v8, v10, v83420; CHECK-NEXT:    ret3421  %1 = call <vscale x 4 x i32> @llvm.riscv.vandn.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)3422  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3423  ret <vscale x 4 x i32> %23424}3425 3426define <vscale x 4 x i32> @vbrev_v(<vscale x 4 x i32> %a, iXLen %vl) {3427; CHECK-LABEL: vbrev_v:3428; CHECK:       # %bb.0:3429; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3430; CHECK-NEXT:    vbrev.v v10, v83431; CHECK-NEXT:    vadd.vv v8, v10, v83432; CHECK-NEXT:    ret3433  %1 = call <vscale x 4 x i32> @llvm.riscv.vbrev.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)3434  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3435  ret <vscale x 4 x i32> %23436}3437 3438define <vscale x 4 x i32> @vbrev8_v(<vscale x 4 x i32> %a, iXLen %vl) {3439; CHECK-LABEL: vbrev8_v:3440; CHECK:       # %bb.0:3441; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3442; CHECK-NEXT:    vbrev8.v v10, v83443; CHECK-NEXT:    vadd.vv v8, v10, v83444; CHECK-NEXT:    ret3445  %1 = call <vscale x 4 x i32> @llvm.riscv.vbrev8.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)3446  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3447  ret <vscale x 4 x i32> %23448}3449 3450define <vscale x 4 x i32> @vrev8_v(<vscale x 4 x i32> %a, iXLen %vl) {3451; CHECK-LABEL: vrev8_v:3452; CHECK:       # %bb.0:3453; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3454; CHECK-NEXT:    vrev8.v v10, v83455; CHECK-NEXT:    vadd.vv v8, v10, v83456; CHECK-NEXT:    ret3457  %1 = call <vscale x 4 x i32> @llvm.riscv.vrev8.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)3458  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3459  ret <vscale x 4 x i32> %23460}3461 3462define <vscale x 4 x i32> @vclz_v(<vscale x 4 x i32> %a, iXLen %vl) {3463; CHECK-LABEL: vclz_v:3464; CHECK:       # %bb.0:3465; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3466; CHECK-NEXT:    vclz.v v10, v83467; CHECK-NEXT:    vadd.vv v8, v10, v83468; CHECK-NEXT:    ret3469  %1 = call <vscale x 4 x i32> @llvm.riscv.vclz.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)3470  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3471  ret <vscale x 4 x i32> %23472}3473 3474define <vscale x 4 x i32> @vcpop_v(<vscale x 4 x i32> %a, iXLen %vl) {3475; CHECK-LABEL: vcpop_v:3476; CHECK:       # %bb.0:3477; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3478; CHECK-NEXT:    vcpop.v v10, v83479; CHECK-NEXT:    vadd.vv v8, v10, v83480; CHECK-NEXT:    ret3481  %1 = call <vscale x 4 x i32> @llvm.riscv.vcpopv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)3482  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3483  ret <vscale x 4 x i32> %23484}3485 3486define <vscale x 4 x i32> @vctz_v(<vscale x 4 x i32> %a, iXLen %vl) {3487; CHECK-LABEL: vctz_v:3488; CHECK:       # %bb.0:3489; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3490; CHECK-NEXT:    vctz.v v10, v83491; CHECK-NEXT:    vadd.vv v8, v10, v83492; CHECK-NEXT:    ret3493  %1 = call <vscale x 4 x i32> @llvm.riscv.vctz.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)3494  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3495  ret <vscale x 4 x i32> %23496}3497 3498define <vscale x 4 x i32> @vror_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {3499; CHECK-LABEL: vror_vv:3500; CHECK:       # %bb.0:3501; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3502; CHECK-NEXT:    vror.vv v10, v8, v103503; CHECK-NEXT:    vadd.vv v8, v10, v83504; CHECK-NEXT:    ret3505  %1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)3506  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3507  ret <vscale x 4 x i32> %23508}3509 3510define <vscale x 4 x i32> @vror_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {3511; CHECK-LABEL: vror_vx:3512; CHECK:       # %bb.0:3513; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma3514; CHECK-NEXT:    vror.vx v10, v8, a03515; CHECK-NEXT:    vadd.vv v8, v10, v83516; CHECK-NEXT:    ret3517  %1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)3518  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3519  ret <vscale x 4 x i32> %23520}3521 3522define <vscale x 4 x i32> @vror_vi(<vscale x 4 x i32> %a, iXLen %vl) {3523; CHECK-LABEL: vror_vi:3524; CHECK:       # %bb.0:3525; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3526; CHECK-NEXT:    vror.vi v10, v8, 53527; CHECK-NEXT:    vadd.vv v8, v10, v83528; CHECK-NEXT:    ret3529  %1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)3530  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3531  ret <vscale x 4 x i32> %23532}3533 3534define <vscale x 4 x i32> @vrol_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {3535; CHECK-LABEL: vrol_vv:3536; CHECK:       # %bb.0:3537; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3538; CHECK-NEXT:    vrol.vv v10, v8, v103539; CHECK-NEXT:    vadd.vv v8, v10, v83540; CHECK-NEXT:    ret3541  %1 = call <vscale x 4 x i32> @llvm.riscv.vrol.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)3542  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3543  ret <vscale x 4 x i32> %23544}3545 3546define <vscale x 4 x i32> @vrol_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {3547; CHECK-LABEL: vrol_vx:3548; CHECK:       # %bb.0:3549; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma3550; CHECK-NEXT:    vrol.vx v10, v8, a03551; CHECK-NEXT:    vadd.vv v8, v10, v83552; CHECK-NEXT:    ret3553  %1 = call <vscale x 4 x i32> @llvm.riscv.vrol.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)3554  %2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)3555  ret <vscale x 4 x i32> %23556}3557 3558define <vscale x 2 x i64> @vclmul_vv(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen %vl) {3559; CHECK-LABEL: vclmul_vv:3560; CHECK:       # %bb.0:3561; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma3562; CHECK-NEXT:    vclmul.vv v10, v8, v103563; CHECK-NEXT:    vadd.vv v8, v10, v83564; CHECK-NEXT:    ret3565  %1 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen -1)3566  %2 = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %1, <vscale x 2 x i64> %a, iXLen %vl)3567  ret <vscale x 2 x i64> %23568}3569 3570define <vscale x 2 x i64> @vclmul_vx(<vscale x 2 x i64> %a, i32 %b, iXLen %vl) {3571; CHECK-LABEL: vclmul_vx:3572; CHECK:       # %bb.0:3573; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma3574; CHECK-NEXT:    vclmul.vx v10, v8, a03575; CHECK-NEXT:    vadd.vv v8, v10, v83576; CHECK-NEXT:    ret3577  %1 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i32(<vscale x 2 x i64> poison, <vscale x 2 x i64> %a, i32 %b, iXLen -1)3578  %2 = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %1, <vscale x 2 x i64> %a, iXLen %vl)3579  ret <vscale x 2 x i64> %23580}3581 3582define <vscale x 2 x i64> @vclmulh_vv(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen %vl) {3583; CHECK-LABEL: vclmulh_vv:3584; CHECK:       # %bb.0:3585; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma3586; CHECK-NEXT:    vclmulh.vv v10, v8, v103587; CHECK-NEXT:    vadd.vv v8, v10, v83588; CHECK-NEXT:    ret3589  %1 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen -1)3590  %2 = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %1, <vscale x 2 x i64> %a, iXLen %vl)3591  ret <vscale x 2 x i64> %23592}3593 3594define <vscale x 2 x i64> @vclmulh_vx(<vscale x 2 x i64> %a, i32 %b, iXLen %vl) {3595; CHECK-LABEL: vclmulh_vx:3596; CHECK:       # %bb.0:3597; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma3598; CHECK-NEXT:    vclmulh.vx v10, v8, a03599; CHECK-NEXT:    vadd.vv v8, v10, v83600; CHECK-NEXT:    ret3601  %1 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i32(<vscale x 2 x i64> poison, <vscale x 2 x i64> %a, i32 %b, iXLen -1)3602  %2 = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %1, <vscale x 2 x i64> %a, iXLen %vl)3603  ret <vscale x 2 x i64> %23604}3605