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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc %s -o - -mtriple=riscv32 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s3 4---5name: vec_instr_with_scalar_def6tracksRegLiveness: true7isSSA: true8body: |9 bb.0:10 ; CHECK-LABEL: name: vec_instr_with_scalar_def11 ; CHECK: [[PseudoVMNAND_MM_B8_:%[0-9]+]]:vr = PseudoVMNAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */12 ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 killed [[PseudoVMNAND_MM_B8_]], -1, 0 /* e8 */13 %1:vr = PseudoVMNAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */14 %2:gpr = PseudoVCPOP_M_B1 killed %1, -1, 0 /* e8 */15...16