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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck %s3; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s4 5define <vscale x 4 x i32> @different_imm_vl_with_ta(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {6; CHECK-LABEL: different_imm_vl_with_ta:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma9; CHECK-NEXT: vadd.vv v8, v10, v1210; CHECK-NEXT: vadd.vv v8, v8, v1011; CHECK-NEXT: ret12 %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 5)13 %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen 4)14 ret <vscale x 4 x i32> %w15}16 17define <vscale x 4 x i32> @vlmax_and_imm_vl_with_ta(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {18; CHECK-LABEL: vlmax_and_imm_vl_with_ta:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma21; CHECK-NEXT: vadd.vv v8, v10, v1222; CHECK-NEXT: vadd.vv v8, v8, v1023; CHECK-NEXT: ret24 %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)25 %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen 4)26 ret <vscale x 4 x i32> %w27}28 29; Not beneficial to propagate VL since VL is larger in the use side.30define <vscale x 4 x i32> @different_imm_vl_with_ta_larger_vl(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {31; CHECK-LABEL: different_imm_vl_with_ta_larger_vl:32; CHECK: # %bb.0:33; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma34; CHECK-NEXT: vadd.vv v8, v10, v1235; CHECK-NEXT: vsetivli zero, 5, e32, m2, ta, ma36; CHECK-NEXT: vadd.vv v8, v8, v1037; CHECK-NEXT: ret38 %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 4)39 %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen 5)40 ret <vscale x 4 x i32> %w41}42 43define <vscale x 4 x i32> @different_imm_reg_vl_with_ta(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {44; CHECK-LABEL: different_imm_reg_vl_with_ta:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma47; CHECK-NEXT: vadd.vv v8, v10, v1248; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma49; CHECK-NEXT: vadd.vv v8, v8, v1050; CHECK-NEXT: ret51 %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 4)52 %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen %vl1)53 ret <vscale x 4 x i32> %w54}55 56; Not beneficial to propagate VL since VL is already one.57define <vscale x 4 x i32> @different_imm_vl_with_ta_1(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {58; CHECK-LABEL: different_imm_vl_with_ta_1:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma61; CHECK-NEXT: vadd.vv v8, v10, v1262; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma63; CHECK-NEXT: vadd.vv v8, v8, v1064; CHECK-NEXT: ret65 %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 1)66 %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen %vl1)67 ret <vscale x 4 x i32> %w68}69 70; Propgate %vl2 to last instruction since it is may smaller than %vl1,71; it's still safe even %vl2 is larger than %vl1, becuase rest of the vector are72; undefined value.73define <vscale x 4 x i32> @different_vl_with_ta(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {74; CHECK-LABEL: different_vl_with_ta:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma77; CHECK-NEXT: vadd.vv v10, v8, v1078; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma79; CHECK-NEXT: vadd.vv v8, v10, v880; CHECK-NEXT: ret81 %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1)82 %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a,iXLen %vl2)83 ret <vscale x 4 x i32> %w84}85 86; We can propagate VL to a tail-undisturbed policy, provided none of its users87; are passthrus (i.e. read past VL).88define <vscale x 4 x i32> @different_vl_with_tu(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {89; CHECK-LABEL: different_vl_with_tu:90; CHECK: # %bb.0:91; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma92; CHECK-NEXT: vmv2r.v v14, v1093; CHECK-NEXT: vadd.vv v14, v10, v1294; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma95; CHECK-NEXT: vadd.vv v8, v14, v1096; CHECK-NEXT: ret97 %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1)98 %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen %vl2)99 ret <vscale x 4 x i32> %w100}101 102; We can propagate VL to a tail-undisturbed policy, provided none of its users103; are passthrus (i.e. read past VL).104define <vscale x 4 x i32> @different_imm_vl_with_tu(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {105; CHECK-LABEL: different_imm_vl_with_tu:106; CHECK: # %bb.0:107; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, ma108; CHECK-NEXT: vmv2r.v v14, v10109; CHECK-NEXT: vadd.vv v14, v10, v12110; CHECK-NEXT: vadd.vv v8, v14, v10111; CHECK-NEXT: ret112 %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 5)113 %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen 4)114 ret <vscale x 4 x i32> %w115}116 117; We can't reduce the VL as %v is used as a passthru, i.e. the elements past VL118; are demanded.119define <vscale x 4 x i32> @different_vl_as_passthru(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {120; CHECK-LABEL: different_vl_as_passthru:121; CHECK: # %bb.0:122; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma123; CHECK-NEXT: vmv2r.v v12, v8124; CHECK-NEXT: vadd.vv v12, v8, v10125; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma126; CHECK-NEXT: vadd.vv v12, v8, v10127; CHECK-NEXT: vmv2r.v v8, v12128; CHECK-NEXT: ret129 %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1)130 %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %v, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl2)131 ret <vscale x 4 x i32> %w132}133 134; We can't reduce the VL as %v is used as a passthru, i.e. the elements past VL135; are demanded.136define <vscale x 4 x i32> @different_imm_vl_as_passthru(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {137; CHECK-LABEL: different_imm_vl_as_passthru:138; CHECK: # %bb.0:139; CHECK-NEXT: vsetivli zero, 5, e32, m2, tu, ma140; CHECK-NEXT: vmv2r.v v12, v8141; CHECK-NEXT: vadd.vv v12, v8, v10142; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, ma143; CHECK-NEXT: vadd.vv v12, v8, v10144; CHECK-NEXT: vmv2r.v v8, v12145; CHECK-NEXT: ret146 %v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 5)147 %w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %v, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 4)148 ret <vscale x 4 x i32> %w149}150 151define <vscale x 4 x i32> @dont_optimize_tied_def(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, iXLen %vl) {152; CHECK-LABEL: dont_optimize_tied_def:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, ma155; CHECK-NEXT: vwmacc.vv v8, v10, v11156; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma157; CHECK-NEXT: vwmacc.vv v8, v10, v11158; CHECK-NEXT: ret159 %1 = call <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.nxv4i16(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, iXLen -1, iXLen 0)160 %2 = call <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.nxv4i16(<vscale x 4 x i32> %1, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, iXLen %vl, iXLen 0)161 ret <vscale x 4 x i32> %2162}163 164define void @optimize_ternary_use(<vscale x 4 x i16> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, ptr %p, iXLen %vl) {165; CHECK-LABEL: optimize_ternary_use:166; CHECK: # %bb.0:167; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma168; CHECK-NEXT: vzext.vf2 v14, v8169; CHECK-NEXT: vmadd.vv v14, v10, v12170; CHECK-NEXT: vse32.v v14, (a0)171; CHECK-NEXT: ret172 %1 = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>173 %2 = mul <vscale x 4 x i32> %b, %1174 %3 = add <vscale x 4 x i32> %2, %c175 call void @llvm.riscv.vse(<vscale x 4 x i32> %3, ptr %p, iXLen %vl)176 ret void177}178 179; This function has a copy between two vrm2 virtual registers, make sure we can180; reduce vl between it.181define void @fadd_fcmp_select_copy(<vscale x 4 x float> %v, <vscale x 4 x i1> %c, ptr %p, iXLen %vl) {182; CHECK-LABEL: fadd_fcmp_select_copy:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma185; CHECK-NEXT: vfadd.vv v8, v8, v8186; CHECK-NEXT: fmv.w.x fa5, zero187; CHECK-NEXT: vmflt.vf v10, v8, fa5188; CHECK-NEXT: vmand.mm v10, v0, v10189; CHECK-NEXT: vse32.v v8, (a0)190; CHECK-NEXT: vsm.v v10, (a0)191; CHECK-NEXT: ret192 %fadd = fadd <vscale x 4 x float> %v, %v193 %fcmp = fcmp olt <vscale x 4 x float> %fadd, zeroinitializer194 %select = select <vscale x 4 x i1> %c, <vscale x 4 x i1> %fcmp, <vscale x 4 x i1> zeroinitializer195 call void @llvm.riscv.vse(<vscale x 4 x float> %fadd, ptr %p, iXLen %vl)196 call void @llvm.riscv.vsm(<vscale x 4 x i1> %select, ptr %p, iXLen %vl)197 ret void198}199 200define <vscale x 8 x i32> @vcompress_cmp(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, iXLen %vl) {201; CHECK-LABEL: vcompress_cmp:202; CHECK: # %bb.0:203; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma204; CHECK-NEXT: vmseq.vv v20, v8, v12205; CHECK-NEXT: vcompress.vm v8, v16, v20206; CHECK-NEXT: ret207 %cmp = icmp eq <vscale x 8 x i32> %a, %b208 %compress = call <vscale x 8 x i32> @llvm.riscv.vcompress.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> %c, <vscale x 8 x i1> %cmp, iXLen %vl)209 ret <vscale x 8 x i32> %compress210}211 212define <vscale x 8 x i32> @vcompress_add(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i1> %c, iXLen %vl) {213; CHECK-LABEL: vcompress_add:214; CHECK: # %bb.0:215; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma216; CHECK-NEXT: vadd.vv v12, v8, v12217; CHECK-NEXT: vcompress.vm v8, v12, v0218; CHECK-NEXT: ret219 %add = add <vscale x 8 x i32> %a, %b220 %compress = call <vscale x 8 x i32> @llvm.riscv.vcompress.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> %add, <vscale x 8 x i1> %c, iXLen %vl)221 ret <vscale x 8 x i32> %compress222}223 224; Make sure we peek through INSERT_SUBREG of tuple registers.225define void @segmented_store_insert_subreg(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, ptr %p, iXLen %vl) {226; CHECK-LABEL: segmented_store_insert_subreg:227; CHECK: # %bb.0:228; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma229; CHECK-NEXT: vfadd.vv v10, v8, v10230; CHECK-NEXT: vsseg3e32.v v8, (a0)231; CHECK-NEXT: ret232 %fadd = fadd <vscale x 4 x float> %v0, %v1233 %t0 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.tuple.insert(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, <vscale x 4 x float> %v0, i32 0)234 %t1 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.tuple.insert(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %t0, <vscale x 4 x float> %fadd, i32 1)235 %t2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.tuple.insert(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %t1, <vscale x 4 x float> %v2, i32 2)236 call void @llvm.riscv.vsseg3(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %t2, ptr %p, iXLen %vl, iXLen 5)237 ret void238}239 240define void @recurrence(<vscale x 4 x i32> %v, ptr %p, iXLen %n, iXLen %vl) {241; CHECK-LABEL: recurrence:242; CHECK: # %bb.0: # %entry243; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma244; CHECK-NEXT: vmv.v.i v10, 0245; CHECK-NEXT: .LBB16_1: # %loop246; CHECK-NEXT: # =>This Inner Loop Header: Depth=1247; CHECK-NEXT: addi a1, a1, -1248; CHECK-NEXT: vadd.vv v10, v10, v8249; CHECK-NEXT: bnez a1, .LBB16_1250; CHECK-NEXT: # %bb.2: # %exit251; CHECK-NEXT: vse32.v v10, (a0)252; CHECK-NEXT: ret253entry:254 br label %loop255loop:256 %iv = phi iXLen [ 0, %entry ], [ %iv.next, %loop ]257 %phi = phi <vscale x 4 x i32> [ zeroinitializer, %entry ], [ %x, %loop ]258 %x = add <vscale x 4 x i32> %phi, %v259 %iv.next = add iXLen %iv, 1260 %done = icmp eq iXLen %iv.next, %n261 br i1 %done, label %exit, label %loop262exit:263 call void @llvm.riscv.vse(<vscale x 4 x i32> %x, ptr %p, iXLen %vl)264 ret void265}266 267define void @recurrence_vleff(<vscale x 4 x i32> %v, ptr %p, iXLen %n, iXLen %vl) {268; CHECK-LABEL: recurrence_vleff:269; CHECK: # %bb.0: # %entry270; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma271; CHECK-NEXT: vmv.v.i v8, 0272; CHECK-NEXT: mv a3, a0273; CHECK-NEXT: .LBB17_1: # %loop274; CHECK-NEXT: # =>This Inner Loop Header: Depth=1275; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma276; CHECK-NEXT: vle32ff.v v10, (a3)277; CHECK-NEXT: addi a1, a1, -1278; CHECK-NEXT: vadd.vv v8, v8, v10279; CHECK-NEXT: vse32.v v8, (a0)280; CHECK-NEXT: addi a3, a3, 4281; CHECK-NEXT: bnez a1, .LBB17_1282; CHECK-NEXT: # %bb.2: # %exit283; CHECK-NEXT: ret284entry:285 br label %loop286loop:287 %iv = phi iXLen [ 0, %entry ], [ %iv.next, %loop ]288 %phi = phi <vscale x 4 x i32> [ zeroinitializer, %entry ], [ %y, %loop ]289 %gep = getelementptr i32, ptr %p, iXLen %iv290 %vleff = call { <vscale x 4 x i32>, iXLen } @llvm.riscv.vleff(<vscale x 4 x i32> poison, ptr %gep, iXLen %vl)291 %vleff.x = extractvalue { <vscale x 4 x i32>, iXLen } %vleff, 0292 %vleff.vl = extractvalue { <vscale x 4 x i32>, iXLen } %vleff, 1293 %y = add <vscale x 4 x i32> %phi, %vleff.x294 call void @llvm.riscv.vse(<vscale x 4 x i32> %y, ptr %p, iXLen %vleff.vl)295 %iv.next = add iXLen %iv, 1296 %done = icmp eq iXLen %iv.next, %n297 br i1 %done, label %exit, label %loop298exit:299 ret void300}301 302define <vscale x 4 x i32> @join(<vscale x 4 x i32> %v, i1 %cond, iXLen %vl) {303; CHECK-LABEL: join:304; CHECK: # %bb.0: # %entry305; CHECK-NEXT: andi a0, a0, 1306; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, ma307; CHECK-NEXT: vadd.vi v8, v8, 1308; CHECK-NEXT: beqz a0, .LBB18_2309; CHECK-NEXT: # %bb.1: # %foo310; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma311; CHECK-NEXT: vadd.vi v8, v8, 1312; CHECK-NEXT: ret313; CHECK-NEXT: .LBB18_2: # %bar314; CHECK-NEXT: vadd.vi v8, v8, 2315; CHECK-NEXT: ret316entry:317 %a = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, iXLen 1, iXLen -1)318 br i1 %cond, label %foo, label %bar319foo:320 %b = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 1, iXLen 1)321 ret <vscale x 4 x i32> %b322bar:323 %c = call <vscale x 4 x i32> @llvm.riscv.vadd(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 2, iXLen 2)324 ret <vscale x 4 x i32> %c325}326 327; The vsmul.vx ends up dead, but doesn't get deleted before RISCVVLOptimizer. Make328; sure we don't crash when we handle it.329; TODO: DeadMachineInstructionElim should remove the dead vsmul.vx.330define <vscale x 2 x i64> @dead_vsmul() {331; CHECK-LABEL: dead_vsmul:332; CHECK: # %bb.0: # %entry333; CHECK-NEXT: vsetivli zero, 0, e16, mf2, ta, ma334; CHECK-NEXT: vmv.v.i v10, 0335; CHECK-NEXT: csrwi vxrm, 0336; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma337; CHECK-NEXT: vmv.v.i v8, 0338; CHECK-NEXT: vsetivli zero, 0, e64, m2, tu, ma339; CHECK-NEXT: vmv.v.v v8, v8340; CHECK-NEXT: vsetvli zero, zero, e16, mf2, tu, ma341; CHECK-NEXT: vsmul.vx v10, v10, zero342; CHECK-NEXT: ret343entry:344 %0 = call <vscale x 2 x i16> @llvm.riscv.vsmul(<vscale x 2 x i16> zeroinitializer, <vscale x 2 x i16> zeroinitializer, i16 0, iXLen 0, iXLen 0)345 %1 = call <vscale x 2 x i32> @llvm.riscv.vwmacc(<vscale x 2 x i32> zeroinitializer, i16 0, <vscale x 2 x i16> %0, iXLen 0, iXLen 0)346 %2 = call <vscale x 2 x i64> @llvm.riscv.vwmul(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> %1, <vscale x 2 x i32> zeroinitializer, iXLen 0)347 %3 = call <vscale x 2 x i64> @llvm.riscv.vmerge(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i64> %2, <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), iXLen 0)348 349 ret <vscale x 2 x i64> %3350}351